1/* 2 * Linux performance counter support for MIPS. 3 * 4 * Copyright (C) 2010 MIPS Technologies, Inc. 5 * Copyright (C) 2011 Cavium Networks, Inc. 6 * Author: Deng-Cheng Zhu 7 * 8 * This code is based on the implementation for ARM, which is in turn 9 * based on the sparc64 perf event code and the x86 code. Performance 10 * counter access is based on the MIPS Oprofile code. And the callchain 11 * support references the code of MIPS stacktrace.c. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18#include <linux/cpumask.h> 19#include <linux/interrupt.h> 20#include <linux/smp.h> 21#include <linux/kernel.h> 22#include <linux/perf_event.h> 23#include <linux/uaccess.h> 24 25#include <asm/irq.h> 26#include <asm/irq_regs.h> 27#include <asm/stacktrace.h> 28#include <asm/time.h> /* For perf_irq */ 29 30#define MIPS_MAX_HWEVENTS 4 31#define MIPS_TCS_PER_COUNTER 2 32#define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1) 33 34struct cpu_hw_events { 35 /* Array of events on this cpu. */ 36 struct perf_event *events[MIPS_MAX_HWEVENTS]; 37 38 /* 39 * Set the bit (indexed by the counter number) when the counter 40 * is used for an event. 41 */ 42 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; 43 44 /* 45 * Software copy of the control register for each performance counter. 46 * MIPS CPUs vary in performance counters. They use this differently, 47 * and even may not use it. 48 */ 49 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; 50}; 51DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { 52 .saved_ctrl = {0}, 53}; 54 55/* The description of MIPS performance events. */ 56struct mips_perf_event { 57 unsigned int event_id; 58 /* 59 * MIPS performance counters are indexed starting from 0. 60 * CNTR_EVEN indicates the indexes of the counters to be used are 61 * even numbers. 62 */ 63 unsigned int cntr_mask; 64 #define CNTR_EVEN 0x55555555 65 #define CNTR_ODD 0xaaaaaaaa 66 #define CNTR_ALL 0xffffffff 67#ifdef CONFIG_MIPS_MT_SMP 68 enum { 69 T = 0, 70 V = 1, 71 P = 2, 72 } range; 73#else 74 #define T 75 #define V 76 #define P 77#endif 78}; 79 80static struct mips_perf_event raw_event; 81static DEFINE_MUTEX(raw_event_mutex); 82 83#define C(x) PERF_COUNT_HW_CACHE_##x 84 85struct mips_pmu { 86 u64 max_period; 87 u64 valid_count; 88 u64 overflow; 89 const char *name; 90 int irq; 91 u64 (*read_counter)(unsigned int idx); 92 void (*write_counter)(unsigned int idx, u64 val); 93 const struct mips_perf_event *(*map_raw_event)(u64 config); 94 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; 95 const struct mips_perf_event (*cache_event_map) 96 [PERF_COUNT_HW_CACHE_MAX] 97 [PERF_COUNT_HW_CACHE_OP_MAX] 98 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 99 unsigned int num_counters; 100}; 101 102static struct mips_pmu mipspmu; 103 104#define M_CONFIG1_PC (1 << 4) 105 106#define M_PERFCTL_EXL (1 << 0) 107#define M_PERFCTL_KERNEL (1 << 1) 108#define M_PERFCTL_SUPERVISOR (1 << 2) 109#define M_PERFCTL_USER (1 << 3) 110#define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) 111#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) 112#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 113 114#ifdef CONFIG_CPU_BMIPS5000 115#define M_PERFCTL_MT_EN(filter) 0 116#else /* !CONFIG_CPU_BMIPS5000 */ 117#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 118#endif /* CONFIG_CPU_BMIPS5000 */ 119 120#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 121#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) 122#define M_TC_EN_TC M_PERFCTL_MT_EN(2) 123#define M_PERFCTL_TCID(tcid) ((tcid) << 22) 124#define M_PERFCTL_WIDE (1 << 30) 125#define M_PERFCTL_MORE (1 << 31) 126#define M_PERFCTL_TC (1 << 30) 127 128#define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ 129 M_PERFCTL_KERNEL | \ 130 M_PERFCTL_USER | \ 131 M_PERFCTL_SUPERVISOR | \ 132 M_PERFCTL_INTERRUPT_ENABLE) 133 134#ifdef CONFIG_MIPS_MT_SMP 135#define M_PERFCTL_CONFIG_MASK 0x3fff801f 136#else 137#define M_PERFCTL_CONFIG_MASK 0x1f 138#endif 139#define M_PERFCTL_EVENT_MASK 0xfe0 140 141 142#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 143static int cpu_has_mipsmt_pertccounters; 144 145static DEFINE_RWLOCK(pmuint_rwlock); 146 147#if defined(CONFIG_CPU_BMIPS5000) 148#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 149 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK)) 150#else 151/* 152 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because 153 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. 154 */ 155#define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 156 0 : smp_processor_id()) 157#endif 158 159/* Copied from op_model_mipsxx.c */ 160static unsigned int vpe_shift(void) 161{ 162 if (num_possible_cpus() > 1) 163 return 1; 164 165 return 0; 166} 167 168static unsigned int counters_total_to_per_cpu(unsigned int counters) 169{ 170 return counters >> vpe_shift(); 171} 172 173#else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */ 174#define vpe_id() 0 175 176#endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */ 177 178static void resume_local_counters(void); 179static void pause_local_counters(void); 180static irqreturn_t mipsxx_pmu_handle_irq(int, void *); 181static int mipsxx_pmu_handle_shared_irq(void); 182 183static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) 184{ 185 if (vpe_id() == 1) 186 idx = (idx + 2) & 3; 187 return idx; 188} 189 190static u64 mipsxx_pmu_read_counter(unsigned int idx) 191{ 192 idx = mipsxx_pmu_swizzle_perf_idx(idx); 193 194 switch (idx) { 195 case 0: 196 /* 197 * The counters are unsigned, we must cast to truncate 198 * off the high bits. 199 */ 200 return (u32)read_c0_perfcntr0(); 201 case 1: 202 return (u32)read_c0_perfcntr1(); 203 case 2: 204 return (u32)read_c0_perfcntr2(); 205 case 3: 206 return (u32)read_c0_perfcntr3(); 207 default: 208 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 209 return 0; 210 } 211} 212 213static u64 mipsxx_pmu_read_counter_64(unsigned int idx) 214{ 215 idx = mipsxx_pmu_swizzle_perf_idx(idx); 216 217 switch (idx) { 218 case 0: 219 return read_c0_perfcntr0_64(); 220 case 1: 221 return read_c0_perfcntr1_64(); 222 case 2: 223 return read_c0_perfcntr2_64(); 224 case 3: 225 return read_c0_perfcntr3_64(); 226 default: 227 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 228 return 0; 229 } 230} 231 232static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) 233{ 234 idx = mipsxx_pmu_swizzle_perf_idx(idx); 235 236 switch (idx) { 237 case 0: 238 write_c0_perfcntr0(val); 239 return; 240 case 1: 241 write_c0_perfcntr1(val); 242 return; 243 case 2: 244 write_c0_perfcntr2(val); 245 return; 246 case 3: 247 write_c0_perfcntr3(val); 248 return; 249 } 250} 251 252static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) 253{ 254 idx = mipsxx_pmu_swizzle_perf_idx(idx); 255 256 switch (idx) { 257 case 0: 258 write_c0_perfcntr0_64(val); 259 return; 260 case 1: 261 write_c0_perfcntr1_64(val); 262 return; 263 case 2: 264 write_c0_perfcntr2_64(val); 265 return; 266 case 3: 267 write_c0_perfcntr3_64(val); 268 return; 269 } 270} 271 272static unsigned int mipsxx_pmu_read_control(unsigned int idx) 273{ 274 idx = mipsxx_pmu_swizzle_perf_idx(idx); 275 276 switch (idx) { 277 case 0: 278 return read_c0_perfctrl0(); 279 case 1: 280 return read_c0_perfctrl1(); 281 case 2: 282 return read_c0_perfctrl2(); 283 case 3: 284 return read_c0_perfctrl3(); 285 default: 286 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 287 return 0; 288 } 289} 290 291static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) 292{ 293 idx = mipsxx_pmu_swizzle_perf_idx(idx); 294 295 switch (idx) { 296 case 0: 297 write_c0_perfctrl0(val); 298 return; 299 case 1: 300 write_c0_perfctrl1(val); 301 return; 302 case 2: 303 write_c0_perfctrl2(val); 304 return; 305 case 3: 306 write_c0_perfctrl3(val); 307 return; 308 } 309} 310 311static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, 312 struct hw_perf_event *hwc) 313{ 314 int i; 315 316 /* 317 * We only need to care the counter mask. The range has been 318 * checked definitely. 319 */ 320 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; 321 322 for (i = mipspmu.num_counters - 1; i >= 0; i--) { 323 /* 324 * Note that some MIPS perf events can be counted by both 325 * even and odd counters, wheresas many other are only by 326 * even _or_ odd counters. This introduces an issue that 327 * when the former kind of event takes the counter the 328 * latter kind of event wants to use, then the "counter 329 * allocation" for the latter event will fail. In fact if 330 * they can be dynamically swapped, they both feel happy. 331 * But here we leave this issue alone for now. 332 */ 333 if (test_bit(i, &cntr_mask) && 334 !test_and_set_bit(i, cpuc->used_mask)) 335 return i; 336 } 337 338 return -EAGAIN; 339} 340 341static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) 342{ 343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 344 345 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 346 347 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | 348 (evt->config_base & M_PERFCTL_CONFIG_MASK) | 349 /* Make sure interrupt enabled. */ 350 M_PERFCTL_INTERRUPT_ENABLE; 351 if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) 352 /* enable the counter for the calling thread */ 353 cpuc->saved_ctrl[idx] |= 354 (1 << (12 + vpe_id())) | M_PERFCTL_TC; 355 356 /* 357 * We do not actually let the counter run. Leave it until start(). 358 */ 359} 360 361static void mipsxx_pmu_disable_event(int idx) 362{ 363 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 364 unsigned long flags; 365 366 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 367 368 local_irq_save(flags); 369 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & 370 ~M_PERFCTL_COUNT_EVENT_WHENEVER; 371 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); 372 local_irq_restore(flags); 373} 374 375static int mipspmu_event_set_period(struct perf_event *event, 376 struct hw_perf_event *hwc, 377 int idx) 378{ 379 u64 left = local64_read(&hwc->period_left); 380 u64 period = hwc->sample_period; 381 int ret = 0; 382 383 if (unlikely((left + period) & (1ULL << 63))) { 384 /* left underflowed by more than period. */ 385 left = period; 386 local64_set(&hwc->period_left, left); 387 hwc->last_period = period; 388 ret = 1; 389 } else if (unlikely((left + period) <= period)) { 390 /* left underflowed by less than period. */ 391 left += period; 392 local64_set(&hwc->period_left, left); 393 hwc->last_period = period; 394 ret = 1; 395 } 396 397 if (left > mipspmu.max_period) { 398 left = mipspmu.max_period; 399 local64_set(&hwc->period_left, left); 400 } 401 402 local64_set(&hwc->prev_count, mipspmu.overflow - left); 403 404 mipspmu.write_counter(idx, mipspmu.overflow - left); 405 406 perf_event_update_userpage(event); 407 408 return ret; 409} 410 411static void mipspmu_event_update(struct perf_event *event, 412 struct hw_perf_event *hwc, 413 int idx) 414{ 415 u64 prev_raw_count, new_raw_count; 416 u64 delta; 417 418again: 419 prev_raw_count = local64_read(&hwc->prev_count); 420 new_raw_count = mipspmu.read_counter(idx); 421 422 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 423 new_raw_count) != prev_raw_count) 424 goto again; 425 426 delta = new_raw_count - prev_raw_count; 427 428 local64_add(delta, &event->count); 429 local64_sub(delta, &hwc->period_left); 430} 431 432static void mipspmu_start(struct perf_event *event, int flags) 433{ 434 struct hw_perf_event *hwc = &event->hw; 435 436 if (flags & PERF_EF_RELOAD) 437 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); 438 439 hwc->state = 0; 440 441 /* Set the period for the event. */ 442 mipspmu_event_set_period(event, hwc, hwc->idx); 443 444 /* Enable the event. */ 445 mipsxx_pmu_enable_event(hwc, hwc->idx); 446} 447 448static void mipspmu_stop(struct perf_event *event, int flags) 449{ 450 struct hw_perf_event *hwc = &event->hw; 451 452 if (!(hwc->state & PERF_HES_STOPPED)) { 453 /* We are working on a local event. */ 454 mipsxx_pmu_disable_event(hwc->idx); 455 barrier(); 456 mipspmu_event_update(event, hwc, hwc->idx); 457 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 458 } 459} 460 461static int mipspmu_add(struct perf_event *event, int flags) 462{ 463 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 464 struct hw_perf_event *hwc = &event->hw; 465 int idx; 466 int err = 0; 467 468 perf_pmu_disable(event->pmu); 469 470 /* To look for a free counter for this event. */ 471 idx = mipsxx_pmu_alloc_counter(cpuc, hwc); 472 if (idx < 0) { 473 err = idx; 474 goto out; 475 } 476 477 /* 478 * If there is an event in the counter we are going to use then 479 * make sure it is disabled. 480 */ 481 event->hw.idx = idx; 482 mipsxx_pmu_disable_event(idx); 483 cpuc->events[idx] = event; 484 485 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 486 if (flags & PERF_EF_START) 487 mipspmu_start(event, PERF_EF_RELOAD); 488 489 /* Propagate our changes to the userspace mapping. */ 490 perf_event_update_userpage(event); 491 492out: 493 perf_pmu_enable(event->pmu); 494 return err; 495} 496 497static void mipspmu_del(struct perf_event *event, int flags) 498{ 499 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 500 struct hw_perf_event *hwc = &event->hw; 501 int idx = hwc->idx; 502 503 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 504 505 mipspmu_stop(event, PERF_EF_UPDATE); 506 cpuc->events[idx] = NULL; 507 clear_bit(idx, cpuc->used_mask); 508 509 perf_event_update_userpage(event); 510} 511 512static void mipspmu_read(struct perf_event *event) 513{ 514 struct hw_perf_event *hwc = &event->hw; 515 516 /* Don't read disabled counters! */ 517 if (hwc->idx < 0) 518 return; 519 520 mipspmu_event_update(event, hwc, hwc->idx); 521} 522 523static void mipspmu_enable(struct pmu *pmu) 524{ 525#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 526 write_unlock(&pmuint_rwlock); 527#endif 528 resume_local_counters(); 529} 530 531/* 532 * MIPS performance counters can be per-TC. The control registers can 533 * not be directly accessed accross CPUs. Hence if we want to do global 534 * control, we need cross CPU calls. on_each_cpu() can help us, but we 535 * can not make sure this function is called with interrupts enabled. So 536 * here we pause local counters and then grab a rwlock and leave the 537 * counters on other CPUs alone. If any counter interrupt raises while 538 * we own the write lock, simply pause local counters on that CPU and 539 * spin in the handler. Also we know we won't be switched to another 540 * CPU after pausing local counters and before grabbing the lock. 541 */ 542static void mipspmu_disable(struct pmu *pmu) 543{ 544 pause_local_counters(); 545#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 546 write_lock(&pmuint_rwlock); 547#endif 548} 549 550static atomic_t active_events = ATOMIC_INIT(0); 551static DEFINE_MUTEX(pmu_reserve_mutex); 552static int (*save_perf_irq)(void); 553 554static int mipspmu_get_irq(void) 555{ 556 int err; 557 558 if (mipspmu.irq >= 0) { 559 /* Request my own irq handler. */ 560 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, 561 IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD, 562 "mips_perf_pmu", NULL); 563 if (err) { 564 pr_warning("Unable to request IRQ%d for MIPS " 565 "performance counters!\n", mipspmu.irq); 566 } 567 } else if (cp0_perfcount_irq < 0) { 568 /* 569 * We are sharing the irq number with the timer interrupt. 570 */ 571 save_perf_irq = perf_irq; 572 perf_irq = mipsxx_pmu_handle_shared_irq; 573 err = 0; 574 } else { 575 pr_warning("The platform hasn't properly defined its " 576 "interrupt controller.\n"); 577 err = -ENOENT; 578 } 579 580 return err; 581} 582 583static void mipspmu_free_irq(void) 584{ 585 if (mipspmu.irq >= 0) 586 free_irq(mipspmu.irq, NULL); 587 else if (cp0_perfcount_irq < 0) 588 perf_irq = save_perf_irq; 589} 590 591/* 592 * mipsxx/rm9000/loongson2 have different performance counters, they have 593 * specific low-level init routines. 594 */ 595static void reset_counters(void *arg); 596static int __hw_perf_event_init(struct perf_event *event); 597 598static void hw_perf_event_destroy(struct perf_event *event) 599{ 600 if (atomic_dec_and_mutex_lock(&active_events, 601 &pmu_reserve_mutex)) { 602 /* 603 * We must not call the destroy function with interrupts 604 * disabled. 605 */ 606 on_each_cpu(reset_counters, 607 (void *)(long)mipspmu.num_counters, 1); 608 mipspmu_free_irq(); 609 mutex_unlock(&pmu_reserve_mutex); 610 } 611} 612 613static int mipspmu_event_init(struct perf_event *event) 614{ 615 int err = 0; 616 617 /* does not support taken branch sampling */ 618 if (has_branch_stack(event)) 619 return -EOPNOTSUPP; 620 621 switch (event->attr.type) { 622 case PERF_TYPE_RAW: 623 case PERF_TYPE_HARDWARE: 624 case PERF_TYPE_HW_CACHE: 625 break; 626 627 default: 628 return -ENOENT; 629 } 630 631 if (event->cpu >= nr_cpumask_bits || 632 (event->cpu >= 0 && !cpu_online(event->cpu))) 633 return -ENODEV; 634 635 if (!atomic_inc_not_zero(&active_events)) { 636 mutex_lock(&pmu_reserve_mutex); 637 if (atomic_read(&active_events) == 0) 638 err = mipspmu_get_irq(); 639 640 if (!err) 641 atomic_inc(&active_events); 642 mutex_unlock(&pmu_reserve_mutex); 643 } 644 645 if (err) 646 return err; 647 648 return __hw_perf_event_init(event); 649} 650 651static struct pmu pmu = { 652 .pmu_enable = mipspmu_enable, 653 .pmu_disable = mipspmu_disable, 654 .event_init = mipspmu_event_init, 655 .add = mipspmu_add, 656 .del = mipspmu_del, 657 .start = mipspmu_start, 658 .stop = mipspmu_stop, 659 .read = mipspmu_read, 660}; 661 662static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) 663{ 664/* 665 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for 666 * event_id. 667 */ 668#ifdef CONFIG_MIPS_MT_SMP 669 return ((unsigned int)pev->range << 24) | 670 (pev->cntr_mask & 0xffff00) | 671 (pev->event_id & 0xff); 672#else 673 return (pev->cntr_mask & 0xffff00) | 674 (pev->event_id & 0xff); 675#endif 676} 677 678static const struct mips_perf_event *mipspmu_map_general_event(int idx) 679{ 680 681 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0) 682 return ERR_PTR(-EOPNOTSUPP); 683 return &(*mipspmu.general_event_map)[idx]; 684} 685 686static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) 687{ 688 unsigned int cache_type, cache_op, cache_result; 689 const struct mips_perf_event *pev; 690 691 cache_type = (config >> 0) & 0xff; 692 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 693 return ERR_PTR(-EINVAL); 694 695 cache_op = (config >> 8) & 0xff; 696 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 697 return ERR_PTR(-EINVAL); 698 699 cache_result = (config >> 16) & 0xff; 700 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 701 return ERR_PTR(-EINVAL); 702 703 pev = &((*mipspmu.cache_event_map) 704 [cache_type] 705 [cache_op] 706 [cache_result]); 707 708 if (pev->cntr_mask == 0) 709 return ERR_PTR(-EOPNOTSUPP); 710 711 return pev; 712 713} 714 715static int validate_group(struct perf_event *event) 716{ 717 struct perf_event *sibling, *leader = event->group_leader; 718 struct cpu_hw_events fake_cpuc; 719 720 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); 721 722 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) 723 return -EINVAL; 724 725 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 726 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) 727 return -EINVAL; 728 } 729 730 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) 731 return -EINVAL; 732 733 return 0; 734} 735 736/* This is needed by specific irq handlers in perf_event_*.c */ 737static void handle_associated_event(struct cpu_hw_events *cpuc, 738 int idx, struct perf_sample_data *data, 739 struct pt_regs *regs) 740{ 741 struct perf_event *event = cpuc->events[idx]; 742 struct hw_perf_event *hwc = &event->hw; 743 744 mipspmu_event_update(event, hwc, idx); 745 data->period = event->hw.last_period; 746 if (!mipspmu_event_set_period(event, hwc, idx)) 747 return; 748 749 if (perf_event_overflow(event, data, regs)) 750 mipsxx_pmu_disable_event(idx); 751} 752 753 754static int __n_counters(void) 755{ 756 if (!(read_c0_config1() & M_CONFIG1_PC)) 757 return 0; 758 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) 759 return 1; 760 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) 761 return 2; 762 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) 763 return 3; 764 765 return 4; 766} 767 768static int n_counters(void) 769{ 770 int counters; 771 772 switch (current_cpu_type()) { 773 case CPU_R10000: 774 counters = 2; 775 break; 776 777 case CPU_R12000: 778 case CPU_R14000: 779 counters = 4; 780 break; 781 782 default: 783 counters = __n_counters(); 784 } 785 786 return counters; 787} 788 789static void reset_counters(void *arg) 790{ 791 int counters = (int)(long)arg; 792 switch (counters) { 793 case 4: 794 mipsxx_pmu_write_control(3, 0); 795 mipspmu.write_counter(3, 0); 796 case 3: 797 mipsxx_pmu_write_control(2, 0); 798 mipspmu.write_counter(2, 0); 799 case 2: 800 mipsxx_pmu_write_control(1, 0); 801 mipspmu.write_counter(1, 0); 802 case 1: 803 mipsxx_pmu_write_control(0, 0); 804 mipspmu.write_counter(0, 0); 805 } 806} 807 808/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */ 809static const struct mips_perf_event mipsxxcore_event_map 810 [PERF_COUNT_HW_MAX] = { 811 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 812 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 813 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, 814 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, 815}; 816 817/* 74K/proAptiv core has different branch event code. */ 818static const struct mips_perf_event mipsxxcore_event_map2 819 [PERF_COUNT_HW_MAX] = { 820 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 821 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 822 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, 823 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, 824}; 825 826static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { 827 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 828 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, 829 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, 830 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, 831 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, 832 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, 833 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, 834}; 835 836static const struct mips_perf_event bmips5000_event_map 837 [PERF_COUNT_HW_MAX] = { 838 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T }, 839 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 840 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, 841}; 842 843static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { 844 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 845 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */ 846 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ 847 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ 848 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ 849 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ 850}; 851 852/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */ 853static const struct mips_perf_event mipsxxcore_cache_map 854 [PERF_COUNT_HW_CACHE_MAX] 855 [PERF_COUNT_HW_CACHE_OP_MAX] 856 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 857[C(L1D)] = { 858 /* 859 * Like some other architectures (e.g. ARM), the performance 860 * counters don't differentiate between read and write 861 * accesses/misses, so this isn't strictly correct, but it's the 862 * best we can do. Writes and reads get combined. 863 */ 864 [C(OP_READ)] = { 865 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 866 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 867 }, 868 [C(OP_WRITE)] = { 869 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 870 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 871 }, 872}, 873[C(L1I)] = { 874 [C(OP_READ)] = { 875 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, 876 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, 877 }, 878 [C(OP_WRITE)] = { 879 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, 880 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, 881 }, 882 [C(OP_PREFETCH)] = { 883 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, 884 /* 885 * Note that MIPS has only "hit" events countable for 886 * the prefetch operation. 887 */ 888 }, 889}, 890[C(LL)] = { 891 [C(OP_READ)] = { 892 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 893 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 894 }, 895 [C(OP_WRITE)] = { 896 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 897 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 898 }, 899}, 900[C(DTLB)] = { 901 [C(OP_READ)] = { 902 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 903 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 904 }, 905 [C(OP_WRITE)] = { 906 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 907 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 908 }, 909}, 910[C(ITLB)] = { 911 [C(OP_READ)] = { 912 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 913 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 914 }, 915 [C(OP_WRITE)] = { 916 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 917 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 918 }, 919}, 920[C(BPU)] = { 921 /* Using the same code for *HW_BRANCH* */ 922 [C(OP_READ)] = { 923 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 924 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 925 }, 926 [C(OP_WRITE)] = { 927 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 928 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 929 }, 930}, 931}; 932 933/* 74K/proAptiv core has completely different cache event map. */ 934static const struct mips_perf_event mipsxxcore_cache_map2 935 [PERF_COUNT_HW_CACHE_MAX] 936 [PERF_COUNT_HW_CACHE_OP_MAX] 937 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 938[C(L1D)] = { 939 /* 940 * Like some other architectures (e.g. ARM), the performance 941 * counters don't differentiate between read and write 942 * accesses/misses, so this isn't strictly correct, but it's the 943 * best we can do. Writes and reads get combined. 944 */ 945 [C(OP_READ)] = { 946 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 947 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 948 }, 949 [C(OP_WRITE)] = { 950 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 951 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 952 }, 953}, 954[C(L1I)] = { 955 [C(OP_READ)] = { 956 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 957 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 958 }, 959 [C(OP_WRITE)] = { 960 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 961 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 962 }, 963 [C(OP_PREFETCH)] = { 964 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, 965 /* 966 * Note that MIPS has only "hit" events countable for 967 * the prefetch operation. 968 */ 969 }, 970}, 971[C(LL)] = { 972 [C(OP_READ)] = { 973 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 974 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, 975 }, 976 [C(OP_WRITE)] = { 977 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 978 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, 979 }, 980}, 981/* 982 * 74K core does not have specific DTLB events. proAptiv core has 983 * "speculative" DTLB events which are numbered 0x63 (even/odd) and 984 * not included here. One can use raw events if really needed. 985 */ 986[C(ITLB)] = { 987 [C(OP_READ)] = { 988 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 989 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 990 }, 991 [C(OP_WRITE)] = { 992 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 993 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 994 }, 995}, 996[C(BPU)] = { 997 /* Using the same code for *HW_BRANCH* */ 998 [C(OP_READ)] = { 999 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 1000 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 1001 }, 1002 [C(OP_WRITE)] = { 1003 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 1004 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 1005 }, 1006}, 1007}; 1008 1009/* BMIPS5000 */ 1010static const struct mips_perf_event bmips5000_cache_map 1011 [PERF_COUNT_HW_CACHE_MAX] 1012 [PERF_COUNT_HW_CACHE_OP_MAX] 1013 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1014[C(L1D)] = { 1015 /* 1016 * Like some other architectures (e.g. ARM), the performance 1017 * counters don't differentiate between read and write 1018 * accesses/misses, so this isn't strictly correct, but it's the 1019 * best we can do. Writes and reads get combined. 1020 */ 1021 [C(OP_READ)] = { 1022 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, 1023 [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, 1024 }, 1025 [C(OP_WRITE)] = { 1026 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, 1027 [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, 1028 }, 1029}, 1030[C(L1I)] = { 1031 [C(OP_READ)] = { 1032 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, 1033 [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, 1034 }, 1035 [C(OP_WRITE)] = { 1036 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, 1037 [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, 1038 }, 1039 [C(OP_PREFETCH)] = { 1040 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T }, 1041 /* 1042 * Note that MIPS has only "hit" events countable for 1043 * the prefetch operation. 1044 */ 1045 }, 1046}, 1047[C(LL)] = { 1048 [C(OP_READ)] = { 1049 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, 1050 [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, 1051 }, 1052 [C(OP_WRITE)] = { 1053 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, 1054 [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, 1055 }, 1056}, 1057[C(BPU)] = { 1058 /* Using the same code for *HW_BRANCH* */ 1059 [C(OP_READ)] = { 1060 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 1061 }, 1062 [C(OP_WRITE)] = { 1063 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 1064 }, 1065}, 1066}; 1067 1068 1069static const struct mips_perf_event octeon_cache_map 1070 [PERF_COUNT_HW_CACHE_MAX] 1071 [PERF_COUNT_HW_CACHE_OP_MAX] 1072 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1073[C(L1D)] = { 1074 [C(OP_READ)] = { 1075 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, 1076 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, 1077 }, 1078 [C(OP_WRITE)] = { 1079 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, 1080 }, 1081}, 1082[C(L1I)] = { 1083 [C(OP_READ)] = { 1084 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, 1085 }, 1086 [C(OP_PREFETCH)] = { 1087 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, 1088 }, 1089}, 1090[C(DTLB)] = { 1091 /* 1092 * Only general DTLB misses are counted use the same event for 1093 * read and write. 1094 */ 1095 [C(OP_READ)] = { 1096 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1097 }, 1098 [C(OP_WRITE)] = { 1099 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1100 }, 1101}, 1102[C(ITLB)] = { 1103 [C(OP_READ)] = { 1104 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, 1105 }, 1106}, 1107}; 1108 1109static const struct mips_perf_event xlp_cache_map 1110 [PERF_COUNT_HW_CACHE_MAX] 1111 [PERF_COUNT_HW_CACHE_OP_MAX] 1112 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1113[C(L1D)] = { 1114 [C(OP_READ)] = { 1115 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */ 1116 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */ 1117 }, 1118 [C(OP_WRITE)] = { 1119 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ 1120 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ 1121 }, 1122}, 1123[C(L1I)] = { 1124 [C(OP_READ)] = { 1125 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ 1126 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ 1127 }, 1128}, 1129[C(LL)] = { 1130 [C(OP_READ)] = { 1131 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */ 1132 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */ 1133 }, 1134 [C(OP_WRITE)] = { 1135 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ 1136 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ 1137 }, 1138}, 1139[C(DTLB)] = { 1140 /* 1141 * Only general DTLB misses are counted use the same event for 1142 * read and write. 1143 */ 1144 [C(OP_READ)] = { 1145 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ 1146 }, 1147 [C(OP_WRITE)] = { 1148 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ 1149 }, 1150}, 1151[C(ITLB)] = { 1152 [C(OP_READ)] = { 1153 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ 1154 }, 1155 [C(OP_WRITE)] = { 1156 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ 1157 }, 1158}, 1159[C(BPU)] = { 1160 [C(OP_READ)] = { 1161 [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, 1162 }, 1163}, 1164}; 1165 1166#ifdef CONFIG_MIPS_MT_SMP 1167static void check_and_calc_range(struct perf_event *event, 1168 const struct mips_perf_event *pev) 1169{ 1170 struct hw_perf_event *hwc = &event->hw; 1171 1172 if (event->cpu >= 0) { 1173 if (pev->range > V) { 1174 /* 1175 * The user selected an event that is processor 1176 * wide, while expecting it to be VPE wide. 1177 */ 1178 hwc->config_base |= M_TC_EN_ALL; 1179 } else { 1180 /* 1181 * FIXME: cpu_data[event->cpu].vpe_id reports 0 1182 * for both CPUs. 1183 */ 1184 hwc->config_base |= M_PERFCTL_VPEID(event->cpu); 1185 hwc->config_base |= M_TC_EN_VPE; 1186 } 1187 } else 1188 hwc->config_base |= M_TC_EN_ALL; 1189} 1190#else 1191static void check_and_calc_range(struct perf_event *event, 1192 const struct mips_perf_event *pev) 1193{ 1194} 1195#endif 1196 1197static int __hw_perf_event_init(struct perf_event *event) 1198{ 1199 struct perf_event_attr *attr = &event->attr; 1200 struct hw_perf_event *hwc = &event->hw; 1201 const struct mips_perf_event *pev; 1202 int err; 1203 1204 /* Returning MIPS event descriptor for generic perf event. */ 1205 if (PERF_TYPE_HARDWARE == event->attr.type) { 1206 if (event->attr.config >= PERF_COUNT_HW_MAX) 1207 return -EINVAL; 1208 pev = mipspmu_map_general_event(event->attr.config); 1209 } else if (PERF_TYPE_HW_CACHE == event->attr.type) { 1210 pev = mipspmu_map_cache_event(event->attr.config); 1211 } else if (PERF_TYPE_RAW == event->attr.type) { 1212 /* We are working on the global raw event. */ 1213 mutex_lock(&raw_event_mutex); 1214 pev = mipspmu.map_raw_event(event->attr.config); 1215 } else { 1216 /* The event type is not (yet) supported. */ 1217 return -EOPNOTSUPP; 1218 } 1219 1220 if (IS_ERR(pev)) { 1221 if (PERF_TYPE_RAW == event->attr.type) 1222 mutex_unlock(&raw_event_mutex); 1223 return PTR_ERR(pev); 1224 } 1225 1226 /* 1227 * We allow max flexibility on how each individual counter shared 1228 * by the single CPU operates (the mode exclusion and the range). 1229 */ 1230 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; 1231 1232 /* Calculate range bits and validate it. */ 1233 if (num_possible_cpus() > 1) 1234 check_and_calc_range(event, pev); 1235 1236 hwc->event_base = mipspmu_perf_event_encode(pev); 1237 if (PERF_TYPE_RAW == event->attr.type) 1238 mutex_unlock(&raw_event_mutex); 1239 1240 if (!attr->exclude_user) 1241 hwc->config_base |= M_PERFCTL_USER; 1242 if (!attr->exclude_kernel) { 1243 hwc->config_base |= M_PERFCTL_KERNEL; 1244 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ 1245 hwc->config_base |= M_PERFCTL_EXL; 1246 } 1247 if (!attr->exclude_hv) 1248 hwc->config_base |= M_PERFCTL_SUPERVISOR; 1249 1250 hwc->config_base &= M_PERFCTL_CONFIG_MASK; 1251 /* 1252 * The event can belong to another cpu. We do not assign a local 1253 * counter for it for now. 1254 */ 1255 hwc->idx = -1; 1256 hwc->config = 0; 1257 1258 if (!hwc->sample_period) { 1259 hwc->sample_period = mipspmu.max_period; 1260 hwc->last_period = hwc->sample_period; 1261 local64_set(&hwc->period_left, hwc->sample_period); 1262 } 1263 1264 err = 0; 1265 if (event->group_leader != event) 1266 err = validate_group(event); 1267 1268 event->destroy = hw_perf_event_destroy; 1269 1270 if (err) 1271 event->destroy(event); 1272 1273 return err; 1274} 1275 1276static void pause_local_counters(void) 1277{ 1278 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1279 int ctr = mipspmu.num_counters; 1280 unsigned long flags; 1281 1282 local_irq_save(flags); 1283 do { 1284 ctr--; 1285 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); 1286 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & 1287 ~M_PERFCTL_COUNT_EVENT_WHENEVER); 1288 } while (ctr > 0); 1289 local_irq_restore(flags); 1290} 1291 1292static void resume_local_counters(void) 1293{ 1294 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1295 int ctr = mipspmu.num_counters; 1296 1297 do { 1298 ctr--; 1299 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); 1300 } while (ctr > 0); 1301} 1302 1303static int mipsxx_pmu_handle_shared_irq(void) 1304{ 1305 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1306 struct perf_sample_data data; 1307 unsigned int counters = mipspmu.num_counters; 1308 u64 counter; 1309 int handled = IRQ_NONE; 1310 struct pt_regs *regs; 1311 1312 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) 1313 return handled; 1314 /* 1315 * First we pause the local counters, so that when we are locked 1316 * here, the counters are all paused. When it gets locked due to 1317 * perf_disable(), the timer interrupt handler will be delayed. 1318 * 1319 * See also mipsxx_pmu_start(). 1320 */ 1321 pause_local_counters(); 1322#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 1323 read_lock(&pmuint_rwlock); 1324#endif 1325 1326 regs = get_irq_regs(); 1327 1328 perf_sample_data_init(&data, 0, 0); 1329 1330 switch (counters) { 1331#define HANDLE_COUNTER(n) \ 1332 case n + 1: \ 1333 if (test_bit(n, cpuc->used_mask)) { \ 1334 counter = mipspmu.read_counter(n); \ 1335 if (counter & mipspmu.overflow) { \ 1336 handle_associated_event(cpuc, n, &data, regs); \ 1337 handled = IRQ_HANDLED; \ 1338 } \ 1339 } 1340 HANDLE_COUNTER(3) 1341 HANDLE_COUNTER(2) 1342 HANDLE_COUNTER(1) 1343 HANDLE_COUNTER(0) 1344 } 1345 1346 /* 1347 * Do all the work for the pending perf events. We can do this 1348 * in here because the performance counter interrupt is a regular 1349 * interrupt, not NMI. 1350 */ 1351 if (handled == IRQ_HANDLED) 1352 irq_work_run(); 1353 1354#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 1355 read_unlock(&pmuint_rwlock); 1356#endif 1357 resume_local_counters(); 1358 return handled; 1359} 1360 1361static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) 1362{ 1363 return mipsxx_pmu_handle_shared_irq(); 1364} 1365 1366/* 24K */ 1367#define IS_BOTH_COUNTERS_24K_EVENT(b) \ 1368 ((b) == 0 || (b) == 1 || (b) == 11) 1369 1370/* 34K */ 1371#define IS_BOTH_COUNTERS_34K_EVENT(b) \ 1372 ((b) == 0 || (b) == 1 || (b) == 11) 1373#ifdef CONFIG_MIPS_MT_SMP 1374#define IS_RANGE_P_34K_EVENT(r, b) \ 1375 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1376 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ 1377 (r) == 176 || ((b) >= 50 && (b) <= 55) || \ 1378 ((b) >= 64 && (b) <= 67)) 1379#define IS_RANGE_V_34K_EVENT(r) ((r) == 47) 1380#endif 1381 1382/* 74K */ 1383#define IS_BOTH_COUNTERS_74K_EVENT(b) \ 1384 ((b) == 0 || (b) == 1) 1385 1386/* proAptiv */ 1387#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \ 1388 ((b) == 0 || (b) == 1) 1389/* P5600 */ 1390#define IS_BOTH_COUNTERS_P5600_EVENT(b) \ 1391 ((b) == 0 || (b) == 1) 1392 1393/* 1004K */ 1394#define IS_BOTH_COUNTERS_1004K_EVENT(b) \ 1395 ((b) == 0 || (b) == 1 || (b) == 11) 1396#ifdef CONFIG_MIPS_MT_SMP 1397#define IS_RANGE_P_1004K_EVENT(r, b) \ 1398 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1399 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \ 1400 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \ 1401 (r) == 188 || (b) == 61 || (b) == 62 || \ 1402 ((b) >= 64 && (b) <= 67)) 1403#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) 1404#endif 1405 1406/* interAptiv */ 1407#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \ 1408 ((b) == 0 || (b) == 1 || (b) == 11) 1409#ifdef CONFIG_MIPS_MT_SMP 1410/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */ 1411#define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \ 1412 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1413 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \ 1414 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \ 1415 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \ 1416 ((b) >= 64 && (b) <= 67)) 1417#define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175) 1418#endif 1419 1420/* BMIPS5000 */ 1421#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \ 1422 ((b) == 0 || (b) == 1) 1423 1424 1425/* 1426 * For most cores the user can use 0-255 raw events, where 0-127 for the events 1427 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to 1428 * indicate the even/odd bank selector. So, for example, when user wants to take 1429 * the Event Num of 15 for odd counters (by referring to the user manual), then 1430 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F) 1431 * to be used. 1432 * 1433 * Some newer cores have even more events, in which case the user can use raw 1434 * events 0-511, where 0-255 are for the events of even counters, and 256-511 1435 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector. 1436 */ 1437static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 1438{ 1439 /* currently most cores have 7-bit event numbers */ 1440 unsigned int raw_id = config & 0xff; 1441 unsigned int base_id = raw_id & 0x7f; 1442 1443 switch (current_cpu_type()) { 1444 case CPU_24K: 1445 if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) 1446 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1447 else 1448 raw_event.cntr_mask = 1449 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1450#ifdef CONFIG_MIPS_MT_SMP 1451 /* 1452 * This is actually doing nothing. Non-multithreading 1453 * CPUs will not check and calculate the range. 1454 */ 1455 raw_event.range = P; 1456#endif 1457 break; 1458 case CPU_34K: 1459 if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) 1460 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1461 else 1462 raw_event.cntr_mask = 1463 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1464#ifdef CONFIG_MIPS_MT_SMP 1465 if (IS_RANGE_P_34K_EVENT(raw_id, base_id)) 1466 raw_event.range = P; 1467 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id))) 1468 raw_event.range = V; 1469 else 1470 raw_event.range = T; 1471#endif 1472 break; 1473 case CPU_74K: 1474 case CPU_1074K: 1475 if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) 1476 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1477 else 1478 raw_event.cntr_mask = 1479 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1480#ifdef CONFIG_MIPS_MT_SMP 1481 raw_event.range = P; 1482#endif 1483 break; 1484 case CPU_PROAPTIV: 1485 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id)) 1486 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1487 else 1488 raw_event.cntr_mask = 1489 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1490#ifdef CONFIG_MIPS_MT_SMP 1491 raw_event.range = P; 1492#endif 1493 break; 1494 case CPU_P5600: 1495 /* 8-bit event numbers */ 1496 raw_id = config & 0x1ff; 1497 base_id = raw_id & 0xff; 1498 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id)) 1499 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1500 else 1501 raw_event.cntr_mask = 1502 raw_id > 255 ? CNTR_ODD : CNTR_EVEN; 1503#ifdef CONFIG_MIPS_MT_SMP 1504 raw_event.range = P; 1505#endif 1506 break; 1507 case CPU_1004K: 1508 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) 1509 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1510 else 1511 raw_event.cntr_mask = 1512 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1513#ifdef CONFIG_MIPS_MT_SMP 1514 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id)) 1515 raw_event.range = P; 1516 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id))) 1517 raw_event.range = V; 1518 else 1519 raw_event.range = T; 1520#endif 1521 break; 1522 case CPU_INTERAPTIV: 1523 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id)) 1524 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1525 else 1526 raw_event.cntr_mask = 1527 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1528#ifdef CONFIG_MIPS_MT_SMP 1529 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id)) 1530 raw_event.range = P; 1531 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id))) 1532 raw_event.range = V; 1533 else 1534 raw_event.range = T; 1535#endif 1536 break; 1537 case CPU_BMIPS5000: 1538 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id)) 1539 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1540 else 1541 raw_event.cntr_mask = 1542 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1543 } 1544 1545 raw_event.event_id = base_id; 1546 1547 return &raw_event; 1548} 1549 1550static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) 1551{ 1552 unsigned int raw_id = config & 0xff; 1553 unsigned int base_id = raw_id & 0x7f; 1554 1555 1556 raw_event.cntr_mask = CNTR_ALL; 1557 raw_event.event_id = base_id; 1558 1559 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { 1560 if (base_id > 0x42) 1561 return ERR_PTR(-EOPNOTSUPP); 1562 } else { 1563 if (base_id > 0x3a) 1564 return ERR_PTR(-EOPNOTSUPP); 1565 } 1566 1567 switch (base_id) { 1568 case 0x00: 1569 case 0x0f: 1570 case 0x1e: 1571 case 0x1f: 1572 case 0x2f: 1573 case 0x34: 1574 case 0x3b ... 0x3f: 1575 return ERR_PTR(-EOPNOTSUPP); 1576 default: 1577 break; 1578 } 1579 1580 return &raw_event; 1581} 1582 1583static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config) 1584{ 1585 unsigned int raw_id = config & 0xff; 1586 1587 /* Only 1-63 are defined */ 1588 if ((raw_id < 0x01) || (raw_id > 0x3f)) 1589 return ERR_PTR(-EOPNOTSUPP); 1590 1591 raw_event.cntr_mask = CNTR_ALL; 1592 raw_event.event_id = raw_id; 1593 1594 return &raw_event; 1595} 1596 1597static int __init 1598init_hw_perf_events(void) 1599{ 1600 int counters, irq; 1601 int counter_bits; 1602 1603 pr_info("Performance counters: "); 1604 1605 counters = n_counters(); 1606 if (counters == 0) { 1607 pr_cont("No available PMU.\n"); 1608 return -ENODEV; 1609 } 1610 1611#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 1612 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); 1613 if (!cpu_has_mipsmt_pertccounters) 1614 counters = counters_total_to_per_cpu(counters); 1615#endif 1616 1617#ifdef MSC01E_INT_BASE 1618 if (cpu_has_veic) { 1619 /* 1620 * Using platform specific interrupt controller defines. 1621 */ 1622 irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 1623 } else { 1624#endif 1625 if ((cp0_perfcount_irq >= 0) && 1626 (cp0_compare_irq != cp0_perfcount_irq)) 1627 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 1628 else 1629 irq = -1; 1630#ifdef MSC01E_INT_BASE 1631 } 1632#endif 1633 1634 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; 1635 1636 switch (current_cpu_type()) { 1637 case CPU_24K: 1638 mipspmu.name = "mips/24K"; 1639 mipspmu.general_event_map = &mipsxxcore_event_map; 1640 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1641 break; 1642 case CPU_34K: 1643 mipspmu.name = "mips/34K"; 1644 mipspmu.general_event_map = &mipsxxcore_event_map; 1645 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1646 break; 1647 case CPU_74K: 1648 mipspmu.name = "mips/74K"; 1649 mipspmu.general_event_map = &mipsxxcore_event_map2; 1650 mipspmu.cache_event_map = &mipsxxcore_cache_map2; 1651 break; 1652 case CPU_PROAPTIV: 1653 mipspmu.name = "mips/proAptiv"; 1654 mipspmu.general_event_map = &mipsxxcore_event_map2; 1655 mipspmu.cache_event_map = &mipsxxcore_cache_map2; 1656 break; 1657 case CPU_P5600: 1658 mipspmu.name = "mips/P5600"; 1659 mipspmu.general_event_map = &mipsxxcore_event_map2; 1660 mipspmu.cache_event_map = &mipsxxcore_cache_map2; 1661 break; 1662 case CPU_1004K: 1663 mipspmu.name = "mips/1004K"; 1664 mipspmu.general_event_map = &mipsxxcore_event_map; 1665 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1666 break; 1667 case CPU_1074K: 1668 mipspmu.name = "mips/1074K"; 1669 mipspmu.general_event_map = &mipsxxcore_event_map; 1670 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1671 break; 1672 case CPU_INTERAPTIV: 1673 mipspmu.name = "mips/interAptiv"; 1674 mipspmu.general_event_map = &mipsxxcore_event_map; 1675 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1676 break; 1677 case CPU_LOONGSON1: 1678 mipspmu.name = "mips/loongson1"; 1679 mipspmu.general_event_map = &mipsxxcore_event_map; 1680 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1681 break; 1682 case CPU_CAVIUM_OCTEON: 1683 case CPU_CAVIUM_OCTEON_PLUS: 1684 case CPU_CAVIUM_OCTEON2: 1685 mipspmu.name = "octeon"; 1686 mipspmu.general_event_map = &octeon_event_map; 1687 mipspmu.cache_event_map = &octeon_cache_map; 1688 mipspmu.map_raw_event = octeon_pmu_map_raw_event; 1689 break; 1690 case CPU_BMIPS5000: 1691 mipspmu.name = "BMIPS5000"; 1692 mipspmu.general_event_map = &bmips5000_event_map; 1693 mipspmu.cache_event_map = &bmips5000_cache_map; 1694 break; 1695 case CPU_XLP: 1696 mipspmu.name = "xlp"; 1697 mipspmu.general_event_map = &xlp_event_map; 1698 mipspmu.cache_event_map = &xlp_cache_map; 1699 mipspmu.map_raw_event = xlp_pmu_map_raw_event; 1700 break; 1701 default: 1702 pr_cont("Either hardware does not support performance " 1703 "counters, or not yet implemented.\n"); 1704 return -ENODEV; 1705 } 1706 1707 mipspmu.num_counters = counters; 1708 mipspmu.irq = irq; 1709 1710 if (read_c0_perfctrl0() & M_PERFCTL_WIDE) { 1711 mipspmu.max_period = (1ULL << 63) - 1; 1712 mipspmu.valid_count = (1ULL << 63) - 1; 1713 mipspmu.overflow = 1ULL << 63; 1714 mipspmu.read_counter = mipsxx_pmu_read_counter_64; 1715 mipspmu.write_counter = mipsxx_pmu_write_counter_64; 1716 counter_bits = 64; 1717 } else { 1718 mipspmu.max_period = (1ULL << 31) - 1; 1719 mipspmu.valid_count = (1ULL << 31) - 1; 1720 mipspmu.overflow = 1ULL << 31; 1721 mipspmu.read_counter = mipsxx_pmu_read_counter; 1722 mipspmu.write_counter = mipsxx_pmu_write_counter; 1723 counter_bits = 32; 1724 } 1725 1726 on_each_cpu(reset_counters, (void *)(long)counters, 1); 1727 1728 pr_cont("%s PMU enabled, %d %d-bit counters available to each " 1729 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, 1730 irq < 0 ? " (share with timer interrupt)" : ""); 1731 1732 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1733 1734 return 0; 1735} 1736early_initcall(init_hw_perf_events); 1737