cp1emu.c revision 70e4c234aa48e11c0575364939dfab4cb27b2172
1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware FPU at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an FPU, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36#include <linux/sched.h> 37#include <linux/debugfs.h> 38#include <linux/kconfig.h> 39#include <linux/percpu-defs.h> 40#include <linux/perf_event.h> 41 42#include <asm/branch.h> 43#include <asm/inst.h> 44#include <asm/ptrace.h> 45#include <asm/signal.h> 46#include <asm/uaccess.h> 47 48#include <asm/processor.h> 49#include <asm/fpu_emulator.h> 50#include <asm/fpu.h> 51 52#include "ieee754.h" 53 54/* Function which emulates a floating point instruction. */ 55 56static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 57 mips_instruction); 58 59static int fpux_emu(struct pt_regs *, 60 struct mips_fpu_struct *, mips_instruction, void *__user *); 61 62/* Control registers */ 63 64#define FPCREG_RID 0 /* $0 = revision id */ 65#define FPCREG_CSR 31 /* $31 = csr */ 66 67/* Determine rounding mode from the RM bits of the FCSR */ 68#define modeindex(v) ((v) & FPU_CSR_RM) 69 70/* convert condition code register number to csr bit */ 71static const unsigned int fpucondbit[8] = { 72 FPU_CSR_COND0, 73 FPU_CSR_COND1, 74 FPU_CSR_COND2, 75 FPU_CSR_COND3, 76 FPU_CSR_COND4, 77 FPU_CSR_COND5, 78 FPU_CSR_COND6, 79 FPU_CSR_COND7 80}; 81 82/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 83static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 84static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 85static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 86static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 87 88/* 89 * This functions translates a 32-bit microMIPS instruction 90 * into a 32-bit MIPS32 instruction. Returns 0 on success 91 * and SIGILL otherwise. 92 */ 93static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 94{ 95 union mips_instruction insn = *insn_ptr; 96 union mips_instruction mips32_insn = insn; 97 int func, fmt, op; 98 99 switch (insn.mm_i_format.opcode) { 100 case mm_ldc132_op: 101 mips32_insn.mm_i_format.opcode = ldc1_op; 102 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 103 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 104 break; 105 case mm_lwc132_op: 106 mips32_insn.mm_i_format.opcode = lwc1_op; 107 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 108 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 109 break; 110 case mm_sdc132_op: 111 mips32_insn.mm_i_format.opcode = sdc1_op; 112 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 113 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 114 break; 115 case mm_swc132_op: 116 mips32_insn.mm_i_format.opcode = swc1_op; 117 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 118 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 119 break; 120 case mm_pool32i_op: 121 /* NOTE: offset is << by 1 if in microMIPS mode. */ 122 if ((insn.mm_i_format.rt == mm_bc1f_op) || 123 (insn.mm_i_format.rt == mm_bc1t_op)) { 124 mips32_insn.fb_format.opcode = cop1_op; 125 mips32_insn.fb_format.bc = bc_op; 126 mips32_insn.fb_format.flag = 127 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 128 } else 129 return SIGILL; 130 break; 131 case mm_pool32f_op: 132 switch (insn.mm_fp0_format.func) { 133 case mm_32f_01_op: 134 case mm_32f_11_op: 135 case mm_32f_02_op: 136 case mm_32f_12_op: 137 case mm_32f_41_op: 138 case mm_32f_51_op: 139 case mm_32f_42_op: 140 case mm_32f_52_op: 141 op = insn.mm_fp0_format.func; 142 if (op == mm_32f_01_op) 143 func = madd_s_op; 144 else if (op == mm_32f_11_op) 145 func = madd_d_op; 146 else if (op == mm_32f_02_op) 147 func = nmadd_s_op; 148 else if (op == mm_32f_12_op) 149 func = nmadd_d_op; 150 else if (op == mm_32f_41_op) 151 func = msub_s_op; 152 else if (op == mm_32f_51_op) 153 func = msub_d_op; 154 else if (op == mm_32f_42_op) 155 func = nmsub_s_op; 156 else 157 func = nmsub_d_op; 158 mips32_insn.fp6_format.opcode = cop1x_op; 159 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 160 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 161 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 162 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 163 mips32_insn.fp6_format.func = func; 164 break; 165 case mm_32f_10_op: 166 func = -1; /* Invalid */ 167 op = insn.mm_fp5_format.op & 0x7; 168 if (op == mm_ldxc1_op) 169 func = ldxc1_op; 170 else if (op == mm_sdxc1_op) 171 func = sdxc1_op; 172 else if (op == mm_lwxc1_op) 173 func = lwxc1_op; 174 else if (op == mm_swxc1_op) 175 func = swxc1_op; 176 177 if (func != -1) { 178 mips32_insn.r_format.opcode = cop1x_op; 179 mips32_insn.r_format.rs = 180 insn.mm_fp5_format.base; 181 mips32_insn.r_format.rt = 182 insn.mm_fp5_format.index; 183 mips32_insn.r_format.rd = 0; 184 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 185 mips32_insn.r_format.func = func; 186 } else 187 return SIGILL; 188 break; 189 case mm_32f_40_op: 190 op = -1; /* Invalid */ 191 if (insn.mm_fp2_format.op == mm_fmovt_op) 192 op = 1; 193 else if (insn.mm_fp2_format.op == mm_fmovf_op) 194 op = 0; 195 if (op != -1) { 196 mips32_insn.fp0_format.opcode = cop1_op; 197 mips32_insn.fp0_format.fmt = 198 sdps_format[insn.mm_fp2_format.fmt]; 199 mips32_insn.fp0_format.ft = 200 (insn.mm_fp2_format.cc<<2) + op; 201 mips32_insn.fp0_format.fs = 202 insn.mm_fp2_format.fs; 203 mips32_insn.fp0_format.fd = 204 insn.mm_fp2_format.fd; 205 mips32_insn.fp0_format.func = fmovc_op; 206 } else 207 return SIGILL; 208 break; 209 case mm_32f_60_op: 210 func = -1; /* Invalid */ 211 if (insn.mm_fp0_format.op == mm_fadd_op) 212 func = fadd_op; 213 else if (insn.mm_fp0_format.op == mm_fsub_op) 214 func = fsub_op; 215 else if (insn.mm_fp0_format.op == mm_fmul_op) 216 func = fmul_op; 217 else if (insn.mm_fp0_format.op == mm_fdiv_op) 218 func = fdiv_op; 219 if (func != -1) { 220 mips32_insn.fp0_format.opcode = cop1_op; 221 mips32_insn.fp0_format.fmt = 222 sdps_format[insn.mm_fp0_format.fmt]; 223 mips32_insn.fp0_format.ft = 224 insn.mm_fp0_format.ft; 225 mips32_insn.fp0_format.fs = 226 insn.mm_fp0_format.fs; 227 mips32_insn.fp0_format.fd = 228 insn.mm_fp0_format.fd; 229 mips32_insn.fp0_format.func = func; 230 } else 231 return SIGILL; 232 break; 233 case mm_32f_70_op: 234 func = -1; /* Invalid */ 235 if (insn.mm_fp0_format.op == mm_fmovn_op) 236 func = fmovn_op; 237 else if (insn.mm_fp0_format.op == mm_fmovz_op) 238 func = fmovz_op; 239 if (func != -1) { 240 mips32_insn.fp0_format.opcode = cop1_op; 241 mips32_insn.fp0_format.fmt = 242 sdps_format[insn.mm_fp0_format.fmt]; 243 mips32_insn.fp0_format.ft = 244 insn.mm_fp0_format.ft; 245 mips32_insn.fp0_format.fs = 246 insn.mm_fp0_format.fs; 247 mips32_insn.fp0_format.fd = 248 insn.mm_fp0_format.fd; 249 mips32_insn.fp0_format.func = func; 250 } else 251 return SIGILL; 252 break; 253 case mm_32f_73_op: /* POOL32FXF */ 254 switch (insn.mm_fp1_format.op) { 255 case mm_movf0_op: 256 case mm_movf1_op: 257 case mm_movt0_op: 258 case mm_movt1_op: 259 if ((insn.mm_fp1_format.op & 0x7f) == 260 mm_movf0_op) 261 op = 0; 262 else 263 op = 1; 264 mips32_insn.r_format.opcode = spec_op; 265 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 266 mips32_insn.r_format.rt = 267 (insn.mm_fp4_format.cc << 2) + op; 268 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 269 mips32_insn.r_format.re = 0; 270 mips32_insn.r_format.func = movc_op; 271 break; 272 case mm_fcvtd0_op: 273 case mm_fcvtd1_op: 274 case mm_fcvts0_op: 275 case mm_fcvts1_op: 276 if ((insn.mm_fp1_format.op & 0x7f) == 277 mm_fcvtd0_op) { 278 func = fcvtd_op; 279 fmt = swl_format[insn.mm_fp3_format.fmt]; 280 } else { 281 func = fcvts_op; 282 fmt = dwl_format[insn.mm_fp3_format.fmt]; 283 } 284 mips32_insn.fp0_format.opcode = cop1_op; 285 mips32_insn.fp0_format.fmt = fmt; 286 mips32_insn.fp0_format.ft = 0; 287 mips32_insn.fp0_format.fs = 288 insn.mm_fp3_format.fs; 289 mips32_insn.fp0_format.fd = 290 insn.mm_fp3_format.rt; 291 mips32_insn.fp0_format.func = func; 292 break; 293 case mm_fmov0_op: 294 case mm_fmov1_op: 295 case mm_fabs0_op: 296 case mm_fabs1_op: 297 case mm_fneg0_op: 298 case mm_fneg1_op: 299 if ((insn.mm_fp1_format.op & 0x7f) == 300 mm_fmov0_op) 301 func = fmov_op; 302 else if ((insn.mm_fp1_format.op & 0x7f) == 303 mm_fabs0_op) 304 func = fabs_op; 305 else 306 func = fneg_op; 307 mips32_insn.fp0_format.opcode = cop1_op; 308 mips32_insn.fp0_format.fmt = 309 sdps_format[insn.mm_fp3_format.fmt]; 310 mips32_insn.fp0_format.ft = 0; 311 mips32_insn.fp0_format.fs = 312 insn.mm_fp3_format.fs; 313 mips32_insn.fp0_format.fd = 314 insn.mm_fp3_format.rt; 315 mips32_insn.fp0_format.func = func; 316 break; 317 case mm_ffloorl_op: 318 case mm_ffloorw_op: 319 case mm_fceill_op: 320 case mm_fceilw_op: 321 case mm_ftruncl_op: 322 case mm_ftruncw_op: 323 case mm_froundl_op: 324 case mm_froundw_op: 325 case mm_fcvtl_op: 326 case mm_fcvtw_op: 327 if (insn.mm_fp1_format.op == mm_ffloorl_op) 328 func = ffloorl_op; 329 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 330 func = ffloor_op; 331 else if (insn.mm_fp1_format.op == mm_fceill_op) 332 func = fceill_op; 333 else if (insn.mm_fp1_format.op == mm_fceilw_op) 334 func = fceil_op; 335 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 336 func = ftruncl_op; 337 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 338 func = ftrunc_op; 339 else if (insn.mm_fp1_format.op == mm_froundl_op) 340 func = froundl_op; 341 else if (insn.mm_fp1_format.op == mm_froundw_op) 342 func = fround_op; 343 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 344 func = fcvtl_op; 345 else 346 func = fcvtw_op; 347 mips32_insn.fp0_format.opcode = cop1_op; 348 mips32_insn.fp0_format.fmt = 349 sd_format[insn.mm_fp1_format.fmt]; 350 mips32_insn.fp0_format.ft = 0; 351 mips32_insn.fp0_format.fs = 352 insn.mm_fp1_format.fs; 353 mips32_insn.fp0_format.fd = 354 insn.mm_fp1_format.rt; 355 mips32_insn.fp0_format.func = func; 356 break; 357 case mm_frsqrt_op: 358 case mm_fsqrt_op: 359 case mm_frecip_op: 360 if (insn.mm_fp1_format.op == mm_frsqrt_op) 361 func = frsqrt_op; 362 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 363 func = fsqrt_op; 364 else 365 func = frecip_op; 366 mips32_insn.fp0_format.opcode = cop1_op; 367 mips32_insn.fp0_format.fmt = 368 sdps_format[insn.mm_fp1_format.fmt]; 369 mips32_insn.fp0_format.ft = 0; 370 mips32_insn.fp0_format.fs = 371 insn.mm_fp1_format.fs; 372 mips32_insn.fp0_format.fd = 373 insn.mm_fp1_format.rt; 374 mips32_insn.fp0_format.func = func; 375 break; 376 case mm_mfc1_op: 377 case mm_mtc1_op: 378 case mm_cfc1_op: 379 case mm_ctc1_op: 380 case mm_mfhc1_op: 381 case mm_mthc1_op: 382 if (insn.mm_fp1_format.op == mm_mfc1_op) 383 op = mfc_op; 384 else if (insn.mm_fp1_format.op == mm_mtc1_op) 385 op = mtc_op; 386 else if (insn.mm_fp1_format.op == mm_cfc1_op) 387 op = cfc_op; 388 else if (insn.mm_fp1_format.op == mm_ctc1_op) 389 op = ctc_op; 390 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 391 op = mfhc_op; 392 else 393 op = mthc_op; 394 mips32_insn.fp1_format.opcode = cop1_op; 395 mips32_insn.fp1_format.op = op; 396 mips32_insn.fp1_format.rt = 397 insn.mm_fp1_format.rt; 398 mips32_insn.fp1_format.fs = 399 insn.mm_fp1_format.fs; 400 mips32_insn.fp1_format.fd = 0; 401 mips32_insn.fp1_format.func = 0; 402 break; 403 default: 404 return SIGILL; 405 } 406 break; 407 case mm_32f_74_op: /* c.cond.fmt */ 408 mips32_insn.fp0_format.opcode = cop1_op; 409 mips32_insn.fp0_format.fmt = 410 sdps_format[insn.mm_fp4_format.fmt]; 411 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 412 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 413 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 414 mips32_insn.fp0_format.func = 415 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 416 break; 417 default: 418 return SIGILL; 419 } 420 break; 421 default: 422 return SIGILL; 423 } 424 425 *insn_ptr = mips32_insn; 426 return 0; 427} 428 429/* 430 * Redundant with logic already in kernel/branch.c, 431 * embedded in compute_return_epc. At some point, 432 * a single subroutine should be used across both 433 * modules. 434 */ 435static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 436 unsigned long *contpc) 437{ 438 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 439 unsigned int fcr31; 440 unsigned int bit = 0; 441 442 switch (insn.i_format.opcode) { 443 case spec_op: 444 switch (insn.r_format.func) { 445 case jalr_op: 446 regs->regs[insn.r_format.rd] = 447 regs->cp0_epc + dec_insn.pc_inc + 448 dec_insn.next_pc_inc; 449 /* Fall through */ 450 case jr_op: 451 *contpc = regs->regs[insn.r_format.rs]; 452 return 1; 453 } 454 break; 455 case bcond_op: 456 switch (insn.i_format.rt) { 457 case bltzal_op: 458 case bltzall_op: 459 regs->regs[31] = regs->cp0_epc + 460 dec_insn.pc_inc + 461 dec_insn.next_pc_inc; 462 /* Fall through */ 463 case bltz_op: 464 case bltzl_op: 465 if ((long)regs->regs[insn.i_format.rs] < 0) 466 *contpc = regs->cp0_epc + 467 dec_insn.pc_inc + 468 (insn.i_format.simmediate << 2); 469 else 470 *contpc = regs->cp0_epc + 471 dec_insn.pc_inc + 472 dec_insn.next_pc_inc; 473 return 1; 474 case bgezal_op: 475 case bgezall_op: 476 regs->regs[31] = regs->cp0_epc + 477 dec_insn.pc_inc + 478 dec_insn.next_pc_inc; 479 /* Fall through */ 480 case bgez_op: 481 case bgezl_op: 482 if ((long)regs->regs[insn.i_format.rs] >= 0) 483 *contpc = regs->cp0_epc + 484 dec_insn.pc_inc + 485 (insn.i_format.simmediate << 2); 486 else 487 *contpc = regs->cp0_epc + 488 dec_insn.pc_inc + 489 dec_insn.next_pc_inc; 490 return 1; 491 } 492 break; 493 case jalx_op: 494 set_isa16_mode(bit); 495 case jal_op: 496 regs->regs[31] = regs->cp0_epc + 497 dec_insn.pc_inc + 498 dec_insn.next_pc_inc; 499 /* Fall through */ 500 case j_op: 501 *contpc = regs->cp0_epc + dec_insn.pc_inc; 502 *contpc >>= 28; 503 *contpc <<= 28; 504 *contpc |= (insn.j_format.target << 2); 505 /* Set microMIPS mode bit: XOR for jalx. */ 506 *contpc ^= bit; 507 return 1; 508 case beq_op: 509 case beql_op: 510 if (regs->regs[insn.i_format.rs] == 511 regs->regs[insn.i_format.rt]) 512 *contpc = regs->cp0_epc + 513 dec_insn.pc_inc + 514 (insn.i_format.simmediate << 2); 515 else 516 *contpc = regs->cp0_epc + 517 dec_insn.pc_inc + 518 dec_insn.next_pc_inc; 519 return 1; 520 case bne_op: 521 case bnel_op: 522 if (regs->regs[insn.i_format.rs] != 523 regs->regs[insn.i_format.rt]) 524 *contpc = regs->cp0_epc + 525 dec_insn.pc_inc + 526 (insn.i_format.simmediate << 2); 527 else 528 *contpc = regs->cp0_epc + 529 dec_insn.pc_inc + 530 dec_insn.next_pc_inc; 531 return 1; 532 case blez_op: 533 case blezl_op: 534 if ((long)regs->regs[insn.i_format.rs] <= 0) 535 *contpc = regs->cp0_epc + 536 dec_insn.pc_inc + 537 (insn.i_format.simmediate << 2); 538 else 539 *contpc = regs->cp0_epc + 540 dec_insn.pc_inc + 541 dec_insn.next_pc_inc; 542 return 1; 543 case bgtz_op: 544 case bgtzl_op: 545 if ((long)regs->regs[insn.i_format.rs] > 0) 546 *contpc = regs->cp0_epc + 547 dec_insn.pc_inc + 548 (insn.i_format.simmediate << 2); 549 else 550 *contpc = regs->cp0_epc + 551 dec_insn.pc_inc + 552 dec_insn.next_pc_inc; 553 return 1; 554#ifdef CONFIG_CPU_CAVIUM_OCTEON 555 case lwc2_op: /* This is bbit0 on Octeon */ 556 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 557 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 558 else 559 *contpc = regs->cp0_epc + 8; 560 return 1; 561 case ldc2_op: /* This is bbit032 on Octeon */ 562 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 563 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 564 else 565 *contpc = regs->cp0_epc + 8; 566 return 1; 567 case swc2_op: /* This is bbit1 on Octeon */ 568 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 569 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 570 else 571 *contpc = regs->cp0_epc + 8; 572 return 1; 573 case sdc2_op: /* This is bbit132 on Octeon */ 574 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 575 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 576 else 577 *contpc = regs->cp0_epc + 8; 578 return 1; 579#endif 580 case cop0_op: 581 case cop1_op: 582 case cop2_op: 583 case cop1x_op: 584 if (insn.i_format.rs == bc_op) { 585 preempt_disable(); 586 if (is_fpu_owner()) 587 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 588 else 589 fcr31 = current->thread.fpu.fcr31; 590 preempt_enable(); 591 592 bit = (insn.i_format.rt >> 2); 593 bit += (bit != 0); 594 bit += 23; 595 switch (insn.i_format.rt & 3) { 596 case 0: /* bc1f */ 597 case 2: /* bc1fl */ 598 if (~fcr31 & (1 << bit)) 599 *contpc = regs->cp0_epc + 600 dec_insn.pc_inc + 601 (insn.i_format.simmediate << 2); 602 else 603 *contpc = regs->cp0_epc + 604 dec_insn.pc_inc + 605 dec_insn.next_pc_inc; 606 return 1; 607 case 1: /* bc1t */ 608 case 3: /* bc1tl */ 609 if (fcr31 & (1 << bit)) 610 *contpc = regs->cp0_epc + 611 dec_insn.pc_inc + 612 (insn.i_format.simmediate << 2); 613 else 614 *contpc = regs->cp0_epc + 615 dec_insn.pc_inc + 616 dec_insn.next_pc_inc; 617 return 1; 618 } 619 } 620 break; 621 } 622 return 0; 623} 624 625/* 626 * In the Linux kernel, we support selection of FPR format on the 627 * basis of the Status.FR bit. If an FPU is not present, the FR bit 628 * is hardwired to zero, which would imply a 32-bit FPU even for 629 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 630 * FPU emu is slow and bulky and optimizing this function offers fairly 631 * sizeable benefits so we try to be clever and make this function return 632 * a constant whenever possible, that is on 64-bit kernels without O32 633 * compatibility enabled and on 32-bit without 64-bit FPU support. 634 */ 635static inline int cop1_64bit(struct pt_regs *xcp) 636{ 637 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) 638 return 1; 639 else if (config_enabled(CONFIG_32BIT) && 640 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) 641 return 0; 642 643 return !test_thread_flag(TIF_32BIT_FPREGS); 644} 645 646#define SIFROMREG(si, x) \ 647do { \ 648 if (cop1_64bit(xcp)) \ 649 (si) = get_fpr32(&ctx->fpr[x], 0); \ 650 else \ 651 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 652} while (0) 653 654#define SITOREG(si, x) \ 655do { \ 656 if (cop1_64bit(xcp)) { \ 657 unsigned i; \ 658 set_fpr32(&ctx->fpr[x], 0, si); \ 659 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 660 set_fpr32(&ctx->fpr[x], i, 0); \ 661 } else { \ 662 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 663 } \ 664} while (0) 665 666#define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) 667 668#define SITOHREG(si, x) \ 669do { \ 670 unsigned i; \ 671 set_fpr32(&ctx->fpr[x], 1, si); \ 672 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 673 set_fpr32(&ctx->fpr[x], i, 0); \ 674} while (0) 675 676#define DIFROMREG(di, x) \ 677 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 678 679#define DITOREG(di, x) \ 680do { \ 681 unsigned fpr, i; \ 682 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 683 set_fpr64(&ctx->fpr[fpr], 0, di); \ 684 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 685 set_fpr64(&ctx->fpr[fpr], i, 0); \ 686} while (0) 687 688#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 689#define SPTOREG(sp, x) SITOREG((sp).bits, x) 690#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 691#define DPTOREG(dp, x) DITOREG((dp).bits, x) 692 693/* 694 * Emulate the single floating point instruction pointed at by EPC. 695 * Two instructions if the instruction is in a branch delay slot. 696 */ 697 698static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 699 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 700{ 701 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 702 unsigned int cond, cbit; 703 mips_instruction ir; 704 int likely, pc_inc; 705 u32 __user *wva; 706 u64 __user *dva; 707 u32 value; 708 u32 wval; 709 u64 dval; 710 int sig; 711 712 /* 713 * These are giving gcc a gentle hint about what to expect in 714 * dec_inst in order to do better optimization. 715 */ 716 if (!cpu_has_mmips && dec_insn.micro_mips_mode) 717 unreachable(); 718 719 /* XXX NEC Vr54xx bug workaround */ 720 if (delay_slot(xcp)) { 721 if (dec_insn.micro_mips_mode) { 722 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 723 clear_delay_slot(xcp); 724 } else { 725 if (!isBranchInstr(xcp, dec_insn, &contpc)) 726 clear_delay_slot(xcp); 727 } 728 } 729 730 if (delay_slot(xcp)) { 731 /* 732 * The instruction to be emulated is in a branch delay slot 733 * which means that we have to emulate the branch instruction 734 * BEFORE we do the cop1 instruction. 735 * 736 * This branch could be a COP1 branch, but in that case we 737 * would have had a trap for that instruction, and would not 738 * come through this route. 739 * 740 * Linux MIPS branch emulator operates on context, updating the 741 * cp0_epc. 742 */ 743 ir = dec_insn.next_insn; /* process delay slot instr */ 744 pc_inc = dec_insn.next_pc_inc; 745 } else { 746 ir = dec_insn.insn; /* process current instr */ 747 pc_inc = dec_insn.pc_inc; 748 } 749 750 /* 751 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 752 * instructions, we want to convert microMIPS FPU instructions 753 * into MIPS32 instructions so that we could reuse all of the 754 * FPU emulation code. 755 * 756 * NOTE: We cannot do this for branch instructions since they 757 * are not a subset. Example: Cannot emulate a 16-bit 758 * aligned target address with a MIPS32 instruction. 759 */ 760 if (dec_insn.micro_mips_mode) { 761 /* 762 * If next instruction is a 16-bit instruction, then it 763 * it cannot be a FPU instruction. This could happen 764 * since we can be called for non-FPU instructions. 765 */ 766 if ((pc_inc == 2) || 767 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 768 == SIGILL)) 769 return SIGILL; 770 } 771 772emul: 773 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 774 MIPS_FPU_EMU_INC_STATS(emulated); 775 switch (MIPSInst_OPCODE(ir)) { 776 case ldc1_op: 777 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 778 MIPSInst_SIMM(ir)); 779 MIPS_FPU_EMU_INC_STATS(loads); 780 781 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) { 782 MIPS_FPU_EMU_INC_STATS(errors); 783 *fault_addr = dva; 784 return SIGBUS; 785 } 786 if (__get_user(dval, dva)) { 787 MIPS_FPU_EMU_INC_STATS(errors); 788 *fault_addr = dva; 789 return SIGSEGV; 790 } 791 DITOREG(dval, MIPSInst_RT(ir)); 792 break; 793 794 case sdc1_op: 795 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 796 MIPSInst_SIMM(ir)); 797 MIPS_FPU_EMU_INC_STATS(stores); 798 DIFROMREG(dval, MIPSInst_RT(ir)); 799 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) { 800 MIPS_FPU_EMU_INC_STATS(errors); 801 *fault_addr = dva; 802 return SIGBUS; 803 } 804 if (__put_user(dval, dva)) { 805 MIPS_FPU_EMU_INC_STATS(errors); 806 *fault_addr = dva; 807 return SIGSEGV; 808 } 809 break; 810 811 case lwc1_op: 812 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 813 MIPSInst_SIMM(ir)); 814 MIPS_FPU_EMU_INC_STATS(loads); 815 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) { 816 MIPS_FPU_EMU_INC_STATS(errors); 817 *fault_addr = wva; 818 return SIGBUS; 819 } 820 if (__get_user(wval, wva)) { 821 MIPS_FPU_EMU_INC_STATS(errors); 822 *fault_addr = wva; 823 return SIGSEGV; 824 } 825 SITOREG(wval, MIPSInst_RT(ir)); 826 break; 827 828 case swc1_op: 829 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 830 MIPSInst_SIMM(ir)); 831 MIPS_FPU_EMU_INC_STATS(stores); 832 SIFROMREG(wval, MIPSInst_RT(ir)); 833 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) { 834 MIPS_FPU_EMU_INC_STATS(errors); 835 *fault_addr = wva; 836 return SIGBUS; 837 } 838 if (__put_user(wval, wva)) { 839 MIPS_FPU_EMU_INC_STATS(errors); 840 *fault_addr = wva; 841 return SIGSEGV; 842 } 843 break; 844 845 case cop1_op: 846 switch (MIPSInst_RS(ir)) { 847 case dmfc_op: 848 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 849 return SIGILL; 850 851 /* copregister fs -> gpr[rt] */ 852 if (MIPSInst_RT(ir) != 0) { 853 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 854 MIPSInst_RD(ir)); 855 } 856 break; 857 858 case dmtc_op: 859 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 860 return SIGILL; 861 862 /* copregister fs <- rt */ 863 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 864 break; 865 866 case mfhc_op: 867 if (!cpu_has_mips_r2) 868 goto sigill; 869 870 /* copregister rd -> gpr[rt] */ 871 if (MIPSInst_RT(ir) != 0) { 872 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 873 MIPSInst_RD(ir)); 874 } 875 break; 876 877 case mthc_op: 878 if (!cpu_has_mips_r2) 879 goto sigill; 880 881 /* copregister rd <- gpr[rt] */ 882 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 883 break; 884 885 case mfc_op: 886 /* copregister rd -> gpr[rt] */ 887 if (MIPSInst_RT(ir) != 0) { 888 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 889 MIPSInst_RD(ir)); 890 } 891 break; 892 893 case mtc_op: 894 /* copregister rd <- rt */ 895 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 896 break; 897 898 case cfc_op: 899 /* cop control register rd -> gpr[rt] */ 900 if (MIPSInst_RD(ir) == FPCREG_CSR) { 901 value = ctx->fcr31; 902 value = (value & ~FPU_CSR_RM) | modeindex(value); 903 pr_debug("%p gpr[%d]<-csr=%08x\n", 904 (void *) (xcp->cp0_epc), 905 MIPSInst_RT(ir), value); 906 } 907 else if (MIPSInst_RD(ir) == FPCREG_RID) 908 value = 0; 909 else 910 value = 0; 911 if (MIPSInst_RT(ir)) 912 xcp->regs[MIPSInst_RT(ir)] = value; 913 break; 914 915 case ctc_op: 916 /* copregister rd <- rt */ 917 if (MIPSInst_RT(ir) == 0) 918 value = 0; 919 else 920 value = xcp->regs[MIPSInst_RT(ir)]; 921 922 /* we only have one writable control reg 923 */ 924 if (MIPSInst_RD(ir) == FPCREG_CSR) { 925 pr_debug("%p gpr[%d]->csr=%08x\n", 926 (void *) (xcp->cp0_epc), 927 MIPSInst_RT(ir), value); 928 929 /* 930 * Don't write reserved bits, 931 * and convert to ieee library modes 932 */ 933 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 934 modeindex(value); 935 } 936 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 937 return SIGFPE; 938 } 939 break; 940 941 case bc_op: 942 if (delay_slot(xcp)) 943 return SIGILL; 944 945 if (cpu_has_mips_4_5_r) 946 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 947 else 948 cbit = FPU_CSR_COND; 949 cond = ctx->fcr31 & cbit; 950 951 likely = 0; 952 switch (MIPSInst_RT(ir) & 3) { 953 case bcfl_op: 954 likely = 1; 955 case bcf_op: 956 cond = !cond; 957 break; 958 case bctl_op: 959 likely = 1; 960 case bct_op: 961 break; 962 default: 963 /* thats an illegal instruction */ 964 return SIGILL; 965 } 966 967 set_delay_slot(xcp); 968 if (cond) { 969 /* 970 * Branch taken: emulate dslot instruction 971 */ 972 xcp->cp0_epc += dec_insn.pc_inc; 973 974 contpc = MIPSInst_SIMM(ir); 975 ir = dec_insn.next_insn; 976 if (dec_insn.micro_mips_mode) { 977 contpc = (xcp->cp0_epc + (contpc << 1)); 978 979 /* If 16-bit instruction, not FPU. */ 980 if ((dec_insn.next_pc_inc == 2) || 981 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 982 983 /* 984 * Since this instruction will 985 * be put on the stack with 986 * 32-bit words, get around 987 * this problem by putting a 988 * NOP16 as the second one. 989 */ 990 if (dec_insn.next_pc_inc == 2) 991 ir = (ir & (~0xffff)) | MM_NOP16; 992 993 /* 994 * Single step the non-CP1 995 * instruction in the dslot. 996 */ 997 return mips_dsemul(xcp, ir, contpc); 998 } 999 } else 1000 contpc = (xcp->cp0_epc + (contpc << 2)); 1001 1002 switch (MIPSInst_OPCODE(ir)) { 1003 case lwc1_op: 1004 goto emul; 1005 1006 case swc1_op: 1007 goto emul; 1008 1009 case ldc1_op: 1010 case sdc1_op: 1011 if (cpu_has_mips_2_3_4_5 || 1012 cpu_has_mips64) 1013 goto emul; 1014 1015 return SIGILL; 1016 goto emul; 1017 1018 case cop1_op: 1019 goto emul; 1020 1021 case cop1x_op: 1022 if (cpu_has_mips_4_5 || cpu_has_mips64) 1023 /* its one of ours */ 1024 goto emul; 1025 1026 return SIGILL; 1027 1028 case spec_op: 1029 if (!cpu_has_mips_4_5_r) 1030 return SIGILL; 1031 1032 if (MIPSInst_FUNC(ir) == movc_op) 1033 goto emul; 1034 break; 1035 } 1036 1037 /* 1038 * Single step the non-cp1 1039 * instruction in the dslot 1040 */ 1041 return mips_dsemul(xcp, ir, contpc); 1042 } else if (likely) { /* branch not taken */ 1043 /* 1044 * branch likely nullifies 1045 * dslot if not taken 1046 */ 1047 xcp->cp0_epc += dec_insn.pc_inc; 1048 contpc += dec_insn.pc_inc; 1049 /* 1050 * else continue & execute 1051 * dslot as normal insn 1052 */ 1053 } 1054 break; 1055 1056 default: 1057 if (!(MIPSInst_RS(ir) & 0x10)) 1058 return SIGILL; 1059 1060 /* a real fpu computation instruction */ 1061 if ((sig = fpu_emu(xcp, ctx, ir))) 1062 return sig; 1063 } 1064 break; 1065 1066 case cop1x_op: 1067 if (!cpu_has_mips_4_5 && !cpu_has_mips64) 1068 return SIGILL; 1069 1070 sig = fpux_emu(xcp, ctx, ir, fault_addr); 1071 if (sig) 1072 return sig; 1073 break; 1074 1075 case spec_op: 1076 if (!cpu_has_mips_4_5_r) 1077 return SIGILL; 1078 1079 if (MIPSInst_FUNC(ir) != movc_op) 1080 return SIGILL; 1081 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1082 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1083 xcp->regs[MIPSInst_RD(ir)] = 1084 xcp->regs[MIPSInst_RS(ir)]; 1085 break; 1086 default: 1087sigill: 1088 return SIGILL; 1089 } 1090 1091 /* we did it !! */ 1092 xcp->cp0_epc = contpc; 1093 clear_delay_slot(xcp); 1094 1095 return 0; 1096} 1097 1098/* 1099 * Conversion table from MIPS compare ops 48-63 1100 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1101 */ 1102static const unsigned char cmptab[8] = { 1103 0, /* cmp_0 (sig) cmp_sf */ 1104 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1105 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1106 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1107 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1108 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1109 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1110 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1111}; 1112 1113 1114/* 1115 * Additional MIPS4 instructions 1116 */ 1117 1118#define DEF3OP(name, p, f1, f2, f3) \ 1119static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ 1120 union ieee754##p s, union ieee754##p t) \ 1121{ \ 1122 struct _ieee754_csr ieee754_csr_save; \ 1123 s = f1(s, t); \ 1124 ieee754_csr_save = ieee754_csr; \ 1125 s = f2(s, r); \ 1126 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1127 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1128 s = f3(s); \ 1129 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1130 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1131 return s; \ 1132} 1133 1134static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1135{ 1136 return ieee754dp_div(ieee754dp_one(0), d); 1137} 1138 1139static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1140{ 1141 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1142} 1143 1144static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1145{ 1146 return ieee754sp_div(ieee754sp_one(0), s); 1147} 1148 1149static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1150{ 1151 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1152} 1153 1154DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1155DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1156DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1157DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1158DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1159DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1160DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1161DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1162 1163static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1164 mips_instruction ir, void *__user *fault_addr) 1165{ 1166 unsigned rcsr = 0; /* resulting csr */ 1167 1168 MIPS_FPU_EMU_INC_STATS(cp1xops); 1169 1170 switch (MIPSInst_FMA_FFMT(ir)) { 1171 case s_fmt:{ /* 0 */ 1172 1173 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1174 union ieee754sp fd, fr, fs, ft; 1175 u32 __user *va; 1176 u32 val; 1177 1178 switch (MIPSInst_FUNC(ir)) { 1179 case lwxc1_op: 1180 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1181 xcp->regs[MIPSInst_FT(ir)]); 1182 1183 MIPS_FPU_EMU_INC_STATS(loads); 1184 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1185 MIPS_FPU_EMU_INC_STATS(errors); 1186 *fault_addr = va; 1187 return SIGBUS; 1188 } 1189 if (__get_user(val, va)) { 1190 MIPS_FPU_EMU_INC_STATS(errors); 1191 *fault_addr = va; 1192 return SIGSEGV; 1193 } 1194 SITOREG(val, MIPSInst_FD(ir)); 1195 break; 1196 1197 case swxc1_op: 1198 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1199 xcp->regs[MIPSInst_FT(ir)]); 1200 1201 MIPS_FPU_EMU_INC_STATS(stores); 1202 1203 SIFROMREG(val, MIPSInst_FS(ir)); 1204 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1205 MIPS_FPU_EMU_INC_STATS(errors); 1206 *fault_addr = va; 1207 return SIGBUS; 1208 } 1209 if (put_user(val, va)) { 1210 MIPS_FPU_EMU_INC_STATS(errors); 1211 *fault_addr = va; 1212 return SIGSEGV; 1213 } 1214 break; 1215 1216 case madd_s_op: 1217 handler = fpemu_sp_madd; 1218 goto scoptop; 1219 case msub_s_op: 1220 handler = fpemu_sp_msub; 1221 goto scoptop; 1222 case nmadd_s_op: 1223 handler = fpemu_sp_nmadd; 1224 goto scoptop; 1225 case nmsub_s_op: 1226 handler = fpemu_sp_nmsub; 1227 goto scoptop; 1228 1229 scoptop: 1230 SPFROMREG(fr, MIPSInst_FR(ir)); 1231 SPFROMREG(fs, MIPSInst_FS(ir)); 1232 SPFROMREG(ft, MIPSInst_FT(ir)); 1233 fd = (*handler) (fr, fs, ft); 1234 SPTOREG(fd, MIPSInst_FD(ir)); 1235 1236 copcsr: 1237 if (ieee754_cxtest(IEEE754_INEXACT)) 1238 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1239 if (ieee754_cxtest(IEEE754_UNDERFLOW)) 1240 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1241 if (ieee754_cxtest(IEEE754_OVERFLOW)) 1242 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1243 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 1244 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1245 1246 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1247 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1248 /*printk ("SIGFPE: FPU csr = %08x\n", 1249 ctx->fcr31); */ 1250 return SIGFPE; 1251 } 1252 1253 break; 1254 1255 default: 1256 return SIGILL; 1257 } 1258 break; 1259 } 1260 1261 case d_fmt:{ /* 1 */ 1262 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1263 union ieee754dp fd, fr, fs, ft; 1264 u64 __user *va; 1265 u64 val; 1266 1267 switch (MIPSInst_FUNC(ir)) { 1268 case ldxc1_op: 1269 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1270 xcp->regs[MIPSInst_FT(ir)]); 1271 1272 MIPS_FPU_EMU_INC_STATS(loads); 1273 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1274 MIPS_FPU_EMU_INC_STATS(errors); 1275 *fault_addr = va; 1276 return SIGBUS; 1277 } 1278 if (__get_user(val, va)) { 1279 MIPS_FPU_EMU_INC_STATS(errors); 1280 *fault_addr = va; 1281 return SIGSEGV; 1282 } 1283 DITOREG(val, MIPSInst_FD(ir)); 1284 break; 1285 1286 case sdxc1_op: 1287 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1288 xcp->regs[MIPSInst_FT(ir)]); 1289 1290 MIPS_FPU_EMU_INC_STATS(stores); 1291 DIFROMREG(val, MIPSInst_FS(ir)); 1292 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1293 MIPS_FPU_EMU_INC_STATS(errors); 1294 *fault_addr = va; 1295 return SIGBUS; 1296 } 1297 if (__put_user(val, va)) { 1298 MIPS_FPU_EMU_INC_STATS(errors); 1299 *fault_addr = va; 1300 return SIGSEGV; 1301 } 1302 break; 1303 1304 case madd_d_op: 1305 handler = fpemu_dp_madd; 1306 goto dcoptop; 1307 case msub_d_op: 1308 handler = fpemu_dp_msub; 1309 goto dcoptop; 1310 case nmadd_d_op: 1311 handler = fpemu_dp_nmadd; 1312 goto dcoptop; 1313 case nmsub_d_op: 1314 handler = fpemu_dp_nmsub; 1315 goto dcoptop; 1316 1317 dcoptop: 1318 DPFROMREG(fr, MIPSInst_FR(ir)); 1319 DPFROMREG(fs, MIPSInst_FS(ir)); 1320 DPFROMREG(ft, MIPSInst_FT(ir)); 1321 fd = (*handler) (fr, fs, ft); 1322 DPTOREG(fd, MIPSInst_FD(ir)); 1323 goto copcsr; 1324 1325 default: 1326 return SIGILL; 1327 } 1328 break; 1329 } 1330 1331 case 0x3: 1332 if (MIPSInst_FUNC(ir) != pfetch_op) 1333 return SIGILL; 1334 1335 /* ignore prefx operation */ 1336 break; 1337 1338 default: 1339 return SIGILL; 1340 } 1341 1342 return 0; 1343} 1344 1345 1346 1347/* 1348 * Emulate a single COP1 arithmetic instruction. 1349 */ 1350static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1351 mips_instruction ir) 1352{ 1353 int rfmt; /* resulting format */ 1354 unsigned rcsr = 0; /* resulting csr */ 1355 unsigned int oldrm; 1356 unsigned int cbit; 1357 unsigned cond; 1358 union { 1359 union ieee754dp d; 1360 union ieee754sp s; 1361 int w; 1362 s64 l; 1363 } rv; /* resulting value */ 1364 u64 bits; 1365 1366 MIPS_FPU_EMU_INC_STATS(cp1ops); 1367 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1368 case s_fmt: { /* 0 */ 1369 union { 1370 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1371 union ieee754sp(*u) (union ieee754sp); 1372 } handler; 1373 union ieee754sp fs, ft; 1374 1375 switch (MIPSInst_FUNC(ir)) { 1376 /* binary ops */ 1377 case fadd_op: 1378 handler.b = ieee754sp_add; 1379 goto scopbop; 1380 case fsub_op: 1381 handler.b = ieee754sp_sub; 1382 goto scopbop; 1383 case fmul_op: 1384 handler.b = ieee754sp_mul; 1385 goto scopbop; 1386 case fdiv_op: 1387 handler.b = ieee754sp_div; 1388 goto scopbop; 1389 1390 /* unary ops */ 1391 case fsqrt_op: 1392 if (!cpu_has_mips_4_5_r) 1393 return SIGILL; 1394 1395 handler.u = ieee754sp_sqrt; 1396 goto scopuop; 1397 1398 /* 1399 * Note that on some MIPS IV implementations such as the 1400 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1401 * achieve full IEEE-754 accuracy - however this emulator does. 1402 */ 1403 case frsqrt_op: 1404 if (!cpu_has_mips_4_5_r2) 1405 return SIGILL; 1406 1407 handler.u = fpemu_sp_rsqrt; 1408 goto scopuop; 1409 1410 case frecip_op: 1411 if (!cpu_has_mips_4_5_r2) 1412 return SIGILL; 1413 1414 handler.u = fpemu_sp_recip; 1415 goto scopuop; 1416 1417 case fmovc_op: 1418 if (!cpu_has_mips_4_5_r) 1419 return SIGILL; 1420 1421 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1422 if (((ctx->fcr31 & cond) != 0) != 1423 ((MIPSInst_FT(ir) & 1) != 0)) 1424 return 0; 1425 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1426 break; 1427 1428 case fmovz_op: 1429 if (!cpu_has_mips_4_5_r) 1430 return SIGILL; 1431 1432 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1433 return 0; 1434 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1435 break; 1436 1437 case fmovn_op: 1438 if (!cpu_has_mips_4_5_r) 1439 return SIGILL; 1440 1441 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1442 return 0; 1443 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1444 break; 1445 1446 case fabs_op: 1447 handler.u = ieee754sp_abs; 1448 goto scopuop; 1449 1450 case fneg_op: 1451 handler.u = ieee754sp_neg; 1452 goto scopuop; 1453 1454 case fmov_op: 1455 /* an easy one */ 1456 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1457 goto copcsr; 1458 1459 /* binary op on handler */ 1460scopbop: 1461 SPFROMREG(fs, MIPSInst_FS(ir)); 1462 SPFROMREG(ft, MIPSInst_FT(ir)); 1463 1464 rv.s = (*handler.b) (fs, ft); 1465 goto copcsr; 1466scopuop: 1467 SPFROMREG(fs, MIPSInst_FS(ir)); 1468 rv.s = (*handler.u) (fs); 1469 goto copcsr; 1470copcsr: 1471 if (ieee754_cxtest(IEEE754_INEXACT)) 1472 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1473 if (ieee754_cxtest(IEEE754_UNDERFLOW)) 1474 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1475 if (ieee754_cxtest(IEEE754_OVERFLOW)) 1476 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1477 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) 1478 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1479 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 1480 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1481 break; 1482 1483 /* unary conv ops */ 1484 case fcvts_op: 1485 return SIGILL; /* not defined */ 1486 1487 case fcvtd_op: 1488 SPFROMREG(fs, MIPSInst_FS(ir)); 1489 rv.d = ieee754dp_fsp(fs); 1490 rfmt = d_fmt; 1491 goto copcsr; 1492 1493 case fcvtw_op: 1494 SPFROMREG(fs, MIPSInst_FS(ir)); 1495 rv.w = ieee754sp_tint(fs); 1496 rfmt = w_fmt; 1497 goto copcsr; 1498 1499 case fround_op: 1500 case ftrunc_op: 1501 case fceil_op: 1502 case ffloor_op: 1503 if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) 1504 return SIGILL; 1505 1506 oldrm = ieee754_csr.rm; 1507 SPFROMREG(fs, MIPSInst_FS(ir)); 1508 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1509 rv.w = ieee754sp_tint(fs); 1510 ieee754_csr.rm = oldrm; 1511 rfmt = w_fmt; 1512 goto copcsr; 1513 1514 case fcvtl_op: 1515 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1516 return SIGILL; 1517 1518 SPFROMREG(fs, MIPSInst_FS(ir)); 1519 rv.l = ieee754sp_tlong(fs); 1520 rfmt = l_fmt; 1521 goto copcsr; 1522 1523 case froundl_op: 1524 case ftruncl_op: 1525 case fceill_op: 1526 case ffloorl_op: 1527 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1528 return SIGILL; 1529 1530 oldrm = ieee754_csr.rm; 1531 SPFROMREG(fs, MIPSInst_FS(ir)); 1532 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1533 rv.l = ieee754sp_tlong(fs); 1534 ieee754_csr.rm = oldrm; 1535 rfmt = l_fmt; 1536 goto copcsr; 1537 1538 default: 1539 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1540 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1541 union ieee754sp fs, ft; 1542 1543 SPFROMREG(fs, MIPSInst_FS(ir)); 1544 SPFROMREG(ft, MIPSInst_FT(ir)); 1545 rv.w = ieee754sp_cmp(fs, ft, 1546 cmptab[cmpop & 0x7], cmpop & 0x8); 1547 rfmt = -1; 1548 if ((cmpop & 0x8) && ieee754_cxtest 1549 (IEEE754_INVALID_OPERATION)) 1550 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1551 else 1552 goto copcsr; 1553 1554 } else 1555 return SIGILL; 1556 break; 1557 } 1558 break; 1559 } 1560 1561 case d_fmt: { 1562 union ieee754dp fs, ft; 1563 union { 1564 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 1565 union ieee754dp(*u) (union ieee754dp); 1566 } handler; 1567 1568 switch (MIPSInst_FUNC(ir)) { 1569 /* binary ops */ 1570 case fadd_op: 1571 handler.b = ieee754dp_add; 1572 goto dcopbop; 1573 case fsub_op: 1574 handler.b = ieee754dp_sub; 1575 goto dcopbop; 1576 case fmul_op: 1577 handler.b = ieee754dp_mul; 1578 goto dcopbop; 1579 case fdiv_op: 1580 handler.b = ieee754dp_div; 1581 goto dcopbop; 1582 1583 /* unary ops */ 1584 case fsqrt_op: 1585 if (!cpu_has_mips_2_3_4_5_r) 1586 return SIGILL; 1587 1588 handler.u = ieee754dp_sqrt; 1589 goto dcopuop; 1590 /* 1591 * Note that on some MIPS IV implementations such as the 1592 * R5000 and R8000 the FSQRT and FRECIP instructions do not 1593 * achieve full IEEE-754 accuracy - however this emulator does. 1594 */ 1595 case frsqrt_op: 1596 if (!cpu_has_mips_4_5_r2) 1597 return SIGILL; 1598 1599 handler.u = fpemu_dp_rsqrt; 1600 goto dcopuop; 1601 case frecip_op: 1602 if (!cpu_has_mips_4_5_r2) 1603 return SIGILL; 1604 1605 handler.u = fpemu_dp_recip; 1606 goto dcopuop; 1607 case fmovc_op: 1608 if (!cpu_has_mips_4_5_r) 1609 return SIGILL; 1610 1611 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1612 if (((ctx->fcr31 & cond) != 0) != 1613 ((MIPSInst_FT(ir) & 1) != 0)) 1614 return 0; 1615 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1616 break; 1617 case fmovz_op: 1618 if (!cpu_has_mips_4_5_r) 1619 return SIGILL; 1620 1621 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1622 return 0; 1623 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1624 break; 1625 case fmovn_op: 1626 if (!cpu_has_mips_4_5_r) 1627 return SIGILL; 1628 1629 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1630 return 0; 1631 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1632 break; 1633 case fabs_op: 1634 handler.u = ieee754dp_abs; 1635 goto dcopuop; 1636 1637 case fneg_op: 1638 handler.u = ieee754dp_neg; 1639 goto dcopuop; 1640 1641 case fmov_op: 1642 /* an easy one */ 1643 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1644 goto copcsr; 1645 1646 /* binary op on handler */ 1647dcopbop: 1648 DPFROMREG(fs, MIPSInst_FS(ir)); 1649 DPFROMREG(ft, MIPSInst_FT(ir)); 1650 1651 rv.d = (*handler.b) (fs, ft); 1652 goto copcsr; 1653dcopuop: 1654 DPFROMREG(fs, MIPSInst_FS(ir)); 1655 rv.d = (*handler.u) (fs); 1656 goto copcsr; 1657 1658 /* 1659 * unary conv ops 1660 */ 1661 case fcvts_op: 1662 DPFROMREG(fs, MIPSInst_FS(ir)); 1663 rv.s = ieee754sp_fdp(fs); 1664 rfmt = s_fmt; 1665 goto copcsr; 1666 1667 case fcvtd_op: 1668 return SIGILL; /* not defined */ 1669 1670 case fcvtw_op: 1671 DPFROMREG(fs, MIPSInst_FS(ir)); 1672 rv.w = ieee754dp_tint(fs); /* wrong */ 1673 rfmt = w_fmt; 1674 goto copcsr; 1675 1676 case fround_op: 1677 case ftrunc_op: 1678 case fceil_op: 1679 case ffloor_op: 1680 if (!cpu_has_mips_2_3_4_5_r) 1681 return SIGILL; 1682 1683 oldrm = ieee754_csr.rm; 1684 DPFROMREG(fs, MIPSInst_FS(ir)); 1685 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1686 rv.w = ieee754dp_tint(fs); 1687 ieee754_csr.rm = oldrm; 1688 rfmt = w_fmt; 1689 goto copcsr; 1690 1691 case fcvtl_op: 1692 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1693 return SIGILL; 1694 1695 DPFROMREG(fs, MIPSInst_FS(ir)); 1696 rv.l = ieee754dp_tlong(fs); 1697 rfmt = l_fmt; 1698 goto copcsr; 1699 1700 case froundl_op: 1701 case ftruncl_op: 1702 case fceill_op: 1703 case ffloorl_op: 1704 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1705 return SIGILL; 1706 1707 oldrm = ieee754_csr.rm; 1708 DPFROMREG(fs, MIPSInst_FS(ir)); 1709 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir)); 1710 rv.l = ieee754dp_tlong(fs); 1711 ieee754_csr.rm = oldrm; 1712 rfmt = l_fmt; 1713 goto copcsr; 1714 1715 default: 1716 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1717 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1718 union ieee754dp fs, ft; 1719 1720 DPFROMREG(fs, MIPSInst_FS(ir)); 1721 DPFROMREG(ft, MIPSInst_FT(ir)); 1722 rv.w = ieee754dp_cmp(fs, ft, 1723 cmptab[cmpop & 0x7], cmpop & 0x8); 1724 rfmt = -1; 1725 if ((cmpop & 0x8) 1726 && 1727 ieee754_cxtest 1728 (IEEE754_INVALID_OPERATION)) 1729 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1730 else 1731 goto copcsr; 1732 1733 } 1734 else { 1735 return SIGILL; 1736 } 1737 break; 1738 } 1739 break; 1740 1741 case w_fmt: 1742 switch (MIPSInst_FUNC(ir)) { 1743 case fcvts_op: 1744 /* convert word to single precision real */ 1745 SPFROMREG(fs, MIPSInst_FS(ir)); 1746 rv.s = ieee754sp_fint(fs.bits); 1747 rfmt = s_fmt; 1748 goto copcsr; 1749 case fcvtd_op: 1750 /* convert word to double precision real */ 1751 SPFROMREG(fs, MIPSInst_FS(ir)); 1752 rv.d = ieee754dp_fint(fs.bits); 1753 rfmt = d_fmt; 1754 goto copcsr; 1755 default: 1756 return SIGILL; 1757 } 1758 break; 1759 } 1760 1761 case l_fmt: 1762 1763 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1764 return SIGILL; 1765 1766 DIFROMREG(bits, MIPSInst_FS(ir)); 1767 1768 switch (MIPSInst_FUNC(ir)) { 1769 case fcvts_op: 1770 /* convert long to single precision real */ 1771 rv.s = ieee754sp_flong(bits); 1772 rfmt = s_fmt; 1773 goto copcsr; 1774 case fcvtd_op: 1775 /* convert long to double precision real */ 1776 rv.d = ieee754dp_flong(bits); 1777 rfmt = d_fmt; 1778 goto copcsr; 1779 default: 1780 return SIGILL; 1781 } 1782 break; 1783 1784 default: 1785 return SIGILL; 1786 } 1787 1788 /* 1789 * Update the fpu CSR register for this operation. 1790 * If an exception is required, generate a tidy SIGFPE exception, 1791 * without updating the result register. 1792 * Note: cause exception bits do not accumulate, they are rewritten 1793 * for each op; only the flag/sticky bits accumulate. 1794 */ 1795 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1796 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1797 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */ 1798 return SIGFPE; 1799 } 1800 1801 /* 1802 * Now we can safely write the result back to the register file. 1803 */ 1804 switch (rfmt) { 1805 case -1: 1806 1807 if (cpu_has_mips_4_5_r) 1808 cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; 1809 else 1810 cbit = FPU_CSR_COND; 1811 if (rv.w) 1812 ctx->fcr31 |= cbit; 1813 else 1814 ctx->fcr31 &= ~cbit; 1815 break; 1816 1817 case d_fmt: 1818 DPTOREG(rv.d, MIPSInst_FD(ir)); 1819 break; 1820 case s_fmt: 1821 SPTOREG(rv.s, MIPSInst_FD(ir)); 1822 break; 1823 case w_fmt: 1824 SITOREG(rv.w, MIPSInst_FD(ir)); 1825 break; 1826 case l_fmt: 1827 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) 1828 return SIGILL; 1829 1830 DITOREG(rv.l, MIPSInst_FD(ir)); 1831 break; 1832 default: 1833 return SIGILL; 1834 } 1835 1836 return 0; 1837} 1838 1839int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1840 int has_fpu, void *__user *fault_addr) 1841{ 1842 unsigned long oldepc, prevepc; 1843 struct mm_decoded_insn dec_insn; 1844 u16 instr[4]; 1845 u16 *instr_ptr; 1846 int sig = 0; 1847 1848 oldepc = xcp->cp0_epc; 1849 do { 1850 prevepc = xcp->cp0_epc; 1851 1852 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 1853 /* 1854 * Get next 2 microMIPS instructions and convert them 1855 * into 32-bit instructions. 1856 */ 1857 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 1858 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 1859 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 1860 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 1861 MIPS_FPU_EMU_INC_STATS(errors); 1862 return SIGBUS; 1863 } 1864 instr_ptr = instr; 1865 1866 /* Get first instruction. */ 1867 if (mm_insn_16bit(*instr_ptr)) { 1868 /* Duplicate the half-word. */ 1869 dec_insn.insn = (*instr_ptr << 16) | 1870 (*instr_ptr); 1871 /* 16-bit instruction. */ 1872 dec_insn.pc_inc = 2; 1873 instr_ptr += 1; 1874 } else { 1875 dec_insn.insn = (*instr_ptr << 16) | 1876 *(instr_ptr+1); 1877 /* 32-bit instruction. */ 1878 dec_insn.pc_inc = 4; 1879 instr_ptr += 2; 1880 } 1881 /* Get second instruction. */ 1882 if (mm_insn_16bit(*instr_ptr)) { 1883 /* Duplicate the half-word. */ 1884 dec_insn.next_insn = (*instr_ptr << 16) | 1885 (*instr_ptr); 1886 /* 16-bit instruction. */ 1887 dec_insn.next_pc_inc = 2; 1888 } else { 1889 dec_insn.next_insn = (*instr_ptr << 16) | 1890 *(instr_ptr+1); 1891 /* 32-bit instruction. */ 1892 dec_insn.next_pc_inc = 4; 1893 } 1894 dec_insn.micro_mips_mode = 1; 1895 } else { 1896 if ((get_user(dec_insn.insn, 1897 (mips_instruction __user *) xcp->cp0_epc)) || 1898 (get_user(dec_insn.next_insn, 1899 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 1900 MIPS_FPU_EMU_INC_STATS(errors); 1901 return SIGBUS; 1902 } 1903 dec_insn.pc_inc = 4; 1904 dec_insn.next_pc_inc = 4; 1905 dec_insn.micro_mips_mode = 0; 1906 } 1907 1908 if ((dec_insn.insn == 0) || 1909 ((dec_insn.pc_inc == 2) && 1910 ((dec_insn.insn & 0xffff) == MM_NOP16))) 1911 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 1912 else { 1913 /* 1914 * The 'ieee754_csr' is an alias of 1915 * ctx->fcr31. No need to copy ctx->fcr31 to 1916 * ieee754_csr. But ieee754_csr.rm is ieee 1917 * library modes. (not mips rounding mode) 1918 */ 1919 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 1920 } 1921 1922 if (has_fpu) 1923 break; 1924 if (sig) 1925 break; 1926 1927 cond_resched(); 1928 } while (xcp->cp0_epc > prevepc); 1929 1930 /* SIGILL indicates a non-fpu instruction */ 1931 if (sig == SIGILL && xcp->cp0_epc != oldepc) 1932 /* but if EPC has advanced, then ignore it */ 1933 sig = 0; 1934 1935 return sig; 1936} 1937