cp1emu.c revision e7e9cae5db78030abc73fd3daa93f7cc005177db
1/* 2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. 9 * 10 * This program is free software; you can distribute it and/or modify it 11 * under the terms of the GNU General Public License (Version 2) as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 * for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, write to the Free Software Foundation, Inc., 21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 22 * 23 * A complete emulator for MIPS coprocessor 1 instructions. This is 24 * required for #float(switch) or #float(trap), where it catches all 25 * COP1 instructions via the "CoProcessor Unusable" exception. 26 * 27 * More surprisingly it is also required for #float(ieee), to help out 28 * the hardware fpu at the boundaries of the IEEE-754 representation 29 * (denormalised values, infinities, underflow, etc). It is made 30 * quite nasty because emulation of some non-COP1 instructions is 31 * required, e.g. in branch delay slots. 32 * 33 * Note if you know that you won't have an fpu, then you'll get much 34 * better performance by compiling with -msoft-float! 35 */ 36#include <linux/sched.h> 37#include <linux/module.h> 38#include <linux/debugfs.h> 39#include <linux/perf_event.h> 40 41#include <asm/inst.h> 42#include <asm/bootinfo.h> 43#include <asm/processor.h> 44#include <asm/ptrace.h> 45#include <asm/signal.h> 46#include <asm/mipsregs.h> 47#include <asm/fpu_emulator.h> 48#include <asm/fpu.h> 49#include <asm/uaccess.h> 50#include <asm/branch.h> 51 52#include "ieee754.h" 53 54/* Strap kernel emulator for full MIPS IV emulation */ 55 56#ifdef __mips 57#undef __mips 58#endif 59#define __mips 4 60 61/* Function which emulates a floating point instruction. */ 62 63static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 64 mips_instruction); 65 66#if __mips >= 4 && __mips != 32 67static int fpux_emu(struct pt_regs *, 68 struct mips_fpu_struct *, mips_instruction, void *__user *); 69#endif 70 71/* Further private data for which no space exists in mips_fpu_struct */ 72 73#ifdef CONFIG_DEBUG_FS 74DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); 75#endif 76 77/* Control registers */ 78 79#define FPCREG_RID 0 /* $0 = revision id */ 80#define FPCREG_CSR 31 /* $31 = csr */ 81 82/* Determine rounding mode from the RM bits of the FCSR */ 83#define modeindex(v) ((v) & FPU_CSR_RM) 84 85/* microMIPS bitfields */ 86#define MM_POOL32A_MINOR_MASK 0x3f 87#define MM_POOL32A_MINOR_SHIFT 0x6 88#define MM_MIPS32_COND_FC 0x30 89 90/* Convert Mips rounding mode (0..3) to IEEE library modes. */ 91static const unsigned char ieee_rm[4] = { 92 [FPU_CSR_RN] = IEEE754_RN, 93 [FPU_CSR_RZ] = IEEE754_RZ, 94 [FPU_CSR_RU] = IEEE754_RU, 95 [FPU_CSR_RD] = IEEE754_RD, 96}; 97/* Convert IEEE library modes to Mips rounding mode (0..3). */ 98static const unsigned char mips_rm[4] = { 99 [IEEE754_RN] = FPU_CSR_RN, 100 [IEEE754_RZ] = FPU_CSR_RZ, 101 [IEEE754_RD] = FPU_CSR_RD, 102 [IEEE754_RU] = FPU_CSR_RU, 103}; 104 105#if __mips >= 4 106/* convert condition code register number to csr bit */ 107static const unsigned int fpucondbit[8] = { 108 FPU_CSR_COND0, 109 FPU_CSR_COND1, 110 FPU_CSR_COND2, 111 FPU_CSR_COND3, 112 FPU_CSR_COND4, 113 FPU_CSR_COND5, 114 FPU_CSR_COND6, 115 FPU_CSR_COND7 116}; 117#endif 118 119/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ 120static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; 121 122/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ 123static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; 124static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; 125static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; 126static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; 127 128/* 129 * This functions translates a 32-bit microMIPS instruction 130 * into a 32-bit MIPS32 instruction. Returns 0 on success 131 * and SIGILL otherwise. 132 */ 133static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) 134{ 135 union mips_instruction insn = *insn_ptr; 136 union mips_instruction mips32_insn = insn; 137 int func, fmt, op; 138 139 switch (insn.mm_i_format.opcode) { 140 case mm_ldc132_op: 141 mips32_insn.mm_i_format.opcode = ldc1_op; 142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 144 break; 145 case mm_lwc132_op: 146 mips32_insn.mm_i_format.opcode = lwc1_op; 147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 149 break; 150 case mm_sdc132_op: 151 mips32_insn.mm_i_format.opcode = sdc1_op; 152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 154 break; 155 case mm_swc132_op: 156 mips32_insn.mm_i_format.opcode = swc1_op; 157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; 158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; 159 break; 160 case mm_pool32i_op: 161 /* NOTE: offset is << by 1 if in microMIPS mode. */ 162 if ((insn.mm_i_format.rt == mm_bc1f_op) || 163 (insn.mm_i_format.rt == mm_bc1t_op)) { 164 mips32_insn.fb_format.opcode = cop1_op; 165 mips32_insn.fb_format.bc = bc_op; 166 mips32_insn.fb_format.flag = 167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; 168 } else 169 return SIGILL; 170 break; 171 case mm_pool32f_op: 172 switch (insn.mm_fp0_format.func) { 173 case mm_32f_01_op: 174 case mm_32f_11_op: 175 case mm_32f_02_op: 176 case mm_32f_12_op: 177 case mm_32f_41_op: 178 case mm_32f_51_op: 179 case mm_32f_42_op: 180 case mm_32f_52_op: 181 op = insn.mm_fp0_format.func; 182 if (op == mm_32f_01_op) 183 func = madd_s_op; 184 else if (op == mm_32f_11_op) 185 func = madd_d_op; 186 else if (op == mm_32f_02_op) 187 func = nmadd_s_op; 188 else if (op == mm_32f_12_op) 189 func = nmadd_d_op; 190 else if (op == mm_32f_41_op) 191 func = msub_s_op; 192 else if (op == mm_32f_51_op) 193 func = msub_d_op; 194 else if (op == mm_32f_42_op) 195 func = nmsub_s_op; 196 else 197 func = nmsub_d_op; 198 mips32_insn.fp6_format.opcode = cop1x_op; 199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; 200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; 201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; 202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; 203 mips32_insn.fp6_format.func = func; 204 break; 205 case mm_32f_10_op: 206 func = -1; /* Invalid */ 207 op = insn.mm_fp5_format.op & 0x7; 208 if (op == mm_ldxc1_op) 209 func = ldxc1_op; 210 else if (op == mm_sdxc1_op) 211 func = sdxc1_op; 212 else if (op == mm_lwxc1_op) 213 func = lwxc1_op; 214 else if (op == mm_swxc1_op) 215 func = swxc1_op; 216 217 if (func != -1) { 218 mips32_insn.r_format.opcode = cop1x_op; 219 mips32_insn.r_format.rs = 220 insn.mm_fp5_format.base; 221 mips32_insn.r_format.rt = 222 insn.mm_fp5_format.index; 223 mips32_insn.r_format.rd = 0; 224 mips32_insn.r_format.re = insn.mm_fp5_format.fd; 225 mips32_insn.r_format.func = func; 226 } else 227 return SIGILL; 228 break; 229 case mm_32f_40_op: 230 op = -1; /* Invalid */ 231 if (insn.mm_fp2_format.op == mm_fmovt_op) 232 op = 1; 233 else if (insn.mm_fp2_format.op == mm_fmovf_op) 234 op = 0; 235 if (op != -1) { 236 mips32_insn.fp0_format.opcode = cop1_op; 237 mips32_insn.fp0_format.fmt = 238 sdps_format[insn.mm_fp2_format.fmt]; 239 mips32_insn.fp0_format.ft = 240 (insn.mm_fp2_format.cc<<2) + op; 241 mips32_insn.fp0_format.fs = 242 insn.mm_fp2_format.fs; 243 mips32_insn.fp0_format.fd = 244 insn.mm_fp2_format.fd; 245 mips32_insn.fp0_format.func = fmovc_op; 246 } else 247 return SIGILL; 248 break; 249 case mm_32f_60_op: 250 func = -1; /* Invalid */ 251 if (insn.mm_fp0_format.op == mm_fadd_op) 252 func = fadd_op; 253 else if (insn.mm_fp0_format.op == mm_fsub_op) 254 func = fsub_op; 255 else if (insn.mm_fp0_format.op == mm_fmul_op) 256 func = fmul_op; 257 else if (insn.mm_fp0_format.op == mm_fdiv_op) 258 func = fdiv_op; 259 if (func != -1) { 260 mips32_insn.fp0_format.opcode = cop1_op; 261 mips32_insn.fp0_format.fmt = 262 sdps_format[insn.mm_fp0_format.fmt]; 263 mips32_insn.fp0_format.ft = 264 insn.mm_fp0_format.ft; 265 mips32_insn.fp0_format.fs = 266 insn.mm_fp0_format.fs; 267 mips32_insn.fp0_format.fd = 268 insn.mm_fp0_format.fd; 269 mips32_insn.fp0_format.func = func; 270 } else 271 return SIGILL; 272 break; 273 case mm_32f_70_op: 274 func = -1; /* Invalid */ 275 if (insn.mm_fp0_format.op == mm_fmovn_op) 276 func = fmovn_op; 277 else if (insn.mm_fp0_format.op == mm_fmovz_op) 278 func = fmovz_op; 279 if (func != -1) { 280 mips32_insn.fp0_format.opcode = cop1_op; 281 mips32_insn.fp0_format.fmt = 282 sdps_format[insn.mm_fp0_format.fmt]; 283 mips32_insn.fp0_format.ft = 284 insn.mm_fp0_format.ft; 285 mips32_insn.fp0_format.fs = 286 insn.mm_fp0_format.fs; 287 mips32_insn.fp0_format.fd = 288 insn.mm_fp0_format.fd; 289 mips32_insn.fp0_format.func = func; 290 } else 291 return SIGILL; 292 break; 293 case mm_32f_73_op: /* POOL32FXF */ 294 switch (insn.mm_fp1_format.op) { 295 case mm_movf0_op: 296 case mm_movf1_op: 297 case mm_movt0_op: 298 case mm_movt1_op: 299 if ((insn.mm_fp1_format.op & 0x7f) == 300 mm_movf0_op) 301 op = 0; 302 else 303 op = 1; 304 mips32_insn.r_format.opcode = spec_op; 305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs; 306 mips32_insn.r_format.rt = 307 (insn.mm_fp4_format.cc << 2) + op; 308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt; 309 mips32_insn.r_format.re = 0; 310 mips32_insn.r_format.func = movc_op; 311 break; 312 case mm_fcvtd0_op: 313 case mm_fcvtd1_op: 314 case mm_fcvts0_op: 315 case mm_fcvts1_op: 316 if ((insn.mm_fp1_format.op & 0x7f) == 317 mm_fcvtd0_op) { 318 func = fcvtd_op; 319 fmt = swl_format[insn.mm_fp3_format.fmt]; 320 } else { 321 func = fcvts_op; 322 fmt = dwl_format[insn.mm_fp3_format.fmt]; 323 } 324 mips32_insn.fp0_format.opcode = cop1_op; 325 mips32_insn.fp0_format.fmt = fmt; 326 mips32_insn.fp0_format.ft = 0; 327 mips32_insn.fp0_format.fs = 328 insn.mm_fp3_format.fs; 329 mips32_insn.fp0_format.fd = 330 insn.mm_fp3_format.rt; 331 mips32_insn.fp0_format.func = func; 332 break; 333 case mm_fmov0_op: 334 case mm_fmov1_op: 335 case mm_fabs0_op: 336 case mm_fabs1_op: 337 case mm_fneg0_op: 338 case mm_fneg1_op: 339 if ((insn.mm_fp1_format.op & 0x7f) == 340 mm_fmov0_op) 341 func = fmov_op; 342 else if ((insn.mm_fp1_format.op & 0x7f) == 343 mm_fabs0_op) 344 func = fabs_op; 345 else 346 func = fneg_op; 347 mips32_insn.fp0_format.opcode = cop1_op; 348 mips32_insn.fp0_format.fmt = 349 sdps_format[insn.mm_fp3_format.fmt]; 350 mips32_insn.fp0_format.ft = 0; 351 mips32_insn.fp0_format.fs = 352 insn.mm_fp3_format.fs; 353 mips32_insn.fp0_format.fd = 354 insn.mm_fp3_format.rt; 355 mips32_insn.fp0_format.func = func; 356 break; 357 case mm_ffloorl_op: 358 case mm_ffloorw_op: 359 case mm_fceill_op: 360 case mm_fceilw_op: 361 case mm_ftruncl_op: 362 case mm_ftruncw_op: 363 case mm_froundl_op: 364 case mm_froundw_op: 365 case mm_fcvtl_op: 366 case mm_fcvtw_op: 367 if (insn.mm_fp1_format.op == mm_ffloorl_op) 368 func = ffloorl_op; 369 else if (insn.mm_fp1_format.op == mm_ffloorw_op) 370 func = ffloor_op; 371 else if (insn.mm_fp1_format.op == mm_fceill_op) 372 func = fceill_op; 373 else if (insn.mm_fp1_format.op == mm_fceilw_op) 374 func = fceil_op; 375 else if (insn.mm_fp1_format.op == mm_ftruncl_op) 376 func = ftruncl_op; 377 else if (insn.mm_fp1_format.op == mm_ftruncw_op) 378 func = ftrunc_op; 379 else if (insn.mm_fp1_format.op == mm_froundl_op) 380 func = froundl_op; 381 else if (insn.mm_fp1_format.op == mm_froundw_op) 382 func = fround_op; 383 else if (insn.mm_fp1_format.op == mm_fcvtl_op) 384 func = fcvtl_op; 385 else 386 func = fcvtw_op; 387 mips32_insn.fp0_format.opcode = cop1_op; 388 mips32_insn.fp0_format.fmt = 389 sd_format[insn.mm_fp1_format.fmt]; 390 mips32_insn.fp0_format.ft = 0; 391 mips32_insn.fp0_format.fs = 392 insn.mm_fp1_format.fs; 393 mips32_insn.fp0_format.fd = 394 insn.mm_fp1_format.rt; 395 mips32_insn.fp0_format.func = func; 396 break; 397 case mm_frsqrt_op: 398 case mm_fsqrt_op: 399 case mm_frecip_op: 400 if (insn.mm_fp1_format.op == mm_frsqrt_op) 401 func = frsqrt_op; 402 else if (insn.mm_fp1_format.op == mm_fsqrt_op) 403 func = fsqrt_op; 404 else 405 func = frecip_op; 406 mips32_insn.fp0_format.opcode = cop1_op; 407 mips32_insn.fp0_format.fmt = 408 sdps_format[insn.mm_fp1_format.fmt]; 409 mips32_insn.fp0_format.ft = 0; 410 mips32_insn.fp0_format.fs = 411 insn.mm_fp1_format.fs; 412 mips32_insn.fp0_format.fd = 413 insn.mm_fp1_format.rt; 414 mips32_insn.fp0_format.func = func; 415 break; 416 case mm_mfc1_op: 417 case mm_mtc1_op: 418 case mm_cfc1_op: 419 case mm_ctc1_op: 420 case mm_mfhc1_op: 421 case mm_mthc1_op: 422 if (insn.mm_fp1_format.op == mm_mfc1_op) 423 op = mfc_op; 424 else if (insn.mm_fp1_format.op == mm_mtc1_op) 425 op = mtc_op; 426 else if (insn.mm_fp1_format.op == mm_cfc1_op) 427 op = cfc_op; 428 else if (insn.mm_fp1_format.op == mm_ctc1_op) 429 op = ctc_op; 430 else if (insn.mm_fp1_format.op == mm_mfhc1_op) 431 op = mfhc_op; 432 else 433 op = mthc_op; 434 mips32_insn.fp1_format.opcode = cop1_op; 435 mips32_insn.fp1_format.op = op; 436 mips32_insn.fp1_format.rt = 437 insn.mm_fp1_format.rt; 438 mips32_insn.fp1_format.fs = 439 insn.mm_fp1_format.fs; 440 mips32_insn.fp1_format.fd = 0; 441 mips32_insn.fp1_format.func = 0; 442 break; 443 default: 444 return SIGILL; 445 } 446 break; 447 case mm_32f_74_op: /* c.cond.fmt */ 448 mips32_insn.fp0_format.opcode = cop1_op; 449 mips32_insn.fp0_format.fmt = 450 sdps_format[insn.mm_fp4_format.fmt]; 451 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; 452 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; 453 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; 454 mips32_insn.fp0_format.func = 455 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; 456 break; 457 default: 458 return SIGILL; 459 } 460 break; 461 default: 462 return SIGILL; 463 } 464 465 *insn_ptr = mips32_insn; 466 return 0; 467} 468 469int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 470 unsigned long *contpc) 471{ 472 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 473 int bc_false = 0; 474 unsigned int fcr31; 475 unsigned int bit; 476 477 if (!cpu_has_mmips) 478 return 0; 479 480 switch (insn.mm_i_format.opcode) { 481 case mm_pool32a_op: 482 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == 483 mm_pool32axf_op) { 484 switch (insn.mm_i_format.simmediate >> 485 MM_POOL32A_MINOR_SHIFT) { 486 case mm_jalr_op: 487 case mm_jalrhb_op: 488 case mm_jalrs_op: 489 case mm_jalrshb_op: 490 if (insn.mm_i_format.rt != 0) /* Not mm_jr */ 491 regs->regs[insn.mm_i_format.rt] = 492 regs->cp0_epc + 493 dec_insn.pc_inc + 494 dec_insn.next_pc_inc; 495 *contpc = regs->regs[insn.mm_i_format.rs]; 496 return 1; 497 } 498 } 499 break; 500 case mm_pool32i_op: 501 switch (insn.mm_i_format.rt) { 502 case mm_bltzals_op: 503 case mm_bltzal_op: 504 regs->regs[31] = regs->cp0_epc + 505 dec_insn.pc_inc + 506 dec_insn.next_pc_inc; 507 /* Fall through */ 508 case mm_bltz_op: 509 if ((long)regs->regs[insn.mm_i_format.rs] < 0) 510 *contpc = regs->cp0_epc + 511 dec_insn.pc_inc + 512 (insn.mm_i_format.simmediate << 1); 513 else 514 *contpc = regs->cp0_epc + 515 dec_insn.pc_inc + 516 dec_insn.next_pc_inc; 517 return 1; 518 case mm_bgezals_op: 519 case mm_bgezal_op: 520 regs->regs[31] = regs->cp0_epc + 521 dec_insn.pc_inc + 522 dec_insn.next_pc_inc; 523 /* Fall through */ 524 case mm_bgez_op: 525 if ((long)regs->regs[insn.mm_i_format.rs] >= 0) 526 *contpc = regs->cp0_epc + 527 dec_insn.pc_inc + 528 (insn.mm_i_format.simmediate << 1); 529 else 530 *contpc = regs->cp0_epc + 531 dec_insn.pc_inc + 532 dec_insn.next_pc_inc; 533 return 1; 534 case mm_blez_op: 535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 536 *contpc = regs->cp0_epc + 537 dec_insn.pc_inc + 538 (insn.mm_i_format.simmediate << 1); 539 else 540 *contpc = regs->cp0_epc + 541 dec_insn.pc_inc + 542 dec_insn.next_pc_inc; 543 return 1; 544 case mm_bgtz_op: 545 if ((long)regs->regs[insn.mm_i_format.rs] <= 0) 546 *contpc = regs->cp0_epc + 547 dec_insn.pc_inc + 548 (insn.mm_i_format.simmediate << 1); 549 else 550 *contpc = regs->cp0_epc + 551 dec_insn.pc_inc + 552 dec_insn.next_pc_inc; 553 return 1; 554 case mm_bc2f_op: 555 case mm_bc1f_op: 556 bc_false = 1; 557 /* Fall through */ 558 case mm_bc2t_op: 559 case mm_bc1t_op: 560 preempt_disable(); 561 if (is_fpu_owner()) 562 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 563 else 564 fcr31 = current->thread.fpu.fcr31; 565 preempt_enable(); 566 567 if (bc_false) 568 fcr31 = ~fcr31; 569 570 bit = (insn.mm_i_format.rs >> 2); 571 bit += (bit != 0); 572 bit += 23; 573 if (fcr31 & (1 << bit)) 574 *contpc = regs->cp0_epc + 575 dec_insn.pc_inc + 576 (insn.mm_i_format.simmediate << 1); 577 else 578 *contpc = regs->cp0_epc + 579 dec_insn.pc_inc + dec_insn.next_pc_inc; 580 return 1; 581 } 582 break; 583 case mm_pool16c_op: 584 switch (insn.mm_i_format.rt) { 585 case mm_jalr16_op: 586 case mm_jalrs16_op: 587 regs->regs[31] = regs->cp0_epc + 588 dec_insn.pc_inc + dec_insn.next_pc_inc; 589 /* Fall through */ 590 case mm_jr16_op: 591 *contpc = regs->regs[insn.mm_i_format.rs]; 592 return 1; 593 } 594 break; 595 case mm_beqz16_op: 596 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) 597 *contpc = regs->cp0_epc + 598 dec_insn.pc_inc + 599 (insn.mm_b1_format.simmediate << 1); 600 else 601 *contpc = regs->cp0_epc + 602 dec_insn.pc_inc + dec_insn.next_pc_inc; 603 return 1; 604 case mm_bnez16_op: 605 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) 606 *contpc = regs->cp0_epc + 607 dec_insn.pc_inc + 608 (insn.mm_b1_format.simmediate << 1); 609 else 610 *contpc = regs->cp0_epc + 611 dec_insn.pc_inc + dec_insn.next_pc_inc; 612 return 1; 613 case mm_b16_op: 614 *contpc = regs->cp0_epc + dec_insn.pc_inc + 615 (insn.mm_b0_format.simmediate << 1); 616 return 1; 617 case mm_beq32_op: 618 if (regs->regs[insn.mm_i_format.rs] == 619 regs->regs[insn.mm_i_format.rt]) 620 *contpc = regs->cp0_epc + 621 dec_insn.pc_inc + 622 (insn.mm_i_format.simmediate << 1); 623 else 624 *contpc = regs->cp0_epc + 625 dec_insn.pc_inc + 626 dec_insn.next_pc_inc; 627 return 1; 628 case mm_bne32_op: 629 if (regs->regs[insn.mm_i_format.rs] != 630 regs->regs[insn.mm_i_format.rt]) 631 *contpc = regs->cp0_epc + 632 dec_insn.pc_inc + 633 (insn.mm_i_format.simmediate << 1); 634 else 635 *contpc = regs->cp0_epc + 636 dec_insn.pc_inc + dec_insn.next_pc_inc; 637 return 1; 638 case mm_jalx32_op: 639 regs->regs[31] = regs->cp0_epc + 640 dec_insn.pc_inc + dec_insn.next_pc_inc; 641 *contpc = regs->cp0_epc + dec_insn.pc_inc; 642 *contpc >>= 28; 643 *contpc <<= 28; 644 *contpc |= (insn.j_format.target << 2); 645 return 1; 646 case mm_jals32_op: 647 case mm_jal32_op: 648 regs->regs[31] = regs->cp0_epc + 649 dec_insn.pc_inc + dec_insn.next_pc_inc; 650 /* Fall through */ 651 case mm_j32_op: 652 *contpc = regs->cp0_epc + dec_insn.pc_inc; 653 *contpc >>= 27; 654 *contpc <<= 27; 655 *contpc |= (insn.j_format.target << 1); 656 set_isa16_mode(*contpc); 657 return 1; 658 } 659 return 0; 660} 661 662/* 663 * Redundant with logic already in kernel/branch.c, 664 * embedded in compute_return_epc. At some point, 665 * a single subroutine should be used across both 666 * modules. 667 */ 668static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, 669 unsigned long *contpc) 670{ 671 union mips_instruction insn = (union mips_instruction)dec_insn.insn; 672 unsigned int fcr31; 673 unsigned int bit = 0; 674 675 switch (insn.i_format.opcode) { 676 case spec_op: 677 switch (insn.r_format.func) { 678 case jalr_op: 679 regs->regs[insn.r_format.rd] = 680 regs->cp0_epc + dec_insn.pc_inc + 681 dec_insn.next_pc_inc; 682 /* Fall through */ 683 case jr_op: 684 *contpc = regs->regs[insn.r_format.rs]; 685 return 1; 686 } 687 break; 688 case bcond_op: 689 switch (insn.i_format.rt) { 690 case bltzal_op: 691 case bltzall_op: 692 regs->regs[31] = regs->cp0_epc + 693 dec_insn.pc_inc + 694 dec_insn.next_pc_inc; 695 /* Fall through */ 696 case bltz_op: 697 case bltzl_op: 698 if ((long)regs->regs[insn.i_format.rs] < 0) 699 *contpc = regs->cp0_epc + 700 dec_insn.pc_inc + 701 (insn.i_format.simmediate << 2); 702 else 703 *contpc = regs->cp0_epc + 704 dec_insn.pc_inc + 705 dec_insn.next_pc_inc; 706 return 1; 707 case bgezal_op: 708 case bgezall_op: 709 regs->regs[31] = regs->cp0_epc + 710 dec_insn.pc_inc + 711 dec_insn.next_pc_inc; 712 /* Fall through */ 713 case bgez_op: 714 case bgezl_op: 715 if ((long)regs->regs[insn.i_format.rs] >= 0) 716 *contpc = regs->cp0_epc + 717 dec_insn.pc_inc + 718 (insn.i_format.simmediate << 2); 719 else 720 *contpc = regs->cp0_epc + 721 dec_insn.pc_inc + 722 dec_insn.next_pc_inc; 723 return 1; 724 } 725 break; 726 case jalx_op: 727 set_isa16_mode(bit); 728 case jal_op: 729 regs->regs[31] = regs->cp0_epc + 730 dec_insn.pc_inc + 731 dec_insn.next_pc_inc; 732 /* Fall through */ 733 case j_op: 734 *contpc = regs->cp0_epc + dec_insn.pc_inc; 735 *contpc >>= 28; 736 *contpc <<= 28; 737 *contpc |= (insn.j_format.target << 2); 738 /* Set microMIPS mode bit: XOR for jalx. */ 739 *contpc ^= bit; 740 return 1; 741 case beq_op: 742 case beql_op: 743 if (regs->regs[insn.i_format.rs] == 744 regs->regs[insn.i_format.rt]) 745 *contpc = regs->cp0_epc + 746 dec_insn.pc_inc + 747 (insn.i_format.simmediate << 2); 748 else 749 *contpc = regs->cp0_epc + 750 dec_insn.pc_inc + 751 dec_insn.next_pc_inc; 752 return 1; 753 case bne_op: 754 case bnel_op: 755 if (regs->regs[insn.i_format.rs] != 756 regs->regs[insn.i_format.rt]) 757 *contpc = regs->cp0_epc + 758 dec_insn.pc_inc + 759 (insn.i_format.simmediate << 2); 760 else 761 *contpc = regs->cp0_epc + 762 dec_insn.pc_inc + 763 dec_insn.next_pc_inc; 764 return 1; 765 case blez_op: 766 case blezl_op: 767 if ((long)regs->regs[insn.i_format.rs] <= 0) 768 *contpc = regs->cp0_epc + 769 dec_insn.pc_inc + 770 (insn.i_format.simmediate << 2); 771 else 772 *contpc = regs->cp0_epc + 773 dec_insn.pc_inc + 774 dec_insn.next_pc_inc; 775 return 1; 776 case bgtz_op: 777 case bgtzl_op: 778 if ((long)regs->regs[insn.i_format.rs] > 0) 779 *contpc = regs->cp0_epc + 780 dec_insn.pc_inc + 781 (insn.i_format.simmediate << 2); 782 else 783 *contpc = regs->cp0_epc + 784 dec_insn.pc_inc + 785 dec_insn.next_pc_inc; 786 return 1; 787#ifdef CONFIG_CPU_CAVIUM_OCTEON 788 case lwc2_op: /* This is bbit0 on Octeon */ 789 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) 790 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 791 else 792 *contpc = regs->cp0_epc + 8; 793 return 1; 794 case ldc2_op: /* This is bbit032 on Octeon */ 795 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) 796 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 797 else 798 *contpc = regs->cp0_epc + 8; 799 return 1; 800 case swc2_op: /* This is bbit1 on Octeon */ 801 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) 802 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 803 else 804 *contpc = regs->cp0_epc + 8; 805 return 1; 806 case sdc2_op: /* This is bbit132 on Octeon */ 807 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) 808 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); 809 else 810 *contpc = regs->cp0_epc + 8; 811 return 1; 812#endif 813 case cop0_op: 814 case cop1_op: 815 case cop2_op: 816 case cop1x_op: 817 if (insn.i_format.rs == bc_op) { 818 preempt_disable(); 819 if (is_fpu_owner()) 820 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 821 else 822 fcr31 = current->thread.fpu.fcr31; 823 preempt_enable(); 824 825 bit = (insn.i_format.rt >> 2); 826 bit += (bit != 0); 827 bit += 23; 828 switch (insn.i_format.rt & 3) { 829 case 0: /* bc1f */ 830 case 2: /* bc1fl */ 831 if (~fcr31 & (1 << bit)) 832 *contpc = regs->cp0_epc + 833 dec_insn.pc_inc + 834 (insn.i_format.simmediate << 2); 835 else 836 *contpc = regs->cp0_epc + 837 dec_insn.pc_inc + 838 dec_insn.next_pc_inc; 839 return 1; 840 case 1: /* bc1t */ 841 case 3: /* bc1tl */ 842 if (fcr31 & (1 << bit)) 843 *contpc = regs->cp0_epc + 844 dec_insn.pc_inc + 845 (insn.i_format.simmediate << 2); 846 else 847 *contpc = regs->cp0_epc + 848 dec_insn.pc_inc + 849 dec_insn.next_pc_inc; 850 return 1; 851 } 852 } 853 break; 854 } 855 return 0; 856} 857 858/* 859 * In the Linux kernel, we support selection of FPR format on the 860 * basis of the Status.FR bit. If an FPU is not present, the FR bit 861 * is hardwired to zero, which would imply a 32-bit FPU even for 862 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 863 * FPU emu is slow and bulky and optimizing this function offers fairly 864 * sizeable benefits so we try to be clever and make this function return 865 * a constant whenever possible, that is on 64-bit kernels without O32 866 * compatibility enabled and on 32-bit without 64-bit FPU support. 867 */ 868static inline int cop1_64bit(struct pt_regs *xcp) 869{ 870#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) 871 return 1; 872#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT) 873 return 0; 874#else 875 return !test_thread_flag(TIF_32BIT_FPREGS); 876#endif 877} 878 879#define SIFROMREG(si, x) do { \ 880 if (cop1_64bit(xcp)) \ 881 (si) = get_fpr32(&ctx->fpr[x], 0); \ 882 else \ 883 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ 884} while (0) 885 886#define SITOREG(si, x) do { \ 887 if (cop1_64bit(xcp)) { \ 888 unsigned i; \ 889 set_fpr32(&ctx->fpr[x], 0, si); \ 890 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 891 set_fpr32(&ctx->fpr[x], i, 0); \ 892 } else { \ 893 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ 894 } \ 895} while (0) 896 897#define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) 898 899#define SITOHREG(si, x) do { \ 900 unsigned i; \ 901 set_fpr32(&ctx->fpr[x], 1, si); \ 902 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ 903 set_fpr32(&ctx->fpr[x], i, 0); \ 904} while (0) 905 906#define DIFROMREG(di, x) \ 907 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) 908 909#define DITOREG(di, x) do { \ 910 unsigned fpr, i; \ 911 fpr = (x) & ~(cop1_64bit(xcp) == 0); \ 912 set_fpr64(&ctx->fpr[fpr], 0, di); \ 913 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ 914 set_fpr64(&ctx->fpr[fpr], i, 0); \ 915} while (0) 916 917#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 918#define SPTOREG(sp, x) SITOREG((sp).bits, x) 919#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) 920#define DPTOREG(dp, x) DITOREG((dp).bits, x) 921 922/* 923 * Emulate the single floating point instruction pointed at by EPC. 924 * Two instructions if the instruction is in a branch delay slot. 925 */ 926 927static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 928 struct mm_decoded_insn dec_insn, void *__user *fault_addr) 929{ 930 mips_instruction ir; 931 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; 932 unsigned int cond; 933 int pc_inc; 934 935 /* XXX NEC Vr54xx bug workaround */ 936 if (delay_slot(xcp)) { 937 if (dec_insn.micro_mips_mode) { 938 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) 939 clear_delay_slot(xcp); 940 } else { 941 if (!isBranchInstr(xcp, dec_insn, &contpc)) 942 clear_delay_slot(xcp); 943 } 944 } 945 946 if (delay_slot(xcp)) { 947 /* 948 * The instruction to be emulated is in a branch delay slot 949 * which means that we have to emulate the branch instruction 950 * BEFORE we do the cop1 instruction. 951 * 952 * This branch could be a COP1 branch, but in that case we 953 * would have had a trap for that instruction, and would not 954 * come through this route. 955 * 956 * Linux MIPS branch emulator operates on context, updating the 957 * cp0_epc. 958 */ 959 ir = dec_insn.next_insn; /* process delay slot instr */ 960 pc_inc = dec_insn.next_pc_inc; 961 } else { 962 ir = dec_insn.insn; /* process current instr */ 963 pc_inc = dec_insn.pc_inc; 964 } 965 966 /* 967 * Since microMIPS FPU instructios are a subset of MIPS32 FPU 968 * instructions, we want to convert microMIPS FPU instructions 969 * into MIPS32 instructions so that we could reuse all of the 970 * FPU emulation code. 971 * 972 * NOTE: We cannot do this for branch instructions since they 973 * are not a subset. Example: Cannot emulate a 16-bit 974 * aligned target address with a MIPS32 instruction. 975 */ 976 if (dec_insn.micro_mips_mode) { 977 /* 978 * If next instruction is a 16-bit instruction, then it 979 * it cannot be a FPU instruction. This could happen 980 * since we can be called for non-FPU instructions. 981 */ 982 if ((pc_inc == 2) || 983 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 984 == SIGILL)) 985 return SIGILL; 986 } 987 988 emul: 989 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); 990 MIPS_FPU_EMU_INC_STATS(emulated); 991 switch (MIPSInst_OPCODE(ir)) { 992 case ldc1_op:{ 993 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 994 MIPSInst_SIMM(ir)); 995 u64 val; 996 997 MIPS_FPU_EMU_INC_STATS(loads); 998 999 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1000 MIPS_FPU_EMU_INC_STATS(errors); 1001 *fault_addr = va; 1002 return SIGBUS; 1003 } 1004 if (__get_user(val, va)) { 1005 MIPS_FPU_EMU_INC_STATS(errors); 1006 *fault_addr = va; 1007 return SIGSEGV; 1008 } 1009 DITOREG(val, MIPSInst_RT(ir)); 1010 break; 1011 } 1012 1013 case sdc1_op:{ 1014 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1015 MIPSInst_SIMM(ir)); 1016 u64 val; 1017 1018 MIPS_FPU_EMU_INC_STATS(stores); 1019 DIFROMREG(val, MIPSInst_RT(ir)); 1020 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1021 MIPS_FPU_EMU_INC_STATS(errors); 1022 *fault_addr = va; 1023 return SIGBUS; 1024 } 1025 if (__put_user(val, va)) { 1026 MIPS_FPU_EMU_INC_STATS(errors); 1027 *fault_addr = va; 1028 return SIGSEGV; 1029 } 1030 break; 1031 } 1032 1033 case lwc1_op:{ 1034 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1035 MIPSInst_SIMM(ir)); 1036 u32 val; 1037 1038 MIPS_FPU_EMU_INC_STATS(loads); 1039 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1040 MIPS_FPU_EMU_INC_STATS(errors); 1041 *fault_addr = va; 1042 return SIGBUS; 1043 } 1044 if (__get_user(val, va)) { 1045 MIPS_FPU_EMU_INC_STATS(errors); 1046 *fault_addr = va; 1047 return SIGSEGV; 1048 } 1049 SITOREG(val, MIPSInst_RT(ir)); 1050 break; 1051 } 1052 1053 case swc1_op:{ 1054 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 1055 MIPSInst_SIMM(ir)); 1056 u32 val; 1057 1058 MIPS_FPU_EMU_INC_STATS(stores); 1059 SIFROMREG(val, MIPSInst_RT(ir)); 1060 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1061 MIPS_FPU_EMU_INC_STATS(errors); 1062 *fault_addr = va; 1063 return SIGBUS; 1064 } 1065 if (__put_user(val, va)) { 1066 MIPS_FPU_EMU_INC_STATS(errors); 1067 *fault_addr = va; 1068 return SIGSEGV; 1069 } 1070 break; 1071 } 1072 1073 case cop1_op: 1074 switch (MIPSInst_RS(ir)) { 1075 1076#if defined(__mips64) 1077 case dmfc_op: 1078 /* copregister fs -> gpr[rt] */ 1079 if (MIPSInst_RT(ir) != 0) { 1080 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1081 MIPSInst_RD(ir)); 1082 } 1083 break; 1084 1085 case dmtc_op: 1086 /* copregister fs <- rt */ 1087 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1088 break; 1089#endif 1090 1091 case mfhc_op: 1092 if (!cpu_has_mips_r2) 1093 goto sigill; 1094 1095 /* copregister rd -> gpr[rt] */ 1096 if (MIPSInst_RT(ir) != 0) { 1097 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1098 MIPSInst_RD(ir)); 1099 } 1100 break; 1101 1102 case mthc_op: 1103 if (!cpu_has_mips_r2) 1104 goto sigill; 1105 1106 /* copregister rd <- gpr[rt] */ 1107 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1108 break; 1109 1110 case mfc_op: 1111 /* copregister rd -> gpr[rt] */ 1112 if (MIPSInst_RT(ir) != 0) { 1113 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 1114 MIPSInst_RD(ir)); 1115 } 1116 break; 1117 1118 case mtc_op: 1119 /* copregister rd <- rt */ 1120 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1121 break; 1122 1123 case cfc_op:{ 1124 /* cop control register rd -> gpr[rt] */ 1125 u32 value; 1126 1127 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1128 value = ctx->fcr31; 1129 value = (value & ~FPU_CSR_RM) | 1130 mips_rm[modeindex(value)]; 1131#ifdef CSRTRACE 1132 printk("%p gpr[%d]<-csr=%08x\n", 1133 (void *) (xcp->cp0_epc), 1134 MIPSInst_RT(ir), value); 1135#endif 1136 } 1137 else if (MIPSInst_RD(ir) == FPCREG_RID) 1138 value = 0; 1139 else 1140 value = 0; 1141 if (MIPSInst_RT(ir)) 1142 xcp->regs[MIPSInst_RT(ir)] = value; 1143 break; 1144 } 1145 1146 case ctc_op:{ 1147 /* copregister rd <- rt */ 1148 u32 value; 1149 1150 if (MIPSInst_RT(ir) == 0) 1151 value = 0; 1152 else 1153 value = xcp->regs[MIPSInst_RT(ir)]; 1154 1155 /* we only have one writable control reg 1156 */ 1157 if (MIPSInst_RD(ir) == FPCREG_CSR) { 1158#ifdef CSRTRACE 1159 printk("%p gpr[%d]->csr=%08x\n", 1160 (void *) (xcp->cp0_epc), 1161 MIPSInst_RT(ir), value); 1162#endif 1163 1164 /* 1165 * Don't write reserved bits, 1166 * and convert to ieee library modes 1167 */ 1168 ctx->fcr31 = (value & 1169 ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 1170 ieee_rm[modeindex(value)]; 1171 } 1172 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1173 return SIGFPE; 1174 } 1175 break; 1176 } 1177 1178 case bc_op:{ 1179 int likely = 0; 1180 1181 if (delay_slot(xcp)) 1182 return SIGILL; 1183 1184#if __mips >= 4 1185 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2]; 1186#else 1187 cond = ctx->fcr31 & FPU_CSR_COND; 1188#endif 1189 switch (MIPSInst_RT(ir) & 3) { 1190 case bcfl_op: 1191 likely = 1; 1192 case bcf_op: 1193 cond = !cond; 1194 break; 1195 case bctl_op: 1196 likely = 1; 1197 case bct_op: 1198 break; 1199 default: 1200 /* thats an illegal instruction */ 1201 return SIGILL; 1202 } 1203 1204 set_delay_slot(xcp); 1205 if (cond) { 1206 /* branch taken: emulate dslot 1207 * instruction 1208 */ 1209 xcp->cp0_epc += dec_insn.pc_inc; 1210 1211 contpc = MIPSInst_SIMM(ir); 1212 ir = dec_insn.next_insn; 1213 if (dec_insn.micro_mips_mode) { 1214 contpc = (xcp->cp0_epc + (contpc << 1)); 1215 1216 /* If 16-bit instruction, not FPU. */ 1217 if ((dec_insn.next_pc_inc == 2) || 1218 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { 1219 1220 /* 1221 * Since this instruction will 1222 * be put on the stack with 1223 * 32-bit words, get around 1224 * this problem by putting a 1225 * NOP16 as the second one. 1226 */ 1227 if (dec_insn.next_pc_inc == 2) 1228 ir = (ir & (~0xffff)) | MM_NOP16; 1229 1230 /* 1231 * Single step the non-CP1 1232 * instruction in the dslot. 1233 */ 1234 return mips_dsemul(xcp, ir, contpc); 1235 } 1236 } else 1237 contpc = (xcp->cp0_epc + (contpc << 2)); 1238 1239 switch (MIPSInst_OPCODE(ir)) { 1240 case lwc1_op: 1241 case swc1_op: 1242#if (__mips >= 2 || defined(__mips64)) 1243 case ldc1_op: 1244 case sdc1_op: 1245#endif 1246 case cop1_op: 1247#if __mips >= 4 && __mips != 32 1248 case cop1x_op: 1249#endif 1250 /* its one of ours */ 1251 goto emul; 1252#if __mips >= 4 1253 case spec_op: 1254 if (MIPSInst_FUNC(ir) == movc_op) 1255 goto emul; 1256 break; 1257#endif 1258 } 1259 1260 /* 1261 * Single step the non-cp1 1262 * instruction in the dslot 1263 */ 1264 return mips_dsemul(xcp, ir, contpc); 1265 } 1266 else { 1267 /* branch not taken */ 1268 if (likely) { 1269 /* 1270 * branch likely nullifies 1271 * dslot if not taken 1272 */ 1273 xcp->cp0_epc += dec_insn.pc_inc; 1274 contpc += dec_insn.pc_inc; 1275 /* 1276 * else continue & execute 1277 * dslot as normal insn 1278 */ 1279 } 1280 } 1281 break; 1282 } 1283 1284 default: 1285 if (!(MIPSInst_RS(ir) & 0x10)) 1286 return SIGILL; 1287 { 1288 int sig; 1289 1290 /* a real fpu computation instruction */ 1291 if ((sig = fpu_emu(xcp, ctx, ir))) 1292 return sig; 1293 } 1294 } 1295 break; 1296 1297#if __mips >= 4 && __mips != 32 1298 case cop1x_op:{ 1299 int sig = fpux_emu(xcp, ctx, ir, fault_addr); 1300 if (sig) 1301 return sig; 1302 break; 1303 } 1304#endif 1305 1306#if __mips >= 4 1307 case spec_op: 1308 if (MIPSInst_FUNC(ir) != movc_op) 1309 return SIGILL; 1310 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 1311 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) 1312 xcp->regs[MIPSInst_RD(ir)] = 1313 xcp->regs[MIPSInst_RS(ir)]; 1314 break; 1315#endif 1316 1317 default: 1318sigill: 1319 return SIGILL; 1320 } 1321 1322 /* we did it !! */ 1323 xcp->cp0_epc = contpc; 1324 clear_delay_slot(xcp); 1325 1326 return 0; 1327} 1328 1329/* 1330 * Conversion table from MIPS compare ops 48-63 1331 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); 1332 */ 1333static const unsigned char cmptab[8] = { 1334 0, /* cmp_0 (sig) cmp_sf */ 1335 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ 1336 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ 1337 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ 1338 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ 1339 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ 1340 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ 1341 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ 1342}; 1343 1344 1345#if __mips >= 4 && __mips != 32 1346 1347/* 1348 * Additional MIPS4 instructions 1349 */ 1350 1351#define DEF3OP(name, p, f1, f2, f3) \ 1352static union ieee754##p fpemu_##p##_##name(union ieee754##p r, union ieee754##p s, \ 1353 union ieee754##p t) \ 1354{ \ 1355 struct _ieee754_csr ieee754_csr_save; \ 1356 s = f1(s, t); \ 1357 ieee754_csr_save = ieee754_csr; \ 1358 s = f2(s, r); \ 1359 ieee754_csr_save.cx |= ieee754_csr.cx; \ 1360 ieee754_csr_save.sx |= ieee754_csr.sx; \ 1361 s = f3(s); \ 1362 ieee754_csr.cx |= ieee754_csr_save.cx; \ 1363 ieee754_csr.sx |= ieee754_csr_save.sx; \ 1364 return s; \ 1365} 1366 1367static union ieee754dp fpemu_dp_recip(union ieee754dp d) 1368{ 1369 return ieee754dp_div(ieee754dp_one(0), d); 1370} 1371 1372static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) 1373{ 1374 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); 1375} 1376 1377static union ieee754sp fpemu_sp_recip(union ieee754sp s) 1378{ 1379 return ieee754sp_div(ieee754sp_one(0), s); 1380} 1381 1382static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) 1383{ 1384 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 1385} 1386 1387DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); 1388DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); 1389DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 1390DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 1391DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); 1392DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); 1393DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 1394DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 1395 1396static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1397 mips_instruction ir, void *__user *fault_addr) 1398{ 1399 unsigned rcsr = 0; /* resulting csr */ 1400 1401 MIPS_FPU_EMU_INC_STATS(cp1xops); 1402 1403 switch (MIPSInst_FMA_FFMT(ir)) { 1404 case s_fmt:{ /* 0 */ 1405 1406 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); 1407 union ieee754sp fd, fr, fs, ft; 1408 u32 __user *va; 1409 u32 val; 1410 1411 switch (MIPSInst_FUNC(ir)) { 1412 case lwxc1_op: 1413 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1414 xcp->regs[MIPSInst_FT(ir)]); 1415 1416 MIPS_FPU_EMU_INC_STATS(loads); 1417 if (!access_ok(VERIFY_READ, va, sizeof(u32))) { 1418 MIPS_FPU_EMU_INC_STATS(errors); 1419 *fault_addr = va; 1420 return SIGBUS; 1421 } 1422 if (__get_user(val, va)) { 1423 MIPS_FPU_EMU_INC_STATS(errors); 1424 *fault_addr = va; 1425 return SIGSEGV; 1426 } 1427 SITOREG(val, MIPSInst_FD(ir)); 1428 break; 1429 1430 case swxc1_op: 1431 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1432 xcp->regs[MIPSInst_FT(ir)]); 1433 1434 MIPS_FPU_EMU_INC_STATS(stores); 1435 1436 SIFROMREG(val, MIPSInst_FS(ir)); 1437 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { 1438 MIPS_FPU_EMU_INC_STATS(errors); 1439 *fault_addr = va; 1440 return SIGBUS; 1441 } 1442 if (put_user(val, va)) { 1443 MIPS_FPU_EMU_INC_STATS(errors); 1444 *fault_addr = va; 1445 return SIGSEGV; 1446 } 1447 break; 1448 1449 case madd_s_op: 1450 handler = fpemu_sp_madd; 1451 goto scoptop; 1452 case msub_s_op: 1453 handler = fpemu_sp_msub; 1454 goto scoptop; 1455 case nmadd_s_op: 1456 handler = fpemu_sp_nmadd; 1457 goto scoptop; 1458 case nmsub_s_op: 1459 handler = fpemu_sp_nmsub; 1460 goto scoptop; 1461 1462 scoptop: 1463 SPFROMREG(fr, MIPSInst_FR(ir)); 1464 SPFROMREG(fs, MIPSInst_FS(ir)); 1465 SPFROMREG(ft, MIPSInst_FT(ir)); 1466 fd = (*handler) (fr, fs, ft); 1467 SPTOREG(fd, MIPSInst_FD(ir)); 1468 1469 copcsr: 1470 if (ieee754_cxtest(IEEE754_INEXACT)) 1471 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1472 if (ieee754_cxtest(IEEE754_UNDERFLOW)) 1473 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1474 if (ieee754_cxtest(IEEE754_OVERFLOW)) 1475 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1476 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 1477 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1478 1479 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 1480 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 1481 /*printk ("SIGFPE: fpu csr = %08x\n", 1482 ctx->fcr31); */ 1483 return SIGFPE; 1484 } 1485 1486 break; 1487 1488 default: 1489 return SIGILL; 1490 } 1491 break; 1492 } 1493 1494 case d_fmt:{ /* 1 */ 1495 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); 1496 union ieee754dp fd, fr, fs, ft; 1497 u64 __user *va; 1498 u64 val; 1499 1500 switch (MIPSInst_FUNC(ir)) { 1501 case ldxc1_op: 1502 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1503 xcp->regs[MIPSInst_FT(ir)]); 1504 1505 MIPS_FPU_EMU_INC_STATS(loads); 1506 if (!access_ok(VERIFY_READ, va, sizeof(u64))) { 1507 MIPS_FPU_EMU_INC_STATS(errors); 1508 *fault_addr = va; 1509 return SIGBUS; 1510 } 1511 if (__get_user(val, va)) { 1512 MIPS_FPU_EMU_INC_STATS(errors); 1513 *fault_addr = va; 1514 return SIGSEGV; 1515 } 1516 DITOREG(val, MIPSInst_FD(ir)); 1517 break; 1518 1519 case sdxc1_op: 1520 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 1521 xcp->regs[MIPSInst_FT(ir)]); 1522 1523 MIPS_FPU_EMU_INC_STATS(stores); 1524 DIFROMREG(val, MIPSInst_FS(ir)); 1525 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { 1526 MIPS_FPU_EMU_INC_STATS(errors); 1527 *fault_addr = va; 1528 return SIGBUS; 1529 } 1530 if (__put_user(val, va)) { 1531 MIPS_FPU_EMU_INC_STATS(errors); 1532 *fault_addr = va; 1533 return SIGSEGV; 1534 } 1535 break; 1536 1537 case madd_d_op: 1538 handler = fpemu_dp_madd; 1539 goto dcoptop; 1540 case msub_d_op: 1541 handler = fpemu_dp_msub; 1542 goto dcoptop; 1543 case nmadd_d_op: 1544 handler = fpemu_dp_nmadd; 1545 goto dcoptop; 1546 case nmsub_d_op: 1547 handler = fpemu_dp_nmsub; 1548 goto dcoptop; 1549 1550 dcoptop: 1551 DPFROMREG(fr, MIPSInst_FR(ir)); 1552 DPFROMREG(fs, MIPSInst_FS(ir)); 1553 DPFROMREG(ft, MIPSInst_FT(ir)); 1554 fd = (*handler) (fr, fs, ft); 1555 DPTOREG(fd, MIPSInst_FD(ir)); 1556 goto copcsr; 1557 1558 default: 1559 return SIGILL; 1560 } 1561 break; 1562 } 1563 1564 case 0x3: 1565 if (MIPSInst_FUNC(ir) != pfetch_op) 1566 return SIGILL; 1567 1568 /* ignore prefx operation */ 1569 break; 1570 1571 default: 1572 return SIGILL; 1573 } 1574 1575 return 0; 1576} 1577#endif 1578 1579 1580 1581/* 1582 * Emulate a single COP1 arithmetic instruction. 1583 */ 1584static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 1585 mips_instruction ir) 1586{ 1587 int rfmt; /* resulting format */ 1588 unsigned rcsr = 0; /* resulting csr */ 1589 unsigned cond; 1590 union { 1591 union ieee754dp d; 1592 union ieee754sp s; 1593 int w; 1594#ifdef __mips64 1595 s64 l; 1596#endif 1597 } rv; /* resulting value */ 1598 1599 MIPS_FPU_EMU_INC_STATS(cp1ops); 1600 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 1601 case s_fmt:{ /* 0 */ 1602 union { 1603 union ieee754sp(*b) (union ieee754sp, union ieee754sp); 1604 union ieee754sp(*u) (union ieee754sp); 1605 } handler; 1606 1607 switch (MIPSInst_FUNC(ir)) { 1608 /* binary ops */ 1609 case fadd_op: 1610 handler.b = ieee754sp_add; 1611 goto scopbop; 1612 case fsub_op: 1613 handler.b = ieee754sp_sub; 1614 goto scopbop; 1615 case fmul_op: 1616 handler.b = ieee754sp_mul; 1617 goto scopbop; 1618 case fdiv_op: 1619 handler.b = ieee754sp_div; 1620 goto scopbop; 1621 1622 /* unary ops */ 1623#if __mips >= 2 || defined(__mips64) 1624 case fsqrt_op: 1625 handler.u = ieee754sp_sqrt; 1626 goto scopuop; 1627#endif 1628#if __mips >= 4 && __mips != 32 1629 case frsqrt_op: 1630 handler.u = fpemu_sp_rsqrt; 1631 goto scopuop; 1632 case frecip_op: 1633 handler.u = fpemu_sp_recip; 1634 goto scopuop; 1635#endif 1636#if __mips >= 4 1637 case fmovc_op: 1638 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1639 if (((ctx->fcr31 & cond) != 0) != 1640 ((MIPSInst_FT(ir) & 1) != 0)) 1641 return 0; 1642 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1643 break; 1644 case fmovz_op: 1645 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1646 return 0; 1647 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1648 break; 1649 case fmovn_op: 1650 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1651 return 0; 1652 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1653 break; 1654#endif 1655 case fabs_op: 1656 handler.u = ieee754sp_abs; 1657 goto scopuop; 1658 case fneg_op: 1659 handler.u = ieee754sp_neg; 1660 goto scopuop; 1661 case fmov_op: 1662 /* an easy one */ 1663 SPFROMREG(rv.s, MIPSInst_FS(ir)); 1664 goto copcsr; 1665 1666 /* binary op on handler */ 1667 scopbop: 1668 { 1669 union ieee754sp fs, ft; 1670 1671 SPFROMREG(fs, MIPSInst_FS(ir)); 1672 SPFROMREG(ft, MIPSInst_FT(ir)); 1673 1674 rv.s = (*handler.b) (fs, ft); 1675 goto copcsr; 1676 } 1677 scopuop: 1678 { 1679 union ieee754sp fs; 1680 1681 SPFROMREG(fs, MIPSInst_FS(ir)); 1682 rv.s = (*handler.u) (fs); 1683 goto copcsr; 1684 } 1685 copcsr: 1686 if (ieee754_cxtest(IEEE754_INEXACT)) 1687 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; 1688 if (ieee754_cxtest(IEEE754_UNDERFLOW)) 1689 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; 1690 if (ieee754_cxtest(IEEE754_OVERFLOW)) 1691 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; 1692 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) 1693 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; 1694 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) 1695 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; 1696 break; 1697 1698 /* unary conv ops */ 1699 case fcvts_op: 1700 return SIGILL; /* not defined */ 1701 case fcvtd_op:{ 1702 union ieee754sp fs; 1703 1704 SPFROMREG(fs, MIPSInst_FS(ir)); 1705 rv.d = ieee754dp_fsp(fs); 1706 rfmt = d_fmt; 1707 goto copcsr; 1708 } 1709 case fcvtw_op:{ 1710 union ieee754sp fs; 1711 1712 SPFROMREG(fs, MIPSInst_FS(ir)); 1713 rv.w = ieee754sp_tint(fs); 1714 rfmt = w_fmt; 1715 goto copcsr; 1716 } 1717 1718#if __mips >= 2 || defined(__mips64) 1719 case fround_op: 1720 case ftrunc_op: 1721 case fceil_op: 1722 case ffloor_op:{ 1723 unsigned int oldrm = ieee754_csr.rm; 1724 union ieee754sp fs; 1725 1726 SPFROMREG(fs, MIPSInst_FS(ir)); 1727 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1728 rv.w = ieee754sp_tint(fs); 1729 ieee754_csr.rm = oldrm; 1730 rfmt = w_fmt; 1731 goto copcsr; 1732 } 1733#endif /* __mips >= 2 */ 1734 1735#if defined(__mips64) 1736 case fcvtl_op:{ 1737 union ieee754sp fs; 1738 1739 SPFROMREG(fs, MIPSInst_FS(ir)); 1740 rv.l = ieee754sp_tlong(fs); 1741 rfmt = l_fmt; 1742 goto copcsr; 1743 } 1744 1745 case froundl_op: 1746 case ftruncl_op: 1747 case fceill_op: 1748 case ffloorl_op:{ 1749 unsigned int oldrm = ieee754_csr.rm; 1750 union ieee754sp fs; 1751 1752 SPFROMREG(fs, MIPSInst_FS(ir)); 1753 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1754 rv.l = ieee754sp_tlong(fs); 1755 ieee754_csr.rm = oldrm; 1756 rfmt = l_fmt; 1757 goto copcsr; 1758 } 1759#endif /* defined(__mips64) */ 1760 1761 default: 1762 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1763 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1764 union ieee754sp fs, ft; 1765 1766 SPFROMREG(fs, MIPSInst_FS(ir)); 1767 SPFROMREG(ft, MIPSInst_FT(ir)); 1768 rv.w = ieee754sp_cmp(fs, ft, 1769 cmptab[cmpop & 0x7], cmpop & 0x8); 1770 rfmt = -1; 1771 if ((cmpop & 0x8) && ieee754_cxtest 1772 (IEEE754_INVALID_OPERATION)) 1773 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1774 else 1775 goto copcsr; 1776 1777 } 1778 else { 1779 return SIGILL; 1780 } 1781 break; 1782 } 1783 break; 1784 } 1785 1786 case d_fmt:{ 1787 union { 1788 union ieee754dp(*b) (union ieee754dp, union ieee754dp); 1789 union ieee754dp(*u) (union ieee754dp); 1790 } handler; 1791 1792 switch (MIPSInst_FUNC(ir)) { 1793 /* binary ops */ 1794 case fadd_op: 1795 handler.b = ieee754dp_add; 1796 goto dcopbop; 1797 case fsub_op: 1798 handler.b = ieee754dp_sub; 1799 goto dcopbop; 1800 case fmul_op: 1801 handler.b = ieee754dp_mul; 1802 goto dcopbop; 1803 case fdiv_op: 1804 handler.b = ieee754dp_div; 1805 goto dcopbop; 1806 1807 /* unary ops */ 1808#if __mips >= 2 || defined(__mips64) 1809 case fsqrt_op: 1810 handler.u = ieee754dp_sqrt; 1811 goto dcopuop; 1812#endif 1813#if __mips >= 4 && __mips != 32 1814 case frsqrt_op: 1815 handler.u = fpemu_dp_rsqrt; 1816 goto dcopuop; 1817 case frecip_op: 1818 handler.u = fpemu_dp_recip; 1819 goto dcopuop; 1820#endif 1821#if __mips >= 4 1822 case fmovc_op: 1823 cond = fpucondbit[MIPSInst_FT(ir) >> 2]; 1824 if (((ctx->fcr31 & cond) != 0) != 1825 ((MIPSInst_FT(ir) & 1) != 0)) 1826 return 0; 1827 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1828 break; 1829 case fmovz_op: 1830 if (xcp->regs[MIPSInst_FT(ir)] != 0) 1831 return 0; 1832 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1833 break; 1834 case fmovn_op: 1835 if (xcp->regs[MIPSInst_FT(ir)] == 0) 1836 return 0; 1837 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1838 break; 1839#endif 1840 case fabs_op: 1841 handler.u = ieee754dp_abs; 1842 goto dcopuop; 1843 1844 case fneg_op: 1845 handler.u = ieee754dp_neg; 1846 goto dcopuop; 1847 1848 case fmov_op: 1849 /* an easy one */ 1850 DPFROMREG(rv.d, MIPSInst_FS(ir)); 1851 goto copcsr; 1852 1853 /* binary op on handler */ 1854 dcopbop:{ 1855 union ieee754dp fs, ft; 1856 1857 DPFROMREG(fs, MIPSInst_FS(ir)); 1858 DPFROMREG(ft, MIPSInst_FT(ir)); 1859 1860 rv.d = (*handler.b) (fs, ft); 1861 goto copcsr; 1862 } 1863 dcopuop:{ 1864 union ieee754dp fs; 1865 1866 DPFROMREG(fs, MIPSInst_FS(ir)); 1867 rv.d = (*handler.u) (fs); 1868 goto copcsr; 1869 } 1870 1871 /* unary conv ops */ 1872 case fcvts_op:{ 1873 union ieee754dp fs; 1874 1875 DPFROMREG(fs, MIPSInst_FS(ir)); 1876 rv.s = ieee754sp_fdp(fs); 1877 rfmt = s_fmt; 1878 goto copcsr; 1879 } 1880 case fcvtd_op: 1881 return SIGILL; /* not defined */ 1882 1883 case fcvtw_op:{ 1884 union ieee754dp fs; 1885 1886 DPFROMREG(fs, MIPSInst_FS(ir)); 1887 rv.w = ieee754dp_tint(fs); /* wrong */ 1888 rfmt = w_fmt; 1889 goto copcsr; 1890 } 1891 1892#if __mips >= 2 || defined(__mips64) 1893 case fround_op: 1894 case ftrunc_op: 1895 case fceil_op: 1896 case ffloor_op:{ 1897 unsigned int oldrm = ieee754_csr.rm; 1898 union ieee754dp fs; 1899 1900 DPFROMREG(fs, MIPSInst_FS(ir)); 1901 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1902 rv.w = ieee754dp_tint(fs); 1903 ieee754_csr.rm = oldrm; 1904 rfmt = w_fmt; 1905 goto copcsr; 1906 } 1907#endif 1908 1909#if defined(__mips64) 1910 case fcvtl_op:{ 1911 union ieee754dp fs; 1912 1913 DPFROMREG(fs, MIPSInst_FS(ir)); 1914 rv.l = ieee754dp_tlong(fs); 1915 rfmt = l_fmt; 1916 goto copcsr; 1917 } 1918 1919 case froundl_op: 1920 case ftruncl_op: 1921 case fceill_op: 1922 case ffloorl_op:{ 1923 unsigned int oldrm = ieee754_csr.rm; 1924 union ieee754dp fs; 1925 1926 DPFROMREG(fs, MIPSInst_FS(ir)); 1927 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1928 rv.l = ieee754dp_tlong(fs); 1929 ieee754_csr.rm = oldrm; 1930 rfmt = l_fmt; 1931 goto copcsr; 1932 } 1933#endif /* __mips >= 3 */ 1934 1935 default: 1936 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1937 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; 1938 union ieee754dp fs, ft; 1939 1940 DPFROMREG(fs, MIPSInst_FS(ir)); 1941 DPFROMREG(ft, MIPSInst_FT(ir)); 1942 rv.w = ieee754dp_cmp(fs, ft, 1943 cmptab[cmpop & 0x7], cmpop & 0x8); 1944 rfmt = -1; 1945 if ((cmpop & 0x8) 1946 && 1947 ieee754_cxtest 1948 (IEEE754_INVALID_OPERATION)) 1949 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; 1950 else 1951 goto copcsr; 1952 1953 } 1954 else { 1955 return SIGILL; 1956 } 1957 break; 1958 } 1959 break; 1960 } 1961 1962 case w_fmt:{ 1963 union ieee754sp fs; 1964 1965 switch (MIPSInst_FUNC(ir)) { 1966 case fcvts_op: 1967 /* convert word to single precision real */ 1968 SPFROMREG(fs, MIPSInst_FS(ir)); 1969 rv.s = ieee754sp_fint(fs.bits); 1970 rfmt = s_fmt; 1971 goto copcsr; 1972 case fcvtd_op: 1973 /* convert word to double precision real */ 1974 SPFROMREG(fs, MIPSInst_FS(ir)); 1975 rv.d = ieee754dp_fint(fs.bits); 1976 rfmt = d_fmt; 1977 goto copcsr; 1978 default: 1979 return SIGILL; 1980 } 1981 break; 1982 } 1983 1984#if defined(__mips64) 1985 case l_fmt:{ 1986 u64 bits; 1987 DIFROMREG(bits, MIPSInst_FS(ir)); 1988 1989 switch (MIPSInst_FUNC(ir)) { 1990 case fcvts_op: 1991 /* convert long to single precision real */ 1992 rv.s = ieee754sp_flong(bits); 1993 rfmt = s_fmt; 1994 goto copcsr; 1995 case fcvtd_op: 1996 /* convert long to double precision real */ 1997 rv.d = ieee754dp_flong(bits); 1998 rfmt = d_fmt; 1999 goto copcsr; 2000 default: 2001 return SIGILL; 2002 } 2003 break; 2004 } 2005#endif 2006 2007 default: 2008 return SIGILL; 2009 } 2010 2011 /* 2012 * Update the fpu CSR register for this operation. 2013 * If an exception is required, generate a tidy SIGFPE exception, 2014 * without updating the result register. 2015 * Note: cause exception bits do not accumulate, they are rewritten 2016 * for each op; only the flag/sticky bits accumulate. 2017 */ 2018 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; 2019 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 2020 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ 2021 return SIGFPE; 2022 } 2023 2024 /* 2025 * Now we can safely write the result back to the register file. 2026 */ 2027 switch (rfmt) { 2028 case -1:{ 2029#if __mips >= 4 2030 cond = fpucondbit[MIPSInst_FD(ir) >> 2]; 2031#else 2032 cond = FPU_CSR_COND; 2033#endif 2034 if (rv.w) 2035 ctx->fcr31 |= cond; 2036 else 2037 ctx->fcr31 &= ~cond; 2038 break; 2039 } 2040 case d_fmt: 2041 DPTOREG(rv.d, MIPSInst_FD(ir)); 2042 break; 2043 case s_fmt: 2044 SPTOREG(rv.s, MIPSInst_FD(ir)); 2045 break; 2046 case w_fmt: 2047 SITOREG(rv.w, MIPSInst_FD(ir)); 2048 break; 2049#if defined(__mips64) 2050 case l_fmt: 2051 DITOREG(rv.l, MIPSInst_FD(ir)); 2052 break; 2053#endif 2054 default: 2055 return SIGILL; 2056 } 2057 2058 return 0; 2059} 2060 2061int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 2062 int has_fpu, void *__user *fault_addr) 2063{ 2064 unsigned long oldepc, prevepc; 2065 struct mm_decoded_insn dec_insn; 2066 u16 instr[4]; 2067 u16 *instr_ptr; 2068 int sig = 0; 2069 2070 oldepc = xcp->cp0_epc; 2071 do { 2072 prevepc = xcp->cp0_epc; 2073 2074 if (get_isa16_mode(prevepc) && cpu_has_mmips) { 2075 /* 2076 * Get next 2 microMIPS instructions and convert them 2077 * into 32-bit instructions. 2078 */ 2079 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || 2080 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || 2081 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || 2082 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { 2083 MIPS_FPU_EMU_INC_STATS(errors); 2084 return SIGBUS; 2085 } 2086 instr_ptr = instr; 2087 2088 /* Get first instruction. */ 2089 if (mm_insn_16bit(*instr_ptr)) { 2090 /* Duplicate the half-word. */ 2091 dec_insn.insn = (*instr_ptr << 16) | 2092 (*instr_ptr); 2093 /* 16-bit instruction. */ 2094 dec_insn.pc_inc = 2; 2095 instr_ptr += 1; 2096 } else { 2097 dec_insn.insn = (*instr_ptr << 16) | 2098 *(instr_ptr+1); 2099 /* 32-bit instruction. */ 2100 dec_insn.pc_inc = 4; 2101 instr_ptr += 2; 2102 } 2103 /* Get second instruction. */ 2104 if (mm_insn_16bit(*instr_ptr)) { 2105 /* Duplicate the half-word. */ 2106 dec_insn.next_insn = (*instr_ptr << 16) | 2107 (*instr_ptr); 2108 /* 16-bit instruction. */ 2109 dec_insn.next_pc_inc = 2; 2110 } else { 2111 dec_insn.next_insn = (*instr_ptr << 16) | 2112 *(instr_ptr+1); 2113 /* 32-bit instruction. */ 2114 dec_insn.next_pc_inc = 4; 2115 } 2116 dec_insn.micro_mips_mode = 1; 2117 } else { 2118 if ((get_user(dec_insn.insn, 2119 (mips_instruction __user *) xcp->cp0_epc)) || 2120 (get_user(dec_insn.next_insn, 2121 (mips_instruction __user *)(xcp->cp0_epc+4)))) { 2122 MIPS_FPU_EMU_INC_STATS(errors); 2123 return SIGBUS; 2124 } 2125 dec_insn.pc_inc = 4; 2126 dec_insn.next_pc_inc = 4; 2127 dec_insn.micro_mips_mode = 0; 2128 } 2129 2130 if ((dec_insn.insn == 0) || 2131 ((dec_insn.pc_inc == 2) && 2132 ((dec_insn.insn & 0xffff) == MM_NOP16))) 2133 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ 2134 else { 2135 /* 2136 * The 'ieee754_csr' is an alias of 2137 * ctx->fcr31. No need to copy ctx->fcr31 to 2138 * ieee754_csr. But ieee754_csr.rm is ieee 2139 * library modes. (not mips rounding mode) 2140 */ 2141 /* convert to ieee library modes */ 2142 ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; 2143 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 2144 /* revert to mips rounding mode */ 2145 ieee754_csr.rm = mips_rm[ieee754_csr.rm]; 2146 } 2147 2148 if (has_fpu) 2149 break; 2150 if (sig) 2151 break; 2152 2153 cond_resched(); 2154 } while (xcp->cp0_epc > prevepc); 2155 2156 /* SIGILL indicates a non-fpu instruction */ 2157 if (sig == SIGILL && xcp->cp0_epc != oldepc) 2158 /* but if epc has advanced, then ignore it */ 2159 sig = 0; 2160 2161 return sig; 2162} 2163 2164#ifdef CONFIG_DEBUG_FS 2165 2166static int fpuemu_stat_get(void *data, u64 *val) 2167{ 2168 int cpu; 2169 unsigned long sum = 0; 2170 for_each_online_cpu(cpu) { 2171 struct mips_fpu_emulator_stats *ps; 2172 local_t *pv; 2173 ps = &per_cpu(fpuemustats, cpu); 2174 pv = (void *)ps + (unsigned long)data; 2175 sum += local_read(pv); 2176 } 2177 *val = sum; 2178 return 0; 2179} 2180DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); 2181 2182extern struct dentry *mips_debugfs_dir; 2183static int __init debugfs_fpuemu(void) 2184{ 2185 struct dentry *d, *dir; 2186 2187 if (!mips_debugfs_dir) 2188 return -ENODEV; 2189 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 2190 if (!dir) 2191 return -ENOMEM; 2192 2193#define FPU_STAT_CREATE(M) \ 2194 do { \ 2195 d = debugfs_create_file(#M , S_IRUGO, dir, \ 2196 (void *)offsetof(struct mips_fpu_emulator_stats, M), \ 2197 &fops_fpuemu_stat); \ 2198 if (!d) \ 2199 return -ENOMEM; \ 2200 } while (0) 2201 2202 FPU_STAT_CREATE(emulated); 2203 FPU_STAT_CREATE(loads); 2204 FPU_STAT_CREATE(stores); 2205 FPU_STAT_CREATE(cp1ops); 2206 FPU_STAT_CREATE(cp1xops); 2207 FPU_STAT_CREATE(errors); 2208 2209 return 0; 2210} 2211__initcall(debugfs_fpuemu); 2212#endif 2213