kilauea.dts revision 049359d655277c382683a6030ae0bac485568ffc
1a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese/* 2a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * Device Tree Source for AMCC Kilauea (405EX) 3a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * 4a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 5a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * 6a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * This file is licensed under the terms of the GNU General Public 7a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * License version 2. This program is licensed "as is" without 8a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese * any warranty of any kind, whether express or implied. 9a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese */ 10a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 1171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson/dts-v1/; 1271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 13a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese/ { 14a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <1>; 15a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <1>; 16a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese model = "amcc,kilauea"; 17a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "amcc,kilauea"; 1871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-parent = <&{/cpus/cpu@0}>; 19a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 208aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese aliases { 218aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese ethernet0 = &EMAC0; 228aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese ethernet1 = &EMAC1; 238aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese serial0 = &UART0; 248aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese serial1 = &UART1; 258aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese }; 268aaed98c1e28a2c803309fcb2d32761bba4bee09Stefan Roese 27a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese cpus { 28a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <1>; 29a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 30a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 3172fda1148e14d2f06d8653c26f579b7d2dabba57Josh Boyer cpu@0 { 32a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese device_type = "cpu"; 3372fda1148e14d2f06d8653c26f579b7d2dabba57Josh Boyer model = "PowerPC,405EX"; 3471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x00000000>; 35a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 36a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 3771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson i-cache-line-size = <32>; 3871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson d-cache-line-size = <32>; 3971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson i-cache-size = <16384>; /* 16 kB */ 4071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson d-cache-size = <16384>; /* 16 kB */ 41a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese dcr-controller; 42a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese dcr-access-method = "native"; 43a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 44a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 45a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 46a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese memory { 47a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese device_type = "memory"; 4871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */ 49a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 50a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 51a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese UIC0: interrupt-controller { 52a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 53a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-controller; 54a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese cell-index = <0>; 5571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x0c0 0x009>; 56a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <0>; 57a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 58a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #interrupt-cells = <2>; 59a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 60a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 61a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese UIC1: interrupt-controller1 { 62a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 63a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-controller; 64a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese cell-index = <1>; 6571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x0d0 0x009>; 66a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <0>; 67a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 68a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #interrupt-cells = <2>; 6971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ 70a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC0>; 71a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 72a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 73a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese UIC2: interrupt-controller2 { 74a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 75a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-controller; 76a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese cell-index = <2>; 7771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x0e0 0x009>; 78a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <0>; 79a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 80a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #interrupt-cells = <2>; 8171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */ 82a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC0>; 83a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 84a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 85a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese plb { 86a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 87a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <1>; 88a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <1>; 89a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese ranges; 90a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 91a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 92a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese SDRAM0: memory-controller { 9394ce1c585ed51dd9e72e812117e11f3f236a5399Grant Erickson compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2"; 9471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x010 0x002>; 9594ce1c585ed51dd9e72e812117e11f3f236a5399Grant Erickson interrupt-parent = <&UIC2>; 9694ce1c585ed51dd9e72e812117e11f3f236a5399Grant Erickson interrupts = <0x5 0x4 /* ECC DED Error */ 9794ce1c585ed51dd9e72e812117e11f3f236a5399Grant Erickson 0x6 0x4>; /* ECC SEC Error */ 98a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 99a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 100049359d655277c382683a6030ae0bac485568ffcJames Hsiao CRYPTO: crypto@ef700000 { 101049359d655277c382683a6030ae0bac485568ffcJames Hsiao compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto"; 102049359d655277c382683a6030ae0bac485568ffcJames Hsiao reg = <0xef700000 0x80400>; 103049359d655277c382683a6030ae0bac485568ffcJames Hsiao interrupt-parent = <&UIC0>; 104049359d655277c382683a6030ae0bac485568ffcJames Hsiao interrupts = <0x17 0x2>; 105049359d655277c382683a6030ae0bac485568ffcJames Hsiao }; 106049359d655277c382683a6030ae0bac485568ffcJames Hsiao 107a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese MAL0: mcmal { 108a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 10971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x180 0x062>; 110a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese num-tx-chans = <2>; 111a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese num-rx-chans = <2>; 112a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&MAL0>; 11371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x0 0x1 0x2 0x3 0x4>; 114a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #interrupt-cells = <1>; 115a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <0>; 116a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 11771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 11871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson /*RXEOB*/ 0x1 &UIC0 0xb 0x4 11971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson /*SERR*/ 0x2 &UIC1 0x0 0x4 12071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson /*TXDE*/ 0x3 &UIC1 0x1 0x4 12171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 12271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupt-map-mask = <0xffffffff>; 123a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 124a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 125a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese POB0: opb { 126a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 127a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <1>; 128a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <1>; 12971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson ranges = <0x80000000 0x80000000 0x10000000 13071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0xef600000 0xef600000 0x00a00000 13171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0xf0000000 0xf0000000 0x10000000>; 13271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x0a0 0x005>; 133a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 134a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 135a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese EBC0: ebc { 136a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 13771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x012 0x002>; 138a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <2>; 139a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <1>; 140a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 141a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese /* ranges property is supplied by U-Boot */ 14271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x5 0x1>; 143a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC1>; 144a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 145a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese nor_flash@0,0 { 146a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 147a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese bank-width = <2>; 14871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x00000000 0x00000000 0x04000000>; 149a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <1>; 150a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <1>; 151a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese partition@0 { 152a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese label = "kernel"; 15371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x00000000 0x00200000>; 154a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 155a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese partition@200000 { 156a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese label = "root"; 15771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x00200000 0x00200000>; 158a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 159a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese partition@400000 { 160a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese label = "user"; 16171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x00400000 0x03b60000>; 162a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 163a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese partition@3f60000 { 164a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese label = "env"; 16571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x03f60000 0x00040000>; 166a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 167a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese partition@3fa0000 { 168a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese label = "u-boot"; 16971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0x03fa0000 0x00060000>; 170a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 171a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 172a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 173a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 174a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese UART0: serial@ef600200 { 175a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese device_type = "serial"; 176a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ns16550"; 17771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xef600200 0x00000008>; 17871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson virtual-reg = <0xef600200>; 179a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 180a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese current-speed = <0>; 181a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC0>; 18271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x1a 0x4>; 183a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 184a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 185a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese UART1: serial@ef600300 { 186a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese device_type = "serial"; 187a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ns16550"; 18871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xef600300 0x00000008>; 18971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson virtual-reg = <0xef600300>; 190a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 191a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese current-speed = <0>; 192a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC0>; 19371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x1 0x4>; 194a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 195a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 196a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese IIC0: i2c@ef600400 { 197a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 19871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xef600400 0x00000014>; 199a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC0>; 20071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x2 0x4>; 201a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 202a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 203a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese IIC1: i2c@ef600500 { 204a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 20571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xef600500 0x00000014>; 206a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&UIC0>; 20771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x7 0x4>; 208a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 209a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 210a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 211a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese RGMII0: emac-rgmii@ef600b00 { 212a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 21371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xef600b00 0x00000104>; 2140a6ea8bef14064ec6b5f9cf3d4ce2f81b73a9bb0Stefan Roese has-mdio; 215a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 216a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 217a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese EMAC0: ethernet@ef600900 { 21871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson linux,network-index = <0x0>; 219a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese device_type = "network"; 22005781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 221a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&EMAC0>; 22271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x0 0x1>; 223a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #interrupt-cells = <1>; 224a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <0>; 225a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 22671f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4 22771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson /*Wake*/ 0x1 &UIC1 0x1d 0x4>; 22805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson reg = <0xef600900 0x000000c4>; 229a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 230a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese mal-device = <&MAL0>; 231a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese mal-tx-channel = <0>; 232a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese mal-rx-channel = <0>; 233a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese cell-index = <0>; 23471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson max-frame-size = <9000>; 23571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson rx-fifo-size = <4096>; 23671f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson tx-fifo-size = <2048>; 237a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese phy-mode = "rgmii"; 23871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson phy-map = <0x00000000>; 239a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese rgmii-device = <&RGMII0>; 240a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese rgmii-channel = <0>; 2410a6ea8bef14064ec6b5f9cf3d4ce2f81b73a9bb0Stefan Roese has-inverted-stacr-oc; 2420a6ea8bef14064ec6b5f9cf3d4ce2f81b73a9bb0Stefan Roese has-new-stacr-staopc; 243a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 244a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese 245a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese EMAC1: ethernet@ef600a00 { 24671f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson linux,network-index = <0x1>; 247a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese device_type = "network"; 24805781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson compatible = "ibm,emac-405ex", "ibm,emac4sync"; 249a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese interrupt-parent = <&EMAC1>; 25071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupts = <0x0 0x1>; 251a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #interrupt-cells = <1>; 252a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #address-cells = <0>; 253a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese #size-cells = <0>; 25471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4 25571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson /*Wake*/ 0x1 &UIC1 0x1f 0x4>; 25605781ccd74c63c6c8567f99101587d5c07c163e0Grant Erickson reg = <0xef600a00 0x000000c4>; 257a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 258a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese mal-device = <&MAL0>; 259a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese mal-tx-channel = <1>; 260a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese mal-rx-channel = <1>; 261a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese cell-index = <1>; 26271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson max-frame-size = <9000>; 26371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson rx-fifo-size = <4096>; 26471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson tx-fifo-size = <2048>; 265a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese phy-mode = "rgmii"; 26671f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson phy-map = <0x00000000>; 267a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese rgmii-device = <&RGMII0>; 268a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese rgmii-channel = <1>; 2690a6ea8bef14064ec6b5f9cf3d4ce2f81b73a9bb0Stefan Roese has-inverted-stacr-oc; 2700a6ea8bef14064ec6b5f9cf3d4ce2f81b73a9bb0Stefan Roese has-new-stacr-staopc; 271a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 272a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 273151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 274151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese PCIE0: pciex@0a0000000 { 275151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese device_type = "pci"; 276151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese #interrupt-cells = <1>; 277151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese #size-cells = <2>; 278151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese #address-cells = <3>; 279151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 280151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese primary; 28171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson port = <0x0>; /* port number */ 28271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xa0000000 0x20000000 /* Config space access */ 28371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0xef000000 0x00001000>; /* Registers */ 28471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x040 0x020>; 28571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson sdr-base = <0x400>; 286151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 287151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese /* Outbound ranges, one memory and one IO, 288151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * later cannot be changed 289151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese */ 29071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000 29171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>; 292151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 293151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese /* Inbound 2GB range starting at 0 */ 29471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 295151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 296dc88416b098a1e0bde82dc4e00ed95109681ab5cStefan Roese /* This drives busses 0x00 to 0x3f */ 29771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson bus-range = <0x0 0x3f>; 298151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 299151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 300151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * to invert PCIe legacy interrupts). 301151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * We are de-swizzling here because the numbers are actually for 302151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * port of the root complex virtual P2P bridge. But I want 303151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * to avoid putting a node for it in the tree, so the numbers 304151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * below are basically de-swizzled numbers. 305151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 306151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese */ 30771f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 308151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese interrupt-map = < 30971f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */ 31071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */ 31171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */ 31271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>; 313151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese }; 314151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 315151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese PCIE1: pciex@0c0000000 { 316151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese device_type = "pci"; 317151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese #interrupt-cells = <1>; 318151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese #size-cells = <2>; 319151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese #address-cells = <3>; 320151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; 321151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese primary; 32271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson port = <0x1>; /* port number */ 32371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson reg = <0xc0000000 0x20000000 /* Config space access */ 32471f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0xef001000 0x00001000>; /* Registers */ 32571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dcr-reg = <0x060 0x020>; 32671f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson sdr-base = <0x440>; 327151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 328151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese /* Outbound ranges, one memory and one IO, 329151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * later cannot be changed 330151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese */ 33171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000 33271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>; 333151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 334151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese /* Inbound 2GB range starting at 0 */ 33571f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; 336151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 337dc88416b098a1e0bde82dc4e00ed95109681ab5cStefan Roese /* This drives busses 0x40 to 0x7f */ 33871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson bus-range = <0x40 0x7f>; 339151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese 340151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese /* Legacy interrupts (note the weird polarity, the bridge seems 341151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * to invert PCIe legacy interrupts). 342151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * We are de-swizzling here because the numbers are actually for 343151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * port of the root complex virtual P2P bridge. But I want 344151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * to avoid putting a node for it in the tree, so the numbers 345151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * below are basically de-swizzled numbers. 346151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese * The real slot is on idsel 0, so the swizzling is 1:1 347151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese */ 34871f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson interrupt-map-mask = <0x0 0x0 0x0 0x7>; 349151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese interrupt-map = < 35071f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */ 35171f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */ 35271f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */ 35371f349799b34c8b6ce3df42126b4de6cfa16456dDavid Gibson 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>; 354151161c6e23160b8573a7048e7de0ded77c89655Stefan Roese }; 355a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese }; 356a62f48de13b7496ede99e9980840c03e2d1dab86Stefan Roese}; 357