cpm.h revision 71d94fe842c34fb93eb32ae20207bea757292b79 
1#ifndef __CPM_H
2#define __CPM_H
3
4#include <linux/compiler.h>
5#include <linux/types.h>
6#include <linux/of.h>
7
8/*
9 * USB Controller pram common to QE and CPM.
10 */
11struct usb_ctlr {
12	u8	usb_usmod;
13	u8	usb_usadr;
14	u8	usb_uscom;
15	u8	res1[1];
16	__be16	usb_usep[4];
17	u8	res2[4];
18	__be16	usb_usber;
19	u8	res3[2];
20	__be16	usb_usbmr;
21	u8	res4[1];
22	u8	usb_usbs;
23	/* Fields down below are QE-only */
24	__be16	usb_ussft;
25	u8	res5[2];
26	__be16	usb_usfrn;
27	u8	res6[0x22];
28} __attribute__ ((packed));
29
30/*
31 * Function code bits, usually generic to devices.
32 */
33#ifdef CONFIG_CPM1
34#define CPMFCR_GBL	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
35#define CPMFCR_TC2	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
36#define CPMFCR_DTB	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
37#define CPMFCR_BDB	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
38#else
39#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
40#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
41#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
42#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
43#endif
44#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */
45
46/* Opcodes common to CPM1 and CPM2
47*/
48#define CPM_CR_INIT_TRX		((ushort)0x0000)
49#define CPM_CR_INIT_RX		((ushort)0x0001)
50#define CPM_CR_INIT_TX		((ushort)0x0002)
51#define CPM_CR_HUNT_MODE	((ushort)0x0003)
52#define CPM_CR_STOP_TX		((ushort)0x0004)
53#define CPM_CR_GRA_STOP_TX	((ushort)0x0005)
54#define CPM_CR_RESTART_TX	((ushort)0x0006)
55#define CPM_CR_CLOSE_RX_BD	((ushort)0x0007)
56#define CPM_CR_SET_GADDR	((ushort)0x0008)
57#define CPM_CR_SET_TIMER	((ushort)0x0008)
58#define CPM_CR_STOP_IDMA	((ushort)0x000b)
59
60/* Buffer descriptors used by many of the CPM protocols. */
61typedef struct cpm_buf_desc {
62	ushort	cbd_sc;		/* Status and Control */
63	ushort	cbd_datlen;	/* Data length in buffer */
64	uint	cbd_bufaddr;	/* Buffer address in host memory */
65} cbd_t;
66
67/* Buffer descriptor control/status used by serial
68 */
69
70#define BD_SC_EMPTY	(0x8000)	/* Receive is empty */
71#define BD_SC_READY	(0x8000)	/* Transmit is ready */
72#define BD_SC_WRAP	(0x2000)	/* Last buffer descriptor */
73#define BD_SC_INTRPT	(0x1000)	/* Interrupt on change */
74#define BD_SC_LAST	(0x0800)	/* Last buffer in frame */
75#define BD_SC_TC	(0x0400)	/* Transmit CRC */
76#define BD_SC_CM	(0x0200)	/* Continous mode */
77#define BD_SC_ID	(0x0100)	/* Rec'd too many idles */
78#define BD_SC_P		(0x0100)	/* xmt preamble */
79#define BD_SC_BR	(0x0020)	/* Break received */
80#define BD_SC_FR	(0x0010)	/* Framing error */
81#define BD_SC_PR	(0x0008)	/* Parity error */
82#define BD_SC_NAK	(0x0004)	/* NAK - did not respond */
83#define BD_SC_OV	(0x0002)	/* Overrun */
84#define BD_SC_UN	(0x0002)	/* Underrun */
85#define BD_SC_CD	(0x0001)	/* */
86#define BD_SC_CL	(0x0001)	/* Collision */
87
88/* Buffer descriptor control/status used by Ethernet receive.
89 * Common to SCC and FCC.
90 */
91#define BD_ENET_RX_EMPTY	(0x8000)
92#define BD_ENET_RX_WRAP		(0x2000)
93#define BD_ENET_RX_INTR		(0x1000)
94#define BD_ENET_RX_LAST		(0x0800)
95#define BD_ENET_RX_FIRST	(0x0400)
96#define BD_ENET_RX_MISS		(0x0100)
97#define BD_ENET_RX_BC		(0x0080)	/* FCC Only */
98#define BD_ENET_RX_MC		(0x0040)	/* FCC Only */
99#define BD_ENET_RX_LG		(0x0020)
100#define BD_ENET_RX_NO		(0x0010)
101#define BD_ENET_RX_SH		(0x0008)
102#define BD_ENET_RX_CR		(0x0004)
103#define BD_ENET_RX_OV		(0x0002)
104#define BD_ENET_RX_CL		(0x0001)
105#define BD_ENET_RX_STATS	(0x01ff)	/* All status bits */
106
107/* Buffer descriptor control/status used by Ethernet transmit.
108 * Common to SCC and FCC.
109 */
110#define BD_ENET_TX_READY	(0x8000)
111#define BD_ENET_TX_PAD		(0x4000)
112#define BD_ENET_TX_WRAP		(0x2000)
113#define BD_ENET_TX_INTR		(0x1000)
114#define BD_ENET_TX_LAST		(0x0800)
115#define BD_ENET_TX_TC		(0x0400)
116#define BD_ENET_TX_DEF		(0x0200)
117#define BD_ENET_TX_HB		(0x0100)
118#define BD_ENET_TX_LC		(0x0080)
119#define BD_ENET_TX_RL		(0x0040)
120#define BD_ENET_TX_RCMASK	(0x003c)
121#define BD_ENET_TX_UN		(0x0002)
122#define BD_ENET_TX_CSL		(0x0001)
123#define BD_ENET_TX_STATS	(0x03ff)	/* All status bits */
124
125/* Buffer descriptor control/status used by Transparent mode SCC.
126 */
127#define BD_SCC_TX_LAST		(0x0800)
128
129/* Buffer descriptor control/status used by I2C.
130 */
131#define BD_I2C_START		(0x0400)
132
133int cpm_muram_init(void);
134unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
135int cpm_muram_free(unsigned long offset);
136unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
137void __iomem *cpm_muram_addr(unsigned long offset);
138unsigned long cpm_muram_offset(void __iomem *addr);
139dma_addr_t cpm_muram_dma(void __iomem *addr);
140int cpm_command(u32 command, u8 opcode);
141
142int cpm2_gpiochip_add32(struct device_node *np);
143
144#endif
145