133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* 233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * Communication Processor Module v2. 333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * 433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * This file contains structures and information for the communication 533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * processor channels found in the dual port RAM or parameter RAM. 633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * All CPM control and status is available through the CPM2 internal 733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * memory map. See immap_cpm2.h for details. 833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#ifdef __KERNEL__ 1033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#ifndef __CPM2__ 1133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define __CPM2__ 1233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 1333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#include <asm/immap_cpm2.h> 1415f8c604a79c4840ed76eecf3af5d88b7c1dee9eScott Wood#include <asm/cpm.h> 15dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#include <sysdev/fsl_soc.h> 1633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 1733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* CPM Command register. 1833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 1933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_RST ((uint)0x80000000) 2033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_PAGE ((uint)0x7c000000) 2133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SBLOCK ((uint)0x03e00000) 2233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FLG ((uint)0x00010000) 2333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_MCN ((uint)0x00003fc0) 2433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_OPCODE ((uint)0x0000000f) 2533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 2633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Device sub-block and page codes. 2733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 2833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC1_SBLOCK (0x04) 2933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC2_SBLOCK (0x05) 3033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC3_SBLOCK (0x06) 3133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC4_SBLOCK (0x07) 3233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SMC1_SBLOCK (0x08) 3333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SMC2_SBLOCK (0x09) 3433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SPI_SBLOCK (0x0a) 3533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_I2C_SBLOCK (0x0b) 3633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_TIMER_SBLOCK (0x0f) 3733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_RAND_SBLOCK (0x0e) 3833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC1_SBLOCK (0x10) 3933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC2_SBLOCK (0x11) 4033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC3_SBLOCK (0x12) 4133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA1_SBLOCK (0x14) 4233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA2_SBLOCK (0x15) 4333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA3_SBLOCK (0x16) 4433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA4_SBLOCK (0x17) 4533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_MCC1_SBLOCK (0x1c) 4633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 4733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC_SBLOCK(x) (x + 0x10) 4833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 4933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC1_PAGE (0x00) 5033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC2_PAGE (0x01) 5133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC3_PAGE (0x02) 5233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SCC4_PAGE (0x03) 5333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SMC1_PAGE (0x07) 5433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SMC2_PAGE (0x08) 5533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_SPI_PAGE (0x09) 5633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_I2C_PAGE (0x0a) 5733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_TIMER_PAGE (0x0a) 5833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_RAND_PAGE (0x0a) 5933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC1_PAGE (0x04) 6033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC2_PAGE (0x05) 6133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC3_PAGE (0x06) 6233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA1_PAGE (0x07) 6333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA2_PAGE (0x08) 6433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA3_PAGE (0x09) 6533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_IDMA4_PAGE (0x0a) 6633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_MCC1_PAGE (0x07) 6733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_MCC2_PAGE (0x08) 6833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 6933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_FCC_PAGE(x) (x + 0x04) 7033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 71e24e788abe0def81341fd23efae43e813678f7b1Laurent Pinchart/* CPM2-specific opcodes (see cpm.h for common opcodes) 7233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 7333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_CR_START_IDMA ((ushort)0x0009) 7433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 7533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define mk_cr_cmd(PG, SBC, MCN, OP) \ 7633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ((PG << 26) | (SBC << 21) | (MCN << 6) | OP) 7733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 7833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* The number of pages of host memory we allocate for CPM. This is 7933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * done early in kernel initialization to get physically contiguous 8033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * pages. 8133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 8233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define NUM_CPM_HOST_PAGES 2 8333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 8433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Export the base address of the communication processor registers 8533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * and dual port ram. 8633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 87449012daa92a60e42f0d55478641cfa796d51528Scott Woodextern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */ 8833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 8915f8c604a79c4840ed76eecf3af5d88b7c1dee9eScott Wood#define cpm_dpalloc cpm_muram_alloc 9015f8c604a79c4840ed76eecf3af5d88b7c1dee9eScott Wood#define cpm_dpfree cpm_muram_free 9115f8c604a79c4840ed76eecf3af5d88b7c1dee9eScott Wood#define cpm_dpram_addr cpm_muram_addr 9215f8c604a79c4840ed76eecf3af5d88b7c1dee9eScott Wood 9333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galaextern void cpm2_reset(void); 9433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 95dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart/* Baud rate generators. 96dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart*/ 97dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_RST ((uint)0x00020000) 98dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_EN ((uint)0x00010000) 99dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_EXTC_INT ((uint)0x00000000) 100dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000) 101dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000) 102dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_ATB ((uint)0x00002000) 103dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 104dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM_BRG_DIV16 ((uint)0x00000001) 105dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart 106dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM2_BRG_INT_CLK (get_brgfreq()) 107dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart#define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16) 108dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart 109dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchartextern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src); 110dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart 111dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart/* This function is used by UARTS, or anything else that uses a 16x 112dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart * oversampled clock. 113dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart */ 114dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchartstatic inline void cpm_setbrg(uint brg, uint rate) 115dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart{ 116dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT); 117dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart} 118dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart 119dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart/* This function is used to set high speed synchronous baud rate 120dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart * clocks. 121dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart */ 122dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchartstatic inline void cpm2_fastbrg(uint brg, uint rate, int div16) 123dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart{ 124dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT); 125dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart} 126dddb8d311157d054da5441385f681b8cc0e5a94bLaurent Pinchart 12733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Parameter RAM offsets from the base. 12833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 12933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SCC1 ((uint)0x8000) 13033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SCC2 ((uint)0x8100) 13133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SCC3 ((uint)0x8200) 13233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SCC4 ((uint)0x8300) 13333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_FCC1 ((uint)0x8400) 13433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_FCC2 ((uint)0x8500) 13533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_FCC3 ((uint)0x8600) 13633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_MCC1 ((uint)0x8700) 13733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SMC1_BASE ((uint)0x87fc) 13833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_IDMA1_BASE ((uint)0x87fe) 13933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_MCC2 ((uint)0x8800) 14033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SMC2_BASE ((uint)0x88fc) 14133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_IDMA2_BASE ((uint)0x88fe) 14233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SPI_BASE ((uint)0x89fc) 14333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_IDMA3_BASE ((uint)0x89fe) 14433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_TIMERS ((uint)0x8ae0) 14533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_REVNUM ((uint)0x8af0) 14633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_RAND ((uint)0x8af8) 14733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_I2C_BASE ((uint)0x8afc) 14833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_IDMA4_BASE ((uint)0x8afe) 14933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 15033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SCC_SIZE ((uint)0x100) 15133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_FCC_SIZE ((uint)0x100) 15233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SMC_SIZE ((uint)64) 15333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 15433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* The SMCs are relocated to any of the first eight DPRAM pages. 15533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * We will fix these at the first locations of DPRAM, until we 15633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * get some microcode patches :-). 15733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * The parameter ram space for the SMCs is fifty-some bytes, and 15833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * they are required to start on a 64 byte boundary. 15933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 16033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SMC1 (0) 16133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PROFF_SMC2 (64) 16233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 16333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 16433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Define enough so I can at least use the serial port as a UART. 16533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 16633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct smc_uart { 16733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_rbase; /* Rx Buffer descriptor base address */ 16833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_tbase; /* Tx Buffer descriptor base address */ 16933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char smc_rfcr; /* Rx function code */ 17033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char smc_tfcr; /* Tx function code */ 17133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_mrblr; /* Max receive buffer length */ 17233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_rstate; /* Internal */ 17333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_idp; /* Internal */ 17433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_rbptr; /* Internal */ 17533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_ibc; /* Internal */ 17633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_rxtmp; /* Internal */ 17733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_tstate; /* Internal */ 17833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_tdp; /* Internal */ 17933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_tbptr; /* Internal */ 18033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_tbc; /* Internal */ 18133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_txtmp; /* Internal */ 18233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_maxidl; /* Maximum idle characters */ 18333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_tmpidl; /* Temporary idle counter */ 18433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_brklen; /* Last received break length */ 18533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_brkec; /* rcv'd break condition counter */ 18633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_brkcr; /* xmt break count register */ 18733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort smc_rmask; /* Temporary bit mask */ 18833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint smc_stmp; /* SDMA Temp */ 18933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} smc_uart_t; 19033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 19133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SMC uart mode register (Internal memory map). 19233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 19333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_REN ((ushort)0x0001) 19433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_TEN ((ushort)0x0002) 19533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_DM ((ushort)0x000c) 19633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_SM_GCI ((ushort)0x0000) 19733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_SM_UART ((ushort)0x0020) 19833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_SM_TRANS ((ushort)0x0030) 19933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_SM_MASK ((ushort)0x0030) 20033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 20133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_REVD SMCMR_PM_EVEN 20233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 20333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_BS SMCMR_PEN 20433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 20533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 20633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 20733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 20833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SMC Event and Mask register. 20933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 21033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 21133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 21233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCM_TXE ((unsigned char)0x10) 21333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCM_BSY ((unsigned char)0x04) 21433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCM_TX ((unsigned char)0x02) 21533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SMCM_RX ((unsigned char)0x01) 21633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 21733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SCCs. 21833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 21933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_IRP ((uint)0x00040000) 22033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_GDE ((uint)0x00010000) 22133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 22233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 22333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 22433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_REVD ((uint)0x00002000) 22533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TRX ((uint)0x00001000) 22633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TTX ((uint)0x00000800) 22733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_CDP ((uint)0x00000400) 22833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_CTSP ((uint)0x00000200) 22933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_CDS ((uint)0x00000100) 23033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_CTSS ((uint)0x00000080) 23133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TFL ((uint)0x00000040) 23233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_RFW ((uint)0x00000020) 23333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_TXSY ((uint)0x00000010) 23433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 23533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 23633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 23733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_RTSM ((uint)0x00000002) 23833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRH_RSYN ((uint)0x00000001) 23933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 24033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 24133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 24233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 24333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 24433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 24533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TCI ((uint)0x10000000) 24633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 24733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 24833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 24933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 25033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RINV ((uint)0x02000000) 25133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TINV ((uint)0x01000000) 25233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 25333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 25433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 25533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 25633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 25733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 25833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 25933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 26033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 26133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 26233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 26333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TEND ((uint)0x00040000) 26433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 26533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 26633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 26733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 26833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 26933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 27033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 27133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 27233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 27333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 27433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 27533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 27633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 27733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 27833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 27933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 28033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 28133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 28233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 28333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 28433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 28533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 28633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_ENR ((uint)0x00000020) 28733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_ENT ((uint)0x00000010) 28833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 28933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 29033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 29133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 29233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 29333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 29433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 29533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 29633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 29733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 29833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 29933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_TODR_TOD ((ushort)0x8000) 30033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 30133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SCC Event and Mask register. 30233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 30333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCM_TXE ((unsigned char)0x10) 30433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCM_BSY ((unsigned char)0x04) 30533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCM_TX ((unsigned char)0x02) 30633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCM_RX ((unsigned char)0x01) 30733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 30833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct scc_param { 30933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_rbase; /* Rx Buffer descriptor base address */ 31033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_tbase; /* Tx Buffer descriptor base address */ 31133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char scc_rfcr; /* Rx function code */ 31233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char scc_tfcr; /* Tx function code */ 31333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_mrblr; /* Max receive buffer length */ 31433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_rstate; /* Internal */ 31533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_idp; /* Internal */ 31633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_rbptr; /* Internal */ 31733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_ibc; /* Internal */ 31833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_rxtmp; /* Internal */ 31933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_tstate; /* Internal */ 32033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_tdp; /* Internal */ 32133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_tbptr; /* Internal */ 32233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_tbc; /* Internal */ 32333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_txtmp; /* Internal */ 32433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_rcrc; /* Internal */ 32533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_tcrc; /* Internal */ 32633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} sccp_t; 32733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 328f4f62301c6f42127b7462274abfcbc278f84d59aHeiko Schocher/* Function code bits. 329f4f62301c6f42127b7462274abfcbc278f84d59aHeiko Schocher*/ 330f4f62301c6f42127b7462274abfcbc278f84d59aHeiko Schocher#define SCC_EB ((u_char) 0x10) /* Set big endian byte order */ 331f4f62301c6f42127b7462274abfcbc278f84d59aHeiko Schocher#define SCC_GBL ((u_char) 0x20) /* Snooping enabled */ 332f4f62301c6f42127b7462274abfcbc278f84d59aHeiko Schocher 33333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* CPM Ethernet through SCC1. 33433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 33533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct scc_enet { 33633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala sccp_t sen_genscc; 33733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_cpres; /* Preset CRC */ 33833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_cmask; /* Constant mask for CRC */ 33933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_crcec; /* CRC Error counter */ 34033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_alec; /* alignment error counter */ 34133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_disfc; /* discard frame counter */ 34233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_pads; /* Tx short frame pad character */ 34333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_retlim; /* Retry limit threshold */ 34433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_retcnt; /* Retry limit counter */ 34533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_maxflr; /* maximum frame length register */ 34633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_minflr; /* minimum frame length register */ 34733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_maxd1; /* maximum DMA1 length */ 34833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_maxd2; /* maximum DMA2 length */ 34933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_maxd; /* Rx max DMA */ 35033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_dmacnt; /* Rx DMA counter */ 35133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_maxb; /* Max BD byte count */ 35233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_gaddr1; /* Group address filter */ 35333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_gaddr2; 35433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_gaddr3; 35533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_gaddr4; 35633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf0data0; /* Save area 0 - current frame */ 35733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf0data1; /* Save area 1 - current frame */ 35833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf0rba; /* Internal */ 35933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf0crc; /* Internal */ 36033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_tbuf0bcnt; /* Internal */ 36133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_paddrh; /* physical address (MSB) */ 36233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_paddrm; 36333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_paddrl; /* physical address (LSB) */ 36433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_pper; /* persistence */ 36533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_rfbdptr; /* Rx first BD pointer */ 36633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_tfbdptr; /* Tx first BD pointer */ 36733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_tlbdptr; /* Tx last BD pointer */ 36833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf1data0; /* Save area 0 - current frame */ 36933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf1data1; /* Save area 1 - current frame */ 37033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf1rba; /* Internal */ 37133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint sen_tbuf1crc; /* Internal */ 37233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_tbuf1bcnt; /* Internal */ 37333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_txlen; /* Tx Frame length counter */ 37433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_iaddr1; /* Individual address filter */ 37533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_iaddr2; 37633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_iaddr3; 37733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_iaddr4; 37833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_boffcnt; /* Backoff counter */ 37933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 38033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala /* NOTE: Some versions of the manual have the following items 38133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * incorrectly documented. Below is the proper order. 38233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 38333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_taddrh; /* temp address (MSB) */ 38433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_taddrm; 38533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sen_taddrl; /* temp address (LSB) */ 38633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} scc_enet_t; 38733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 38833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 38933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SCC Event register as used by Ethernet. 39033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 39133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 39233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 39333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 39433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 39533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 39633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 39733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 39833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SCC Mode Register (PSMR) as used by Ethernet. 39933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 40033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 40133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 40233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 40333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 40433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 40533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 40633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 40733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 40833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 40933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 41033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 41133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 41233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 41333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 41433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SCC as UART 41533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 41633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct scc_uart { 41733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala sccp_t scc_genscc; 41833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_res1; /* Reserved */ 41933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint scc_res2; /* Reserved */ 42033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_maxidl; /* Maximum idle chars */ 42133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_idlc; /* temp idle counter */ 42233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_brkcr; /* Break count register */ 42333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_parec; /* receive parity error counter */ 42433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_frmec; /* receive framing error counter */ 42533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_nosec; /* receive noise counter */ 42633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_brkec; /* receive break condition counter */ 42733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_brkln; /* last received break length */ 42833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_uaddr1; /* UART address character 1 */ 42933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_uaddr2; /* UART address character 2 */ 43033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_rtemp; /* Temp storage */ 43133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_toseq; /* Transmit out of sequence char */ 43233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char1; /* control character 1 */ 43333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char2; /* control character 2 */ 43433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char3; /* control character 3 */ 43533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char4; /* control character 4 */ 43633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char5; /* control character 5 */ 43733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char6; /* control character 6 */ 43833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char7; /* control character 7 */ 43933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_char8; /* control character 8 */ 44033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_rccm; /* receive control character mask */ 44133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_rccr; /* receive control character register */ 44233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort scc_rlbc; /* receive last break character */ 44333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} scc_uart_t; 44433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 44533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* SCC Event and Mask registers when it is used as a UART. 44633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 44733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_GLR ((ushort)0x1000) 44833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_GLT ((ushort)0x0800) 44933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_AB ((ushort)0x0200) 45033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_IDL ((ushort)0x0100) 45133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_GRA ((ushort)0x0080) 45233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_BRKE ((ushort)0x0040) 45333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_BRKS ((ushort)0x0020) 45433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_CCR ((ushort)0x0008) 45533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_BSY ((ushort)0x0004) 45633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_TX ((ushort)0x0002) 45733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define UART_SCCM_RX ((ushort)0x0001) 45833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 45933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* The SCC PSMR when used as a UART. 46033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 46133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_FLC ((ushort)0x8000) 46233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_SL ((ushort)0x4000) 46333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_CL ((ushort)0x3000) 46433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_UM ((ushort)0x0c00) 46533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_FRZ ((ushort)0x0200) 46633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_RZS ((ushort)0x0100) 46733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_SYN ((ushort)0x0080) 46833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_DRT ((ushort)0x0040) 46933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_PEN ((ushort)0x0010) 47033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_RPM ((ushort)0x000c) 47133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_REVP ((ushort)0x0008) 47233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_TPM ((ushort)0x0003) 47333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCU_PSMR_TEVP ((ushort)0x0002) 47433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 47533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* CPM Transparent mode SCC. 47633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 47733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct scc_trans { 47833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala sccp_t st_genscc; 47933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint st_cpres; /* Preset CRC */ 48033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint st_cmask; /* Constant mask for CRC */ 48133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} scc_trans_t; 48233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 48333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* How about some FCCs..... 48433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 48533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_DIAG_NORM ((uint)0x00000000) 48633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_DIAG_LE ((uint)0x40000000) 48733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_DIAG_AE ((uint)0x80000000) 48833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000) 48933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TCI ((uint)0x20000000) 49033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TRX ((uint)0x10000000) 49133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TTX ((uint)0x08000000) 49233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_CDP ((uint)0x04000000) 49333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_CTSP ((uint)0x02000000) 49433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_CDS ((uint)0x01000000) 49533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_CTSS ((uint)0x00800000) 49633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_SYNL_NONE ((uint)0x00000000) 49733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000) 49833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_SYNL_8 ((uint)0x00008000) 49933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_SYNL_16 ((uint)0x0000c000) 50033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_RTSM ((uint)0x00002000) 50133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_RENC_NRZ ((uint)0x00000000) 50233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_RENC_NRZI ((uint)0x00000800) 50333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_REVD ((uint)0x00000400) 50433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TENC_NRZ ((uint)0x00000000) 50533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TENC_NRZI ((uint)0x00000100) 50633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TCRC_16 ((uint)0x00000000) 50733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_TCRC_32 ((uint)0x00000080) 50833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_ENR ((uint)0x00000020) 50933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_ENT ((uint)0x00000010) 51033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_MODE_ENET ((uint)0x0000000c) 51133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_MODE_ATM ((uint)0x0000000a) 51233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_GFMR_MODE_HDLC ((uint)0x00000000) 51333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 51433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Generic FCC parameter ram. 51533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 51633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct fcc_param { 51733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_riptr; /* Rx Internal temp pointer */ 51833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_tiptr; /* Tx Internal temp pointer */ 51933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_res1; 52033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */ 52133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_rstate; /* Upper byte is Func code, must be set */ 52233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_rbase; /* Receive BD base */ 52333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_rbdstat; /* RxBD status */ 52433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_rbdlen; /* RxBD down counter */ 52533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_rdptr; /* RxBD internal data pointer */ 52633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_tstate; /* Upper byte is Func code, must be set */ 52733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_tbase; /* Transmit BD base */ 52833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_tbdstat; /* TxBD status */ 52933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fcc_tbdlen; /* TxBD down counter */ 53033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_tdptr; /* TxBD internal data pointer */ 53133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_rbptr; /* Rx BD Internal buf pointer */ 53233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_tbptr; /* Tx BD Internal buf pointer */ 53333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_rcrc; /* Rx temp CRC */ 53433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_res2; 53533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fcc_tcrc; /* Tx temp CRC */ 53633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} fccp_t; 53733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 53833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 53933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Ethernet controller through FCC. 54033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 54133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct fcc_enet { 54233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala fccp_t fen_genfcc; 54333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_statbuf; /* Internal status buffer */ 54433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_camptr; /* CAM address */ 54533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_cmask; /* Constant mask for CRC */ 54633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_cpres; /* Preset CRC */ 54733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_crcec; /* CRC Error counter */ 54833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_alec; /* alignment error counter */ 54933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_disfc; /* discard frame counter */ 55033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_retlim; /* Retry limit */ 55133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_retcnt; /* Retry counter */ 55233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_pper; /* Persistence */ 55333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_boffcnt; /* backoff counter */ 55433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_gaddrh; /* Group address filter, high 32-bits */ 55533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_gaddrl; /* Group address filter, low 32-bits */ 55633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_tfcstat; /* out of sequence TxBD */ 55733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_tfclen; 55833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_tfcptr; 55933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_mflr; /* Maximum frame length (1518) */ 56033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_paddrh; /* MAC address */ 56133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_paddrm; 56233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_paddrl; 56333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_ibdcount; /* Internal BD counter */ 56433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_ibdstart; /* Internal BD start pointer */ 56533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_ibdend; /* Internal BD end pointer */ 56633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_txlen; /* Internal Tx frame length counter */ 56733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_ibdbase[8]; /* Internal use */ 56833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_iaddrh; /* Individual address filter */ 56933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_iaddrl; 57033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_minflr; /* Minimum frame length (64) */ 57133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_taddrh; /* Filter transfer MAC address */ 57233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_taddrm; 57333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_taddrl; 57433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_padptr; /* Pointer to pad byte buffer */ 57533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_cftype; /* control frame type */ 57633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_cfrange; /* control frame range */ 57733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_maxb; /* maximum BD count */ 57833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_maxd1; /* Max DMA1 length (1520) */ 57933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_maxd2; /* Max DMA2 length (1520) */ 58033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_maxd; /* internal max DMA count */ 58133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_dmacnt; /* internal DMA counter */ 58233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_octc; /* Total octect counter */ 58333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_colc; /* Total collision counter */ 58433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_broc; /* Total broadcast packet counter */ 58533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_mulc; /* Total multicast packet count */ 58633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_uspc; /* Total packets < 64 bytes */ 58733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_frgc; /* Total packets < 64 bytes with errors */ 58833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_ospc; /* Total packets > 1518 */ 58933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_jbrc; /* Total packets > 1518 with errors */ 59033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_p64c; /* Total packets == 64 bytes */ 59133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_p65c; /* Total packets 64 < bytes <= 127 */ 59233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_p128c; /* Total packets 127 < bytes <= 255 */ 59333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_p256c; /* Total packets 256 < bytes <= 511 */ 59433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_p512c; /* Total packets 512 < bytes <= 1023 */ 59533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */ 59633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint fen_cambuf; /* Internal CAM buffer poiner */ 59733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_rfthr; /* Received frames threshold */ 59833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort fen_rfcnt; /* Received frames count */ 59933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} fcc_enet_t; 60033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 60133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* FCC Event/Mask register as used by Ethernet. 60233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 60333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 60433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */ 60533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */ 60633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 60733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */ 60833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */ 60933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 61033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 61133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 61233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* FCC Mode Register (FPSMR) as used by Ethernet. 61333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 61433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */ 61533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */ 61633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */ 61733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */ 61833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */ 61933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */ 62033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */ 62133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */ 62233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */ 62333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */ 62433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */ 62533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */ 62633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */ 62733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 62833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* IIC parameter RAM. 62933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 63033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct iic { 63133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_rbase; /* Rx Buffer descriptor base address */ 63233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_tbase; /* Tx Buffer descriptor base address */ 63333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char iic_rfcr; /* Rx function code */ 63433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char iic_tfcr; /* Tx function code */ 63533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_mrblr; /* Max receive buffer length */ 63633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint iic_rstate; /* Internal */ 63733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint iic_rdp; /* Internal */ 63833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_rbptr; /* Internal */ 63933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_rbc; /* Internal */ 64033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint iic_rxtmp; /* Internal */ 64133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint iic_tstate; /* Internal */ 64233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint iic_tdp; /* Internal */ 64333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_tbptr; /* Internal */ 64433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort iic_tbc; /* Internal */ 64533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint iic_txtmp; /* Internal */ 64633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} iic_t; 64733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 64833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* IDMA parameter RAM 64933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 65033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct idma { 65133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort ibase; /* IDMA buffer descriptor table base address */ 65233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort dcm; /* DMA channel mode */ 65333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort ibdptr; /* IDMA current buffer descriptor pointer */ 65433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort dpr_buf; /* IDMA transfer buffer base address */ 65533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort buf_inv; /* internal buffer inventory */ 65633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort ss_max; /* steady-state maximum transfer size */ 65733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort dpr_in_ptr; /* write pointer inside the internal buffer */ 65833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort sts; /* source transfer size */ 65933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort dpr_out_ptr; /* read pointer inside the internal buffer */ 66033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort seob; /* source end of burst */ 66133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort deob; /* destination end of burst */ 66233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort dts; /* destination transfer size */ 66333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort ret_add; /* return address when working in ERM=1 mode */ 66433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala ushort res0; /* reserved */ 66533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint bd_cnt; /* internal byte count */ 66633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint s_ptr; /* source internal data pointer */ 66733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint d_ptr; /* destination internal data pointer */ 66833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint istate; /* internal state */ 66933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char res1[20]; /* pad to 64-byte length */ 67033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} idma_t; 67133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 67233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* DMA channel mode bit fields 67333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 67433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */ 67533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */ 67633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */ 67733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */ 67833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */ 67933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */ 68033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */ 68133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */ 68233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */ 68333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */ 68433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */ 68533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */ 68633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */ 68733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */ 68833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */ 68933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */ 69033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */ 69133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */ 69233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 69333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* IDMA Buffer Descriptors 69433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 69533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct idma_bd { 69633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint flags; 69733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint len; /* data length */ 69833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint src; /* source data buffer pointer */ 69933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala uint dst; /* destination data buffer pointer */ 70033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} idma_bd_t; 70133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 70233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* IDMA buffer descriptor flag bit fields 70333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 70433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_V ((uint)0x80000000) /* valid */ 70533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_W ((uint)0x20000000) /* wrap */ 70633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_I ((uint)0x10000000) /* interrupt */ 70733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_L ((uint)0x08000000) /* last */ 70833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */ 70933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_SDN ((uint)0x00400000) /* source done */ 71033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */ 71133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */ 71233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */ 71333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */ 71433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */ 71533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */ 71633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */ 71733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */ 71833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */ 71933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 72033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* per-channel IDMA registers 72133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 72233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galatypedef struct im_idma { 72333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char idsr; /* IDMAn event status register */ 72433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char res0[3]; 72533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char idmr; /* IDMAn event mask register */ 72633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala u_char res1[3]; 72733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala} im_idma_t; 72833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 72933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* IDMA event register bit fields 73033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 73133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */ 73233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */ 73333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */ 73433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */ 73533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 73633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* RISC Controller Configuration Register (RCCR) bit fields 73733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 73833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_TIME ((uint)0x80000000) /* timer enable */ 73933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */ 74033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */ 74133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */ 74233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */ 74333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */ 74433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */ 74533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */ 74633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */ 74733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */ 74833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */ 74933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */ 75033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */ 75133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */ 75233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */ 75333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */ 75433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */ 75533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */ 75633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */ 75733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */ 75833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */ 75933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */ 76033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */ 76133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */ 76233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */ 76333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */ 76433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */ 76533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */ 76633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */ 76733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */ 76833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */ 76933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */ 77033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */ 77133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */ 77233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */ 77333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */ 77433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */ 77533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */ 77633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 77733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/*----------------------------------------------------------------------- 77833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * CMXFCR - CMX FCC Clock Route Register 77933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 78033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_FC1 0x40000000 /* FCC1 connection */ 78133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */ 78233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */ 78333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_FC2 0x00400000 /* FCC2 connection */ 78433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */ 78533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */ 78633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_FC3 0x00004000 /* FCC3 connection */ 78733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */ 78833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */ 78933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 79033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */ 79133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */ 79233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */ 79333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */ 79433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */ 79533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */ 79633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */ 79733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */ 79833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 79933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */ 80033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */ 80133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */ 80233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */ 80333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */ 80433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */ 80533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */ 80633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */ 80733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 80833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */ 80933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */ 81033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */ 81133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */ 81233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */ 81333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */ 81433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */ 81533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */ 81633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 81733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */ 81833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */ 81933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */ 82033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */ 82133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */ 82233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */ 82333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */ 82433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */ 82533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 82633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */ 82733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */ 82833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */ 82933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */ 83033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */ 83133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */ 83233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */ 83333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */ 83433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 83533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */ 83633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */ 83733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */ 83833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */ 83933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */ 84033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */ 84133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */ 84233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */ 84333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 84433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/*----------------------------------------------------------------------- 84533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * CMXSCR - CMX SCC Clock Route Register 84633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 84733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */ 84833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_SC1 0x40000000 /* SCC1 connection */ 84933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */ 85033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */ 85133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */ 85233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_SC2 0x00400000 /* SCC2 connection */ 85333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */ 85433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */ 85533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */ 85633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_SC3 0x00004000 /* SCC3 connection */ 85733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */ 85833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */ 85933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */ 86033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_SC4 0x00000040 /* SCC4 connection */ 86133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */ 86233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */ 86333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 86433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */ 86533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */ 86633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */ 86733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */ 86833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */ 86933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */ 87033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */ 87133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */ 87233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 87333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */ 87433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */ 87533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */ 87633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */ 87733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */ 87833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */ 87933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */ 88033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */ 88133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 88233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */ 88333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */ 88433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */ 88533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */ 88633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */ 88733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */ 88833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */ 88933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */ 89033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 89133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */ 89233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */ 89333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */ 89433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */ 89533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */ 89633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */ 89733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */ 89833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */ 89933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 90033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */ 90133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */ 90233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */ 90333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */ 90433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */ 90533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */ 90633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */ 90733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */ 90833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 90933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */ 91033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */ 91133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */ 91233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */ 91333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */ 91433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */ 91533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */ 91633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */ 91733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 91833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */ 91933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */ 92033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */ 92133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */ 92233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */ 92333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */ 92433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */ 92533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */ 92633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 92733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */ 92833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */ 92933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */ 93033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */ 93133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */ 93233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */ 93333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ 93433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ 93533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 93633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/*----------------------------------------------------------------------- 93733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * SIUMCR - SIU Module Configuration Register 4-31 93833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 93933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */ 94033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */ 94133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */ 94233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_CDIS 0x10000000 /* Core Disable */ 94333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/ 94433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_DPPC01 0x04000000 /* - " - */ 94533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_DPPC10 0x08000000 /* - " - */ 94633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_DPPC11 0x0c000000 /* - " - */ 94733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */ 94833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_L2CPC01 0x01000000 /* - " - */ 94933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_L2CPC10 0x02000000 /* - " - */ 95033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_L2CPC11 0x03000000 /* - " - */ 95133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */ 95233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_LBPC01 0x00400000 /* - " - */ 95333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_LBPC10 0x00800000 /* - " - */ 95433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_LBPC11 0x00c00000 /* - " - */ 95533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/ 95633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_APPC01 0x00100000 /* - " - */ 95733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_APPC10 0x00200000 /* - " - */ 95833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_APPC11 0x00300000 /* - " - */ 95933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */ 96033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_CS10PC01 0x00040000 /* - " - */ 96133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_CS10PC10 0x00080000 /* - " - */ 96233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_CS10PC11 0x000c0000 /* - " - */ 96333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */ 96433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_BCTLC01 0x00010000 /* - " - */ 96533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_BCTLC10 0x00020000 /* - " - */ 96633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_BCTLC11 0x00030000 /* - " - */ 96733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */ 96833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_MMR01 0x00004000 /* - " - */ 96933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_MMR10 0x00008000 /* - " - */ 97033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_MMR11 0x0000c000 /* - " - */ 97133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/ 97233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 97333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/*----------------------------------------------------------------------- 97433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * SCCR - System Clock Control Register 9-8 97533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala*/ 97633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */ 97733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */ 97833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ 97933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define SCCR_PCIDF_SHIFT 3 98033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 98133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#ifndef CPM_IMMR_OFFSET 98233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPM_IMMR_OFFSET 0x101a8 98333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#endif 98433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 98533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ 98633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 98733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK 98833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * in order to use clock-computing stuff below for the FCC x 98933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 99033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 99133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Automatically generates register configurations */ 99233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */ 99333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 99433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */ 99533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */ 99633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */ 99733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */ 99833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */ 99933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */ 100033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 100133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_F1RXCLK PC_CLK(F1_RXCLK) 100233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_F1TXCLK PC_CLK(F1_TXCLK) 100333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK)) 100433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMX1_CLK_MASK ((uint)0xff000000) 100533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 100633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_F2RXCLK PC_CLK(F2_RXCLK) 100733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_F2TXCLK PC_CLK(F2_TXCLK) 100833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK)) 100933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMX2_CLK_MASK ((uint)0x00ff0000) 101033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 101133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_F3RXCLK PC_CLK(F3_RXCLK) 101233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC_F3TXCLK PC_CLK(F3_TXCLK) 101333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK)) 101433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CMX3_CLK_MASK ((uint)0x0000ff00) 101533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 101633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK) 101733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE) 101833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 101933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK) 102033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 102133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* I/O Pin assignment for FCC1. I don't yet know the best way to do this, 102233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * but there is little variation among the choices. 102333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 102433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_COL 0x00000001U 102533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_CRS 0x00000002U 102633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_TXER 0x00000004U 102733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_TXEN 0x00000008U 102833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_RXDV 0x00000010U 102933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_RXER 0x00000020U 103033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_TXDAT 0x00003c00U 103133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_RXDAT 0x0003c000U 103233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT) 103333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \ 103433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala PA1_RXDV | PA1_RXER) 103533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV) 103633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER) 103733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 103833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 103933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* I/O Pin assignment for FCC2. I don't yet know the best way to do this, 104033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * but there is little variation among the choices. 104133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 104233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_TXER 0x00000001U 104333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_RXDV 0x00000002U 104433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_TXEN 0x00000004U 104533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_RXER 0x00000008U 104633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_COL 0x00000010U 104733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_CRS 0x00000020U 104833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_TXDAT 0x000003c0U 104933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_RXDAT 0x00003c00U 105033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \ 105133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala PB2_RXER | PB2_RXDV | PB2_TXER) 105233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_PSORB1 (PB2_TXEN) 105333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV) 105433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER) 105533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 105633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 105733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* I/O Pin assignment for FCC3. I don't yet know the best way to do this, 105833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala * but there is little variation among the choices. 105933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala */ 106033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_RXDV 0x00004000U 106133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_RXER 0x00008000U 106233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_TXER 0x00010000U 106333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_TXEN 0x00020000U 106433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_COL 0x00040000U 106533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_CRS 0x00080000U 106633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_TXDAT 0x0f000000U 106733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC3_TXDAT 0x00000010U 106833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_RXDAT 0x00f00000U 106933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \ 107033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN) 107133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_PSORB1 0 107233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV) 107333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER) 107433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define PC3_DIRC1 (PC3_TXDAT) 107533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 107633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Handy macro to specify mem for FCCs*/ 107733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128)) 107833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0) 107933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1) 108033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2) 108133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 108233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala/* Clocks and GRG's */ 108333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 108433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galaenum cpm_clk_dir { 108533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_RX, 108633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_TX, 108733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_RTX 108833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala}; 108933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 109033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galaenum cpm_clk_target { 109133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_SCC1, 109233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_SCC2, 109333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_SCC3, 109433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_SCC4, 109533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_FCC1, 109633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_FCC2, 10972652d4ec4a363487d0106a8bf51f1b081dd7e397Scott Wood CPM_CLK_FCC3, 10982652d4ec4a363487d0106a8bf51f1b081dd7e397Scott Wood CPM_CLK_SMC1, 10992652d4ec4a363487d0106a8bf51f1b081dd7e397Scott Wood CPM_CLK_SMC2, 110033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala}; 110133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 110233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galaenum cpm_clk { 110333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_NONE = 0, 110433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG1, /* Baud Rate Generator 1 */ 110533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG2, /* Baud Rate Generator 2 */ 110633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG3, /* Baud Rate Generator 3 */ 110733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG4, /* Baud Rate Generator 4 */ 110833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG5, /* Baud Rate Generator 5 */ 110933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG6, /* Baud Rate Generator 6 */ 111033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG7, /* Baud Rate Generator 7 */ 111133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_BRG8, /* Baud Rate Generator 8 */ 111233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK1, /* Clock 1 */ 111333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK2, /* Clock 2 */ 111433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK3, /* Clock 3 */ 111533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK4, /* Clock 4 */ 111633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK5, /* Clock 5 */ 111733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK6, /* Clock 6 */ 111833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK7, /* Clock 7 */ 111933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK8, /* Clock 8 */ 112033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK9, /* Clock 9 */ 112133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK10, /* Clock 10 */ 112233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK11, /* Clock 11 */ 112333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK12, /* Clock 12 */ 112433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK13, /* Clock 13 */ 112533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK14, /* Clock 14 */ 112633d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK15, /* Clock 15 */ 112733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK16, /* Clock 16 */ 112833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK17, /* Clock 17 */ 112933d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK18, /* Clock 18 */ 113033d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK19, /* Clock 19 */ 113133d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK20, /* Clock 20 */ 113233d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala CPM_CLK_DUMMY 113333d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala}; 113433d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 113533d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Galaextern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode); 11362652d4ec4a363487d0106a8bf51f1b081dd7e397Scott Woodextern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock); 113733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala 11387f21f52940212c25b4387c2450018e161043549aScott Wood#define CPM_PIN_INPUT 0 11397f21f52940212c25b4387c2450018e161043549aScott Wood#define CPM_PIN_OUTPUT 1 11407f21f52940212c25b4387c2450018e161043549aScott Wood#define CPM_PIN_PRIMARY 0 11417f21f52940212c25b4387c2450018e161043549aScott Wood#define CPM_PIN_SECONDARY 2 11427f21f52940212c25b4387c2450018e161043549aScott Wood#define CPM_PIN_GPIO 4 11437f21f52940212c25b4387c2450018e161043549aScott Wood#define CPM_PIN_OPENDRAIN 8 11447f21f52940212c25b4387c2450018e161043549aScott Wood 11457f21f52940212c25b4387c2450018e161043549aScott Woodvoid cpm2_set_pin(int port, int pin, int flags); 11467f21f52940212c25b4387c2450018e161043549aScott Wood 114733d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#endif /* __CPM2__ */ 114833d71d26ba982f99b8cb76b86b2e1e0a0964a8acKumar Gala#endif /* __KERNEL__ */ 1149