reg.h revision 53b56ca0195b8a2a098a358088ecfefafb030b40
1/* 2 * Contains the definition of registers common to all PowerPC variants. 3 * If a register definition has been changed in a different PowerPC 4 * variant, we will case it in #ifndef XXX ... #endif, and have the 5 * number used in the Programming Environments Manual For 32-Bit 6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 7 */ 8 9#ifndef _ASM_POWERPC_REG_H 10#define _ASM_POWERPC_REG_H 11#ifdef __KERNEL__ 12 13#include <linux/stringify.h> 14#include <asm/cputable.h> 15 16/* Pickup Book E specific registers. */ 17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 18#include <asm/reg_booke.h> 19#endif /* CONFIG_BOOKE || CONFIG_40x */ 20 21#ifdef CONFIG_FSL_EMB_PERFMON 22#include <asm/reg_fsl_emb.h> 23#endif 24 25#ifdef CONFIG_8xx 26#include <asm/reg_8xx.h> 27#endif /* CONFIG_8xx */ 28 29#define MSR_SF_LG 63 /* Enable 64 bit mode */ 30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 31#define MSR_HV_LG 60 /* Hypervisor state */ 32#define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */ 33#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ 34#define MSR_TS_LG 33 /* Trans Mem state (2 bits) */ 35#define MSR_TM_LG 32 /* Trans Mem Available */ 36#define MSR_VEC_LG 25 /* Enable AltiVec */ 37#define MSR_VSX_LG 23 /* Enable VSX */ 38#define MSR_POW_LG 18 /* Enable Power Management */ 39#define MSR_WE_LG 18 /* Wait State Enable */ 40#define MSR_TGPR_LG 17 /* TLB Update registers in use */ 41#define MSR_CE_LG 17 /* Critical Interrupt Enable */ 42#define MSR_ILE_LG 16 /* Interrupt Little Endian */ 43#define MSR_EE_LG 15 /* External Interrupt Enable */ 44#define MSR_PR_LG 14 /* Problem State / Privilege Level */ 45#define MSR_FP_LG 13 /* Floating Point enable */ 46#define MSR_ME_LG 12 /* Machine Check Enable */ 47#define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 48#define MSR_SE_LG 10 /* Single Step */ 49#define MSR_BE_LG 9 /* Branch Trace */ 50#define MSR_DE_LG 9 /* Debug Exception Enable */ 51#define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 52#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 53#define MSR_IR_LG 5 /* Instruction Relocate */ 54#define MSR_DR_LG 4 /* Data Relocate */ 55#define MSR_PE_LG 3 /* Protection Enable */ 56#define MSR_PX_LG 2 /* Protection Exclusive Mode */ 57#define MSR_PMM_LG 2 /* Performance monitor */ 58#define MSR_RI_LG 1 /* Recoverable Exception */ 59#define MSR_LE_LG 0 /* Little Endian */ 60 61#ifdef __ASSEMBLY__ 62#define __MASK(X) (1<<(X)) 63#else 64#define __MASK(X) (1UL<<(X)) 65#endif 66 67#ifdef CONFIG_PPC64 68#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 69#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 70#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 71#else 72/* so tests for these bits fail on 32-bit */ 73#define MSR_SF 0 74#define MSR_ISF 0 75#define MSR_HV 0 76#endif 77 78#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 79#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ 80#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 81#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 82#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 83#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 84#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 85#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 86#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 87#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 88#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 89#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 90#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 91#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 92#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 93#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 94#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 95#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 96#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 97#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 98#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 99#ifndef MSR_PMM 100#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ 101#endif 102#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 103#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 104 105#define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ 106#define MSR_TS_N 0 /* Non-transactional */ 107#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ 108#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */ 109#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */ 110#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */ 111#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) 112#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) 113 114/* Reason codes describing kernel causes for transaction aborts. By 115 convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if 116 the failure is persistent. 117*/ 118#define TM_CAUSE_RESCHED 0xfe 119#define TM_CAUSE_TLBI 0xfc 120#define TM_CAUSE_FAC_UNAV 0xfa 121#define TM_CAUSE_SYSCALL 0xf9 /* Persistent */ 122#define TM_CAUSE_MISC 0xf6 123#define TM_CAUSE_SIGNAL 0xf4 124 125#if defined(CONFIG_PPC_BOOK3S_64) 126#define MSR_64BIT MSR_SF 127 128/* Server variant */ 129#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV 130#define MSR_KERNEL MSR_ | MSR_64BIT 131#define MSR_USER32 MSR_ | MSR_PR | MSR_EE 132#define MSR_USER64 MSR_USER32 | MSR_64BIT 133#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx) 134/* Default MSR for kernel mode. */ 135#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 136#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 137#endif 138 139#ifndef MSR_64BIT 140#define MSR_64BIT 0 141#endif 142 143/* Floating Point Status and Control Register (FPSCR) Fields */ 144#define FPSCR_FX 0x80000000 /* FPU exception summary */ 145#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 146#define FPSCR_VX 0x20000000 /* Invalid operation summary */ 147#define FPSCR_OX 0x10000000 /* Overflow exception summary */ 148#define FPSCR_UX 0x08000000 /* Underflow exception summary */ 149#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 150#define FPSCR_XX 0x02000000 /* Inexact exception summary */ 151#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 152#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 153#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 154#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 155#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 156#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 157#define FPSCR_FR 0x00040000 /* Fraction rounded */ 158#define FPSCR_FI 0x00020000 /* Fraction inexact */ 159#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 160#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 161#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 162#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 163#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 164#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 165#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 166#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 167#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 168#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 169#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 170#define FPSCR_RN 0x00000003 /* FPU rounding control */ 171 172/* Bit definitions for SPEFSCR. */ 173#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ 174#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ 175#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ 176#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ 177#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ 178#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ 179#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ 180#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ 181#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ 182#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ 183#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ 184#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ 185#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ 186#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ 187#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ 188#define SPEFSCR_OV 0x00004000 /* Integer overflow */ 189#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ 190#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ 191#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ 192#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ 193#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ 194#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ 195#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ 196#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ 197#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ 198#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ 199#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ 200#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ 201 202/* Special Purpose Registers (SPRNs)*/ 203 204#ifdef CONFIG_40x 205#define SPRN_PID 0x3B1 /* Process ID */ 206#else 207#define SPRN_PID 0x030 /* Process ID */ 208#ifdef CONFIG_BOOKE 209#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ 210#endif 211#endif 212 213#define SPRN_CTR 0x009 /* Count Register */ 214#define SPRN_DSCR 0x11 215#define SPRN_CFAR 0x1c /* Come From Address Register */ 216#define SPRN_AMR 0x1d /* Authority Mask Register */ 217#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */ 218#define SPRN_AMOR 0x15d /* Authority Mask Override Register */ 219#define SPRN_ACOP 0x1F /* Available Coprocessor Register */ 220#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ 221#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ 222#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ 223#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ 224#define SPRN_CTRLF 0x088 225#define SPRN_CTRLT 0x098 226#define CTRL_CT 0xc0000000 /* current thread */ 227#define CTRL_CT0 0x80000000 /* thread 0 */ 228#define CTRL_CT1 0x40000000 /* thread 1 */ 229#define CTRL_TE 0x00c00000 /* thread enable */ 230#define CTRL_RUNLATCH 0x1 231#define SPRN_DAWR 0xB4 232#define SPRN_DAWRX 0xBC 233#define DAWRX_USER (1UL << 0) 234#define DAWRX_KERNEL (1UL << 1) 235#define DAWRX_HYP (1UL << 2) 236#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 237#define SPRN_DABR2 0x13D /* e300 */ 238#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 239#define DABRX_USER (1UL << 0) 240#define DABRX_KERNEL (1UL << 1) 241#define DABRX_HYP (1UL << 2) 242#define DABRX_BTI (1UL << 3) 243#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) 244#define SPRN_DAR 0x013 /* Data Address Register */ 245#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 246#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 247#define DSISR_NOHPTE 0x40000000 /* no translation found */ 248#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 249#define DSISR_ISSTORE 0x02000000 /* access was a store */ 250#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 251#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 252#define DSISR_KEYFAULT 0x00200000 /* Key fault */ 253#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ 254#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ 255#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 256#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 257#define SPRN_SPURR 0x134 /* Scaled PURR */ 258#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */ 259#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */ 260#define SPRN_HDSISR 0x132 261#define SPRN_HDAR 0x133 262#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */ 263#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 264#define SPRN_RMOR 0x138 /* Real mode offset register */ 265#define SPRN_HRMOR 0x139 /* Real mode offset register */ 266#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 267#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 268#define SPRN_FSCR 0x099 /* Facility Status & Control Register */ 269#define FSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ 270#define FSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ 271#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ 272#define HFSCR_TAR (1 << (63-55)) /* Enable Target Address Register */ 273#define HFSCR_TM (1 << (63-58)) /* Enable Transactional Memory */ 274#define HFSCR_PM (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */ 275#define HFSCR_BHRB (1 << (63-59)) /* Enable Branch History Rolling Buffer*/ 276#define HFSCR_DSCR (1 << (63-61)) /* Enable Data Stream Control Register */ 277#define HFSCR_VECVSX (1 << (63-62)) /* Enable VMX/VSX */ 278#define HFSCR_FP (1 << (63-63)) /* Enable Floating Point */ 279#define SPRN_TAR 0x32f /* Target Address Register */ 280#define SPRN_LPCR 0x13E /* LPAR Control Register */ 281#define LPCR_VPM0 (1ul << (63-0)) 282#define LPCR_VPM1 (1ul << (63-1)) 283#define LPCR_ISL (1ul << (63-2)) 284#define LPCR_VC_SH (63-2) 285#define LPCR_DPFD_SH (63-11) 286#define LPCR_VRMASD (0x1ful << (63-16)) 287#define LPCR_VRMA_L (1ul << (63-12)) 288#define LPCR_VRMA_LP0 (1ul << (63-15)) 289#define LPCR_VRMA_LP1 (1ul << (63-16)) 290#define LPCR_VRMASD_SH (63-16) 291#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ 292#define LPCR_RMLS_SH (63-37) 293#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ 294#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ 295#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ 296#define LPCR_PECE 0x00007000 /* powersave exit cause enable */ 297#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ 298#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ 299#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */ 300#define LPCR_MER 0x00000800 /* Mediated External Exception */ 301#define LPCR_LPES 0x0000000c 302#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */ 303#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */ 304#define LPCR_LPES_SH 2 305#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */ 306#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */ 307#ifndef SPRN_LPID 308#define SPRN_LPID 0x13F /* Logical Partition Identifier */ 309#endif 310#define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */ 311#define SPRN_HMER 0x150 /* Hardware m? error recovery */ 312#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */ 313#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ 314#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ 315#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */ 316#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */ 317#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */ 318#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 319#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 320#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 321#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 322#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 323#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 324#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 325#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 326#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 327#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 328#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 329#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 330#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 331#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 332#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 333#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 334#define SPRN_PPR 0x380 /* SMT Thread status Register */ 335 336#define SPRN_DEC 0x016 /* Decrement Register */ 337#define SPRN_DER 0x095 /* Debug Enable Regsiter */ 338#define DER_RSTE 0x40000000 /* Reset Interrupt */ 339#define DER_CHSTPE 0x20000000 /* Check Stop */ 340#define DER_MCIE 0x10000000 /* Machine Check Interrupt */ 341#define DER_EXTIE 0x02000000 /* External Interrupt */ 342#define DER_ALIE 0x01000000 /* Alignment Interrupt */ 343#define DER_PRIE 0x00800000 /* Program Interrupt */ 344#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ 345#define DER_DECIE 0x00200000 /* Decrementer Interrupt */ 346#define DER_SYSIE 0x00040000 /* System Call Interrupt */ 347#define DER_TRE 0x00020000 /* Trace Interrupt */ 348#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ 349#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ 350#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ 351#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ 352#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ 353#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ 354#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ 355#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 356#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 357#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 358#define SPRN_EAR 0x11A /* External Address Register */ 359#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 360#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 361#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 362#define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */ 363#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 364#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 365#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 366#define HID0_SBCLK (1<<27) 367#define HID0_EICE (1<<26) 368#define HID0_TBEN (1<<26) /* Timebase enable - 745x */ 369#define HID0_ECLK (1<<25) 370#define HID0_PAR (1<<24) 371#define HID0_STEN (1<<24) /* Software table search enable - 745x */ 372#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ 373#define HID0_DOZE (1<<23) 374#define HID0_NAP (1<<22) 375#define HID0_SLEEP (1<<21) 376#define HID0_DPM (1<<20) 377#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ 378#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ 379#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ 380#define HID0_ICE (1<<15) /* Instruction Cache Enable */ 381#define HID0_DCE (1<<14) /* Data Cache Enable */ 382#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 383#define HID0_DLOCK (1<<12) /* Data Cache Lock */ 384#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 385#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 386#define HID0_SPD (1<<9) /* Speculative disable */ 387#define HID0_DAPUEN (1<<8) /* Debug APU enable */ 388#define HID0_SGE (1<<7) /* Store Gathering Enable */ 389#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 390#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 391#define HID0_LRSTK (1<<4) /* Link register stack - 745x */ 392#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ 393#define HID0_ABE (1<<3) /* Address Broadcast Enable */ 394#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ 395#define HID0_BHTE (1<<2) /* Branch History Table Enable */ 396#define HID0_BTCD (1<<1) /* Branch target cache disable */ 397#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ 398#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ 399 400#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 401#ifdef CONFIG_6xx 402#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 403#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 404#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 405#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 406#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 407#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 408#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 409#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ 410#define HID1_PS (1<<16) /* 750FX PLL selection */ 411#endif 412#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ 413#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ 414#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 415#define SPRN_IABR2 0x3FA /* 83xx */ 416#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 417#define SPRN_HID4 0x3F4 /* 970 HID4 */ 418#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ 419#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ 420#define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */ 421#define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */ 422#define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */ 423#define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */ 424#define HID4_LPID1_SH 0 /* partition ID top 2 bits */ 425#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ 426#define SPRN_HID5 0x3F6 /* 970 HID5 */ 427#define SPRN_HID6 0x3F9 /* BE HID 6 */ 428#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ 429#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ 430#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ 431#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ 432#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ 433#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ 434#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ 435#define SPRN_TSC 0x3FD /* Thread switch control on others */ 436#define SPRN_TST 0x3FC /* Thread switch timeout on others */ 437#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) 438#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 439#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 440#endif 441#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 442#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 443#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 444#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 445#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 446#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 447#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 448#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 449#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 450#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 451#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 452#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 453#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 454#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 455#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 456#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 457#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 458#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 459#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 460#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 461#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 462#define ICTRL_EICP 0x00000100 /* enable icache par. check */ 463#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 464#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 465#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 466#define SPRN_L2CR2 0x3f8 467#define L2CR_L2E 0x80000000 /* L2 enable */ 468#define L2CR_L2PE 0x40000000 /* L2 parity enable */ 469#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ 470#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ 471#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ 472#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ 473#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ 474#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ 475#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ 476#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ 477#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ 478#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ 479#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ 480#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ 481#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ 482#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ 483#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ 484#define L2CR_L2DO 0x00400000 /* L2 data only */ 485#define L2CR_L2I 0x00200000 /* L2 global invalidate */ 486#define L2CR_L2CTL 0x00100000 /* L2 RAM control */ 487#define L2CR_L2WT 0x00080000 /* L2 write-through */ 488#define L2CR_L2TS 0x00040000 /* L2 test support */ 489#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ 490#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ 491#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ 492#define L2CR_L2SL 0x00008000 /* L2 DLL slow */ 493#define L2CR_L2DF 0x00004000 /* L2 differential clock */ 494#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ 495#define L2CR_L2IP 0x00000001 /* L2 GI in progress */ 496#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ 497#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ 498#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ 499#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ 500#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ 501#define L3CR_L3E 0x80000000 /* L3 enable */ 502#define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 503#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 504#define L3CR_L3SIZ 0x10000000 /* L3 size */ 505#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 506#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 507#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 508#define L3CR_L3IO 0x00400000 /* L3 instruction only */ 509#define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 510#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 511#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 512#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 513#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 514#define L3CR_L3I 0x00000400 /* L3 global invalidate */ 515#define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 516#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 517#define L3CR_L3DO 0x00000040 /* L3 data only mode */ 518#define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 519#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ 520 521#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ 522#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ 523#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ 524#define SPRN_LDSTDB 0x3f4 /* */ 525#define SPRN_LR 0x008 /* Link Register */ 526#ifndef SPRN_PIR 527#define SPRN_PIR 0x3FF /* Processor Identification Register */ 528#endif 529#define SPRN_TIR 0x1BE /* Thread Identification Register */ 530#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 531#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 532#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 533#define SPRN_PVR 0x11F /* Processor Version Register */ 534#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 535#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 536#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 537#define SPRN_ASR 0x118 /* Address Space Register */ 538#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 539#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 540#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 541#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 542#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 543#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ 544#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 545#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 546#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 547#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 548#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 549#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 550#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ 551#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ 552#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ 553#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 554#define SRR1_WAKESYSERR 0x00300000 /* System error */ 555#define SRR1_WAKEEE 0x00200000 /* External interrupt */ 556#define SRR1_WAKEMT 0x00280000 /* mtctrl */ 557#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ 558#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 559#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 560#define SRR1_WAKERESET 0x00100000 /* System reset */ 561#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */ 562#define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained, 563 * may not be recoverable */ 564#define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */ 565#define SRR1_WS_DEEP 0x00010000 /* All resources maintained */ 566#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ 567#define SRR1_PROGILL 0x00080000 /* Illegal instruction */ 568#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ 569#define SRR1_PROGTRAP 0x00020000 /* Trap */ 570#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ 571 572#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 573#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 574#define HSRR1_DENORM 0x00100000 /* Denorm exception */ 575 576#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ 577#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ 578#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ 579#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ 580#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ 581 582#ifndef SPRN_SVR 583#define SPRN_SVR 0x11E /* System Version Register */ 584#endif 585#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 586/* these bits were defined in inverted endian sense originally, ugh, confusing */ 587#define THRM1_TIN (1 << 31) 588#define THRM1_TIV (1 << 30) 589#define THRM1_THRES(x) ((x&0x7f)<<23) 590#define THRM3_SITV(x) ((x&0x3fff)<<1) 591#define THRM1_TID (1<<2) 592#define THRM1_TIE (1<<1) 593#define THRM1_V (1<<0) 594#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 595#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 596#define THRM3_E (1<<0) 597#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 598#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 599#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 600#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 601#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 602#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 603#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 604#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 605#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ 606#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 607 608#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ 609#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ 610#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ 611#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ 612#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ 613#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ 614#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ 615 616#define SPRN_SCOMC 0x114 /* SCOM Access Control */ 617#define SPRN_SCOMD 0x115 /* SCOM Access DATA */ 618 619/* Performance monitor SPRs */ 620#ifdef CONFIG_PPC64 621#define SPRN_MMCR0 795 622#define MMCR0_FC 0x80000000UL /* freeze counters */ 623#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 624#define MMCR0_KERNEL_DISABLE MMCR0_FCS 625#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 626#define MMCR0_PROBLEM_DISABLE MMCR0_FCP 627#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 628#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 629#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 630#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 631#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 632#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 633#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 634#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 635#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 636#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 637#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 638#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 639#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 640#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 641#define SPRN_MMCR1 798 642#define SPRN_MMCR2 769 643#define SPRN_MMCRA 0x312 644#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ 645#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL 646#define MMCRA_SDAR_ERAT_MISS 0x20000000UL 647#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 648#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 649#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 650#define MMCRA_SLOT_SHIFT 24 651#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 652#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ 653#define POWER6_MMCRA_SIHV 0x0000040000000000ULL 654#define POWER6_MMCRA_SIPR 0x0000020000000000ULL 655#define POWER6_MMCRA_THRM 0x00000020UL 656#define POWER6_MMCRA_OTHER 0x0000000EUL 657 658#define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */ 659#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */ 660 661#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ 662#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ 663#define SPRN_MMCRC 851 /* Core monitor mode control register */ 664 665#define SPRN_PMC1 787 666#define SPRN_PMC2 788 667#define SPRN_PMC3 789 668#define SPRN_PMC4 790 669#define SPRN_PMC5 791 670#define SPRN_PMC6 792 671#define SPRN_PMC7 793 672#define SPRN_PMC8 794 673#define SPRN_SIAR 780 674#define SPRN_SDAR 781 675#define SPRN_SIER 784 676#define SIER_SIPR 0x2000000 /* Sampled MSR_PR */ 677#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ 678#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ 679#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ 680 681#define SPRN_PA6T_MMCR0 795 682#define PA6T_MMCR0_EN0 0x0000000000000001UL 683#define PA6T_MMCR0_EN1 0x0000000000000002UL 684#define PA6T_MMCR0_EN2 0x0000000000000004UL 685#define PA6T_MMCR0_EN3 0x0000000000000008UL 686#define PA6T_MMCR0_EN4 0x0000000000000010UL 687#define PA6T_MMCR0_EN5 0x0000000000000020UL 688#define PA6T_MMCR0_SUPEN 0x0000000000000040UL 689#define PA6T_MMCR0_PREN 0x0000000000000080UL 690#define PA6T_MMCR0_HYPEN 0x0000000000000100UL 691#define PA6T_MMCR0_FCM0 0x0000000000000200UL 692#define PA6T_MMCR0_FCM1 0x0000000000000400UL 693#define PA6T_MMCR0_INTGEN 0x0000000000000800UL 694#define PA6T_MMCR0_INTEN0 0x0000000000001000UL 695#define PA6T_MMCR0_INTEN1 0x0000000000002000UL 696#define PA6T_MMCR0_INTEN2 0x0000000000004000UL 697#define PA6T_MMCR0_INTEN3 0x0000000000008000UL 698#define PA6T_MMCR0_INTEN4 0x0000000000010000UL 699#define PA6T_MMCR0_INTEN5 0x0000000000020000UL 700#define PA6T_MMCR0_DISCNT 0x0000000000040000UL 701#define PA6T_MMCR0_UOP 0x0000000000080000UL 702#define PA6T_MMCR0_TRG 0x0000000000100000UL 703#define PA6T_MMCR0_TRGEN 0x0000000000200000UL 704#define PA6T_MMCR0_TRGREG 0x0000000001600000UL 705#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL 706#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL 707#define PA6T_MMCR0_PROEN 0x0000000008000000UL 708#define PA6T_MMCR0_PROLOG 0x0000000010000000UL 709#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL 710#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL 711#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL 712#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL 713#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL 714#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL 715#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL 716#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL 717#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL 718#define PA6T_MMCR0_PCTEN 0x0000004000000000UL 719#define PA6T_MMCR0_SOCEN 0x0000008000000000UL 720#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL 721 722#define SPRN_PA6T_MMCR1 798 723#define PA6T_MMCR1_ES2 0x00000000000000ffUL 724#define PA6T_MMCR1_ES3 0x000000000000ff00UL 725#define PA6T_MMCR1_ES4 0x0000000000ff0000UL 726#define PA6T_MMCR1_ES5 0x00000000ff000000UL 727 728#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ 729#define SPRN_PA6T_UPMC1 772 /* ... */ 730#define SPRN_PA6T_UPMC2 773 731#define SPRN_PA6T_UPMC3 774 732#define SPRN_PA6T_UPMC4 775 733#define SPRN_PA6T_UPMC5 776 734#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ 735#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ 736#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ 737#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ 738#define SPRN_PA6T_PMC0 787 739#define SPRN_PA6T_PMC1 788 740#define SPRN_PA6T_PMC2 789 741#define SPRN_PA6T_PMC3 790 742#define SPRN_PA6T_PMC4 791 743#define SPRN_PA6T_PMC5 792 744#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ 745#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ 746#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ 747#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ 748 749#define SPRN_PA6T_IER 981 /* Icache Error Register */ 750#define SPRN_PA6T_DER 982 /* Dcache Error Register */ 751#define SPRN_PA6T_BER 862 /* BIU Error Address Register */ 752#define SPRN_PA6T_MER 849 /* MMU Error Register */ 753 754#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ 755#define SPRN_PA6T_IMA1 881 /* ... */ 756#define SPRN_PA6T_IMA2 882 757#define SPRN_PA6T_IMA3 883 758#define SPRN_PA6T_IMA4 884 759#define SPRN_PA6T_IMA5 885 760#define SPRN_PA6T_IMA6 886 761#define SPRN_PA6T_IMA7 887 762#define SPRN_PA6T_IMA8 888 763#define SPRN_PA6T_IMA9 889 764#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 765#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 766#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 767#define SPRN_BKMK 1020 /* Cell Bookmark Register */ 768#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 769 770 771#else /* 32-bit */ 772#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 773#define MMCR0_FC 0x80000000UL /* freeze counters */ 774#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 775#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 776#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 777#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 778#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 779#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 780#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 781#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 782#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ 783#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 784#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ 785#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ 786 787#define SPRN_MMCR1 956 788#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ 789#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ 790#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ 791#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ 792#define SPRN_MMCR2 944 793#define SPRN_PMC1 953 /* Performance Counter Register 1 */ 794#define SPRN_PMC2 954 /* Performance Counter Register 2 */ 795#define SPRN_PMC3 957 /* Performance Counter Register 3 */ 796#define SPRN_PMC4 958 /* Performance Counter Register 4 */ 797#define SPRN_PMC5 945 /* Performance Counter Register 5 */ 798#define SPRN_PMC6 946 /* Performance Counter Register 6 */ 799 800#define SPRN_SIAR 955 /* Sampled Instruction Address Register */ 801 802/* Bit definitions for MMCR0 and PMC1 / PMC2. */ 803#define MMCR0_PMC1_CYCLES (1 << 7) 804#define MMCR0_PMC1_ICACHEMISS (5 << 7) 805#define MMCR0_PMC1_DTLB (6 << 7) 806#define MMCR0_PMC2_DCACHEMISS 0x6 807#define MMCR0_PMC2_CYCLES 0x1 808#define MMCR0_PMC2_ITLB 0x7 809#define MMCR0_PMC2_LOADMISSTIME 0x5 810#endif 811 812/* 813 * SPRG usage: 814 * 815 * All 64-bit: 816 * - SPRG1 stores PACA pointer except 64-bit server in 817 * HV mode in which case it is HSPRG0 818 * 819 * 64-bit server: 820 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4) 821 * - SPRG2 scratch for exception vectors 822 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) 823 * - HSPRG0 stores PACA in HV mode 824 * - HSPRG1 scratch for "HV" exceptions 825 * 826 * 64-bit embedded 827 * - SPRG0 generic exception scratch 828 * - SPRG2 TLB exception stack 829 * - SPRG3 critical exception scratch and 830 * CPU and NUMA node for VDSO getcpu (user visible) 831 * - SPRG4 unused (user visible) 832 * - SPRG6 TLB miss scratch (user visible, sorry !) 833 * - SPRG7 critical exception scratch 834 * - SPRG8 machine check exception scratch 835 * - SPRG9 debug exception scratch 836 * 837 * All 32-bit: 838 * - SPRG3 current thread_info pointer 839 * (virtual on BookE, physical on others) 840 * 841 * 32-bit classic: 842 * - SPRG0 scratch for exception vectors 843 * - SPRG1 scratch for exception vectors 844 * - SPRG2 indicator that we are in RTAS 845 * - SPRG4 (603 only) pseudo TLB LRU data 846 * 847 * 32-bit 40x: 848 * - SPRG0 scratch for exception vectors 849 * - SPRG1 scratch for exception vectors 850 * - SPRG2 scratch for exception vectors 851 * - SPRG4 scratch for exception vectors (not 403) 852 * - SPRG5 scratch for exception vectors (not 403) 853 * - SPRG6 scratch for exception vectors (not 403) 854 * - SPRG7 scratch for exception vectors (not 403) 855 * 856 * 32-bit 440 and FSL BookE: 857 * - SPRG0 scratch for exception vectors 858 * - SPRG1 scratch for exception vectors (*) 859 * - SPRG2 scratch for crit interrupts handler 860 * - SPRG4 scratch for exception vectors 861 * - SPRG5 scratch for exception vectors 862 * - SPRG6 scratch for machine check handler 863 * - SPRG7 scratch for exception vectors 864 * - SPRG9 scratch for debug vectors (e500 only) 865 * 866 * Additionally, BookE separates "read" and "write" 867 * of those registers. That allows to use the userspace 868 * readable variant for reads, which can avoid a fault 869 * with KVM type virtualization. 870 * 871 * (*) Under KVM, the host SPRG1 is used to point to 872 * the current VCPU data structure 873 * 874 * 32-bit 8xx: 875 * - SPRG0 scratch for exception vectors 876 * - SPRG1 scratch for exception vectors 877 * - SPRG2 apparently unused but initialized 878 * 879 */ 880#ifdef CONFIG_PPC64 881#define SPRN_SPRG_PACA SPRN_SPRG1 882#else 883#define SPRN_SPRG_THREAD SPRN_SPRG3 884#endif 885 886#ifdef CONFIG_PPC_BOOK3S_64 887#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 888#define SPRN_SPRG_HPACA SPRN_HSPRG0 889#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 890 891#define GET_PACA(rX) \ 892 BEGIN_FTR_SECTION_NESTED(66); \ 893 mfspr rX,SPRN_SPRG_PACA; \ 894 FTR_SECTION_ELSE_NESTED(66); \ 895 mfspr rX,SPRN_SPRG_HPACA; \ 896 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 897 898#define SET_PACA(rX) \ 899 BEGIN_FTR_SECTION_NESTED(66); \ 900 mtspr SPRN_SPRG_PACA,rX; \ 901 FTR_SECTION_ELSE_NESTED(66); \ 902 mtspr SPRN_SPRG_HPACA,rX; \ 903 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 904 905#define GET_SCRATCH0(rX) \ 906 BEGIN_FTR_SECTION_NESTED(66); \ 907 mfspr rX,SPRN_SPRG_SCRATCH0; \ 908 FTR_SECTION_ELSE_NESTED(66); \ 909 mfspr rX,SPRN_SPRG_HSCRATCH0; \ 910 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 911 912#define SET_SCRATCH0(rX) \ 913 BEGIN_FTR_SECTION_NESTED(66); \ 914 mtspr SPRN_SPRG_SCRATCH0,rX; \ 915 FTR_SECTION_ELSE_NESTED(66); \ 916 mtspr SPRN_SPRG_HSCRATCH0,rX; \ 917 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 918 919#else /* CONFIG_PPC_BOOK3S_64 */ 920#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0 921#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX 922 923#endif 924 925#ifdef CONFIG_PPC_BOOK3E_64 926#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 927#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3 928#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 929#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 930#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 931#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 932#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH 933 934#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX 935#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA 936 937#endif 938 939#ifdef CONFIG_PPC_BOOK3S_32 940#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 941#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 942#define SPRN_SPRG_RTAS SPRN_SPRG2 943#define SPRN_SPRG_603_LRU SPRN_SPRG4 944#endif 945 946#ifdef CONFIG_40x 947#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 948#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 949#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 950#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4 951#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5 952#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6 953#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7 954#endif 955 956#ifdef CONFIG_BOOKE 957#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0 958#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0 959#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1 960#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1 961#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2 962#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2 963#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R 964#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W 965#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R 966#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W 967#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1 968#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1 969#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R 970#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W 971#ifdef CONFIG_E200 972#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R 973#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W 974#else 975#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9 976#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9 977#endif 978#endif 979 980#ifdef CONFIG_8xx 981#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 982#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 983#endif 984 985 986 987/* 988 * An mtfsf instruction with the L bit set. On CPUs that support this a 989 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 990 * 991 * Until binutils gets the new form of mtfsf, hardwire the instruction. 992 */ 993#ifdef CONFIG_PPC64 994#define MTFSF_L(REG) \ 995 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) 996#else 997#define MTFSF_L(REG) mtfsf 0xff, (REG) 998#endif 999 1000/* Processor Version Register (PVR) field extraction */ 1001 1002#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 1003#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 1004 1005#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr)) 1006 1007/* 1008 * IBM has further subdivided the standard PowerPC 16-bit version and 1009 * revision subfields of the PVR for the PowerPC 403s into the following: 1010 */ 1011 1012#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 1013#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 1014#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 1015#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 1016#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 1017#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 1018 1019/* Processor Version Numbers */ 1020 1021#define PVR_403GA 0x00200000 1022#define PVR_403GB 0x00200100 1023#define PVR_403GC 0x00200200 1024#define PVR_403GCX 0x00201400 1025#define PVR_405GP 0x40110000 1026#define PVR_476 0x11a52000 1027#define PVR_476FPE 0x7ff50000 1028#define PVR_STB03XXX 0x40310000 1029#define PVR_NP405H 0x41410000 1030#define PVR_NP405L 0x41610000 1031#define PVR_601 0x00010000 1032#define PVR_602 0x00050000 1033#define PVR_603 0x00030000 1034#define PVR_603e 0x00060000 1035#define PVR_603ev 0x00070000 1036#define PVR_603r 0x00071000 1037#define PVR_604 0x00040000 1038#define PVR_604e 0x00090000 1039#define PVR_604r 0x000A0000 1040#define PVR_620 0x00140000 1041#define PVR_740 0x00080000 1042#define PVR_750 PVR_740 1043#define PVR_740P 0x10080000 1044#define PVR_750P PVR_740P 1045#define PVR_7400 0x000C0000 1046#define PVR_7410 0x800C0000 1047#define PVR_7450 0x80000000 1048#define PVR_8540 0x80200000 1049#define PVR_8560 0x80200000 1050#define PVR_VER_E500V1 0x8020 1051#define PVR_VER_E500V2 0x8021 1052/* 1053 * For the 8xx processors, all of them report the same PVR family for 1054 * the PowerPC core. The various versions of these processors must be 1055 * differentiated by the version number in the Communication Processor 1056 * Module (CPM). 1057 */ 1058#define PVR_821 0x00500000 1059#define PVR_823 PVR_821 1060#define PVR_850 PVR_821 1061#define PVR_860 PVR_821 1062#define PVR_8240 0x00810100 1063#define PVR_8245 0x80811014 1064#define PVR_8260 PVR_8240 1065 1066/* 476 Simulator seems to currently have the PVR of the 602... */ 1067#define PVR_476_ISS 0x00052000 1068 1069/* 64-bit processors */ 1070#define PVR_NORTHSTAR 0x0033 1071#define PVR_PULSAR 0x0034 1072#define PVR_POWER4 0x0035 1073#define PVR_ICESTAR 0x0036 1074#define PVR_SSTAR 0x0037 1075#define PVR_POWER4p 0x0038 1076#define PVR_970 0x0039 1077#define PVR_POWER5 0x003A 1078#define PVR_POWER5p 0x003B 1079#define PVR_970FX 0x003C 1080#define PVR_POWER6 0x003E 1081#define PVR_POWER7 0x003F 1082#define PVR_630 0x0040 1083#define PVR_630p 0x0041 1084#define PVR_970MP 0x0044 1085#define PVR_970GX 0x0045 1086#define PVR_POWER7p 0x004A 1087#define PVR_POWER8 0x004B 1088#define PVR_BE 0x0070 1089#define PVR_PA6T 0x0090 1090 1091/* Macros for setting and retrieving special purpose registers */ 1092#ifndef __ASSEMBLY__ 1093#define mfmsr() ({unsigned long rval; \ 1094 asm volatile("mfmsr %0" : "=r" (rval) : \ 1095 : "memory"); rval;}) 1096#ifdef CONFIG_PPC_BOOK3S_64 1097#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 1098 : : "r" (v) : "memory") 1099#define mtmsrd(v) __mtmsrd((v), 0) 1100#define mtmsr(v) mtmsrd(v) 1101#else 1102#define mtmsr(v) asm volatile("mtmsr %0" : \ 1103 : "r" ((unsigned long)(v)) \ 1104 : "memory") 1105#endif 1106 1107#define mfspr(rn) ({unsigned long rval; \ 1108 asm volatile("mfspr %0," __stringify(rn) \ 1109 : "=r" (rval)); rval;}) 1110#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ 1111 : "r" ((unsigned long)(v)) \ 1112 : "memory") 1113 1114#ifdef __powerpc64__ 1115#ifdef CONFIG_PPC_CELL 1116#define mftb() ({unsigned long rval; \ 1117 asm volatile( \ 1118 "90: mftb %0;\n" \ 1119 "97: cmpwi %0,0;\n" \ 1120 " beq- 90b;\n" \ 1121 "99:\n" \ 1122 ".section __ftr_fixup,\"a\"\n" \ 1123 ".align 3\n" \ 1124 "98:\n" \ 1125 " .llong %1\n" \ 1126 " .llong %1\n" \ 1127 " .llong 97b-98b\n" \ 1128 " .llong 99b-98b\n" \ 1129 " .llong 0\n" \ 1130 " .llong 0\n" \ 1131 ".previous" \ 1132 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;}) 1133#else 1134#define mftb() ({unsigned long rval; \ 1135 asm volatile("mftb %0" : "=r" (rval)); rval;}) 1136#endif /* !CONFIG_PPC_CELL */ 1137 1138#else /* __powerpc64__ */ 1139 1140#define mftbl() ({unsigned long rval; \ 1141 asm volatile("mftbl %0" : "=r" (rval)); rval;}) 1142#define mftbu() ({unsigned long rval; \ 1143 asm volatile("mftbu %0" : "=r" (rval)); rval;}) 1144#endif /* !__powerpc64__ */ 1145 1146#define mttbl(v) asm volatile("mttbl %0":: "r"(v)) 1147#define mttbu(v) asm volatile("mttbu %0":: "r"(v)) 1148 1149#ifdef CONFIG_PPC32 1150#define mfsrin(v) ({unsigned int rval; \ 1151 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ 1152 rval;}) 1153#endif 1154 1155#define proc_trap() asm volatile("trap") 1156 1157#define __get_SP() ({unsigned long sp; \ 1158 asm volatile("mr %0,1": "=r" (sp)); sp;}) 1159 1160extern unsigned long scom970_read(unsigned int address); 1161extern void scom970_write(unsigned int address, unsigned long value); 1162 1163struct pt_regs; 1164 1165extern void ppc_save_regs(struct pt_regs *regs); 1166 1167#endif /* __ASSEMBLY__ */ 1168#endif /* __KERNEL__ */ 1169#endif /* _ASM_POWERPC_REG_H */ 1170