reg.h revision 8f42ab2749d00ea15157ab896cfbed73a247b3e1
1/* 2 * Contains the definition of registers common to all PowerPC variants. 3 * If a register definition has been changed in a different PowerPC 4 * variant, we will case it in #ifndef XXX ... #endif, and have the 5 * number used in the Programming Environments Manual For 32-Bit 6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 7 */ 8 9#ifndef _ASM_POWERPC_REG_H 10#define _ASM_POWERPC_REG_H 11#ifdef __KERNEL__ 12 13#include <linux/stringify.h> 14#include <asm/cputable.h> 15 16/* Pickup Book E specific registers. */ 17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 18#include <asm/reg_booke.h> 19#endif /* CONFIG_BOOKE || CONFIG_40x */ 20 21#ifdef CONFIG_FSL_EMB_PERFMON 22#include <asm/reg_fsl_emb.h> 23#endif 24 25#ifdef CONFIG_8xx 26#include <asm/reg_8xx.h> 27#endif /* CONFIG_8xx */ 28 29#define MSR_SF_LG 63 /* Enable 64 bit mode */ 30#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 31#define MSR_HV_LG 60 /* Hypervisor state */ 32#define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */ 33#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ 34#define MSR_TS_LG 33 /* Trans Mem state (2 bits) */ 35#define MSR_TM_LG 32 /* Trans Mem Available */ 36#define MSR_VEC_LG 25 /* Enable AltiVec */ 37#define MSR_VSX_LG 23 /* Enable VSX */ 38#define MSR_POW_LG 18 /* Enable Power Management */ 39#define MSR_WE_LG 18 /* Wait State Enable */ 40#define MSR_TGPR_LG 17 /* TLB Update registers in use */ 41#define MSR_CE_LG 17 /* Critical Interrupt Enable */ 42#define MSR_ILE_LG 16 /* Interrupt Little Endian */ 43#define MSR_EE_LG 15 /* External Interrupt Enable */ 44#define MSR_PR_LG 14 /* Problem State / Privilege Level */ 45#define MSR_FP_LG 13 /* Floating Point enable */ 46#define MSR_ME_LG 12 /* Machine Check Enable */ 47#define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 48#define MSR_SE_LG 10 /* Single Step */ 49#define MSR_BE_LG 9 /* Branch Trace */ 50#define MSR_DE_LG 9 /* Debug Exception Enable */ 51#define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 52#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 53#define MSR_IR_LG 5 /* Instruction Relocate */ 54#define MSR_DR_LG 4 /* Data Relocate */ 55#define MSR_PE_LG 3 /* Protection Enable */ 56#define MSR_PX_LG 2 /* Protection Exclusive Mode */ 57#define MSR_PMM_LG 2 /* Performance monitor */ 58#define MSR_RI_LG 1 /* Recoverable Exception */ 59#define MSR_LE_LG 0 /* Little Endian */ 60 61#ifdef __ASSEMBLY__ 62#define __MASK(X) (1<<(X)) 63#else 64#define __MASK(X) (1UL<<(X)) 65#endif 66 67#ifdef CONFIG_PPC64 68#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 69#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 70#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 71#else 72/* so tests for these bits fail on 32-bit */ 73#define MSR_SF 0 74#define MSR_ISF 0 75#define MSR_HV 0 76#endif 77 78#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 79#define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ 80#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 81#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 82#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 83#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 84#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 85#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 86#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 87#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 88#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 89#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 90#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 91#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 92#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 93#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 94#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 95#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 96#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 97#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 98#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 99#ifndef MSR_PMM 100#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ 101#endif 102#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 103#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 104 105#define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ 106#define MSR_TS_N 0 /* Non-transactional */ 107#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ 108#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */ 109#define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */ 110#define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */ 111#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) 112#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) 113 114#if defined(CONFIG_PPC_BOOK3S_64) 115#define MSR_64BIT MSR_SF 116 117/* Server variant */ 118#define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV) 119#ifdef __BIG_ENDIAN__ 120#define MSR_ __MSR 121#else 122#define MSR_ (__MSR | MSR_LE) 123#endif 124#define MSR_KERNEL (MSR_ | MSR_64BIT) 125#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE) 126#define MSR_USER64 (MSR_USER32 | MSR_64BIT) 127#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx) 128/* Default MSR for kernel mode. */ 129#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 130#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 131#endif 132 133#ifndef MSR_64BIT 134#define MSR_64BIT 0 135#endif 136 137/* Floating Point Status and Control Register (FPSCR) Fields */ 138#define FPSCR_FX 0x80000000 /* FPU exception summary */ 139#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 140#define FPSCR_VX 0x20000000 /* Invalid operation summary */ 141#define FPSCR_OX 0x10000000 /* Overflow exception summary */ 142#define FPSCR_UX 0x08000000 /* Underflow exception summary */ 143#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 144#define FPSCR_XX 0x02000000 /* Inexact exception summary */ 145#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 146#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 147#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 148#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 149#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 150#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 151#define FPSCR_FR 0x00040000 /* Fraction rounded */ 152#define FPSCR_FI 0x00020000 /* Fraction inexact */ 153#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 154#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 155#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 156#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 157#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 158#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 159#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 160#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 161#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 162#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 163#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 164#define FPSCR_RN 0x00000003 /* FPU rounding control */ 165 166/* Bit definitions for SPEFSCR. */ 167#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ 168#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ 169#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ 170#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ 171#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ 172#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ 173#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ 174#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ 175#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ 176#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ 177#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ 178#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ 179#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ 180#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ 181#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ 182#define SPEFSCR_OV 0x00004000 /* Integer overflow */ 183#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ 184#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ 185#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ 186#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ 187#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ 188#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ 189#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ 190#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ 191#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ 192#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ 193#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ 194#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ 195 196/* Special Purpose Registers (SPRNs)*/ 197 198#ifdef CONFIG_40x 199#define SPRN_PID 0x3B1 /* Process ID */ 200#else 201#define SPRN_PID 0x030 /* Process ID */ 202#ifdef CONFIG_BOOKE 203#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ 204#endif 205#endif 206 207#define SPRN_CTR 0x009 /* Count Register */ 208#define SPRN_DSCR 0x11 209#define SPRN_CFAR 0x1c /* Come From Address Register */ 210#define SPRN_AMR 0x1d /* Authority Mask Register */ 211#define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */ 212#define SPRN_AMOR 0x15d /* Authority Mask Override Register */ 213#define SPRN_ACOP 0x1F /* Available Coprocessor Register */ 214#define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ 215#define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ 216#define TEXASR_FS __MASK(63-36) /* Transaction Failure Summary */ 217#define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ 218#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ 219#define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ 220#define SPRN_CTRLF 0x088 221#define SPRN_CTRLT 0x098 222#define CTRL_CT 0xc0000000 /* current thread */ 223#define CTRL_CT0 0x80000000 /* thread 0 */ 224#define CTRL_CT1 0x40000000 /* thread 1 */ 225#define CTRL_TE 0x00c00000 /* thread enable */ 226#define CTRL_RUNLATCH 0x1 227#define SPRN_DAWR 0xB4 228#define SPRN_RPR 0xBA /* Relative Priority Register */ 229#define SPRN_CIABR 0xBB 230#define CIABR_PRIV 0x3 231#define CIABR_PRIV_USER 1 232#define CIABR_PRIV_SUPER 2 233#define CIABR_PRIV_HYPER 3 234#define SPRN_DAWRX 0xBC 235#define DAWRX_USER __MASK(0) 236#define DAWRX_KERNEL __MASK(1) 237#define DAWRX_HYP __MASK(2) 238#define DAWRX_WTI __MASK(3) 239#define DAWRX_WT __MASK(4) 240#define DAWRX_DR __MASK(5) 241#define DAWRX_DW __MASK(6) 242#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 243#define SPRN_DABR2 0x13D /* e300 */ 244#define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 245#define DABRX_USER __MASK(0) 246#define DABRX_KERNEL __MASK(1) 247#define DABRX_HYP __MASK(2) 248#define DABRX_BTI __MASK(3) 249#define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) 250#define SPRN_DAR 0x013 /* Data Address Register */ 251#define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 252#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 253#define DSISR_NOHPTE 0x40000000 /* no translation found */ 254#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 255#define DSISR_ISSTORE 0x02000000 /* access was a store */ 256#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 257#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 258#define DSISR_KEYFAULT 0x00200000 /* Key fault */ 259#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ 260#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ 261#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 262#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 263#define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */ 264#define SPRN_SPURR 0x134 /* Scaled PURR */ 265#define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */ 266#define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */ 267#define SPRN_HDSISR 0x132 268#define SPRN_HDAR 0x133 269#define SPRN_HDEC 0x136 /* Hypervisor Decrementer */ 270#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 271#define SPRN_RMOR 0x138 /* Real mode offset register */ 272#define SPRN_HRMOR 0x139 /* Real mode offset register */ 273#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ 274#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ 275#define SPRN_IC 0x350 /* Virtual Instruction Count */ 276#define SPRN_VTB 0x351 /* Virtual Time Base */ 277#define SPRN_LDBAR 0x352 /* LD Base Address Register */ 278#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */ 279#define SPRN_PMSR 0x355 /* Power Management Status Reg */ 280#define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */ 281#define SPRN_PMCR 0x374 /* Power Management Control Register */ 282 283/* HFSCR and FSCR bit numbers are the same */ 284#define FSCR_TAR_LG 8 /* Enable Target Address Register */ 285#define FSCR_EBB_LG 7 /* Enable Event Based Branching */ 286#define FSCR_TM_LG 5 /* Enable Transactional Memory */ 287#define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/ 288#define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */ 289#define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */ 290#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ 291#define FSCR_FP_LG 0 /* Enable Floating Point */ 292#define SPRN_FSCR 0x099 /* Facility Status & Control Register */ 293#define FSCR_TAR __MASK(FSCR_TAR_LG) 294#define FSCR_EBB __MASK(FSCR_EBB_LG) 295#define FSCR_DSCR __MASK(FSCR_DSCR_LG) 296#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ 297#define HFSCR_TAR __MASK(FSCR_TAR_LG) 298#define HFSCR_EBB __MASK(FSCR_EBB_LG) 299#define HFSCR_TM __MASK(FSCR_TM_LG) 300#define HFSCR_PM __MASK(FSCR_PM_LG) 301#define HFSCR_BHRB __MASK(FSCR_BHRB_LG) 302#define HFSCR_DSCR __MASK(FSCR_DSCR_LG) 303#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG) 304#define HFSCR_FP __MASK(FSCR_FP_LG) 305#define SPRN_TAR 0x32f /* Target Address Register */ 306#define SPRN_LPCR 0x13E /* LPAR Control Register */ 307#define LPCR_VPM0 (1ul << (63-0)) 308#define LPCR_VPM1 (1ul << (63-1)) 309#define LPCR_ISL (1ul << (63-2)) 310#define LPCR_VC_SH (63-2) 311#define LPCR_DPFD_SH (63-11) 312#define LPCR_DPFD (7ul << LPCR_DPFD_SH) 313#define LPCR_VRMASD (0x1ful << (63-16)) 314#define LPCR_VRMA_L (1ul << (63-12)) 315#define LPCR_VRMA_LP0 (1ul << (63-15)) 316#define LPCR_VRMA_LP1 (1ul << (63-16)) 317#define LPCR_VRMASD_SH (63-16) 318#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ 319#define LPCR_RMLS_SH (63-37) 320#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ 321#define LPCR_AIL 0x01800000 /* Alternate interrupt location */ 322#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ 323#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ 324#define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */ 325#define LPCR_PECE 0x0001f000 /* powersave exit cause enable */ 326#define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */ 327#define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */ 328#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ 329#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ 330#define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */ 331#define LPCR_MER 0x00000800 /* Mediated External Exception */ 332#define LPCR_MER_SH 11 333#define LPCR_TC 0x00000200 /* Translation control */ 334#define LPCR_LPES 0x0000000c 335#define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */ 336#define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */ 337#define LPCR_LPES_SH 2 338#define LPCR_RMI 0x00000002 /* real mode is cache inhibit */ 339#define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */ 340#ifndef SPRN_LPID 341#define SPRN_LPID 0x13F /* Logical Partition Identifier */ 342#endif 343#define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */ 344#define SPRN_HMER 0x150 /* Hardware m? error recovery */ 345#define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */ 346#define SPRN_PCR 0x152 /* Processor compatibility register */ 347#define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ 348#define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ 349#define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ 350#define PCR_ARCH_206 0x4 /* Architecture 2.06 */ 351#define PCR_ARCH_205 0x2 /* Architecture 2.05 */ 352#define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ 353#define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ 354#define SPRN_TLBVPNR 0x155 /* P7 TLB control register */ 355#define SPRN_TLBRPNR 0x156 /* P7 TLB control register */ 356#define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */ 357#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 358#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 359#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 360#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 361#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 362#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 363#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 364#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 365#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 366#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 367#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 368#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 369#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 370#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 371#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 372#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 373#define SPRN_PPR 0x380 /* SMT Thread status Register */ 374 375#define SPRN_DEC 0x016 /* Decrement Register */ 376#define SPRN_DER 0x095 /* Debug Enable Regsiter */ 377#define DER_RSTE 0x40000000 /* Reset Interrupt */ 378#define DER_CHSTPE 0x20000000 /* Check Stop */ 379#define DER_MCIE 0x10000000 /* Machine Check Interrupt */ 380#define DER_EXTIE 0x02000000 /* External Interrupt */ 381#define DER_ALIE 0x01000000 /* Alignment Interrupt */ 382#define DER_PRIE 0x00800000 /* Program Interrupt */ 383#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ 384#define DER_DECIE 0x00200000 /* Decrementer Interrupt */ 385#define DER_SYSIE 0x00040000 /* System Call Interrupt */ 386#define DER_TRE 0x00020000 /* Trace Interrupt */ 387#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ 388#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ 389#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ 390#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ 391#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ 392#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ 393#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ 394#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 395#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 396#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 397#define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */ 398#define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */ 399#define SPRN_EAR 0x11A /* External Address Register */ 400#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 401#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 402#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 403#define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */ 404#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 405#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 406#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 407#define HID0_SBCLK (1<<27) 408#define HID0_EICE (1<<26) 409#define HID0_TBEN (1<<26) /* Timebase enable - 745x */ 410#define HID0_ECLK (1<<25) 411#define HID0_PAR (1<<24) 412#define HID0_STEN (1<<24) /* Software table search enable - 745x */ 413#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ 414#define HID0_DOZE (1<<23) 415#define HID0_NAP (1<<22) 416#define HID0_SLEEP (1<<21) 417#define HID0_DPM (1<<20) 418#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ 419#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ 420#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ 421#define HID0_ICE (1<<15) /* Instruction Cache Enable */ 422#define HID0_DCE (1<<14) /* Data Cache Enable */ 423#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 424#define HID0_DLOCK (1<<12) /* Data Cache Lock */ 425#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 426#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 427#define HID0_SPD (1<<9) /* Speculative disable */ 428#define HID0_DAPUEN (1<<8) /* Debug APU enable */ 429#define HID0_SGE (1<<7) /* Store Gathering Enable */ 430#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 431#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 432#define HID0_LRSTK (1<<4) /* Link register stack - 745x */ 433#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ 434#define HID0_ABE (1<<3) /* Address Broadcast Enable */ 435#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ 436#define HID0_BHTE (1<<2) /* Branch History Table Enable */ 437#define HID0_BTCD (1<<1) /* Branch target cache disable */ 438#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ 439#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ 440/* POWER8 HID0 bits */ 441#define HID0_POWER8_4LPARMODE __MASK(61) 442#define HID0_POWER8_2LPARMODE __MASK(57) 443#define HID0_POWER8_1TO2LPAR __MASK(52) 444#define HID0_POWER8_1TO4LPAR __MASK(51) 445#define HID0_POWER8_DYNLPARDIS __MASK(48) 446 447#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 448#ifdef CONFIG_6xx 449#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 450#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 451#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 452#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 453#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 454#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 455#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 456#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ 457#define HID1_PS (1<<16) /* 750FX PLL selection */ 458#endif 459#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ 460#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ 461#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 462#define SPRN_IABR2 0x3FA /* 83xx */ 463#define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 464#define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */ 465#define SPRN_HID4 0x3F4 /* 970 HID4 */ 466#define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ 467#define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ 468#define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */ 469#define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */ 470#define HID4_RMOR (0xFFFFul << HID4_RMOR_SH) 471#define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */ 472#define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */ 473#define HID4_LPID1_SH 0 /* partition ID top 2 bits */ 474#define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ 475#define SPRN_HID5 0x3F6 /* 970 HID5 */ 476#define SPRN_HID6 0x3F9 /* BE HID 6 */ 477#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ 478#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ 479#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ 480#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ 481#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ 482#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ 483#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ 484#define SPRN_TSC 0x3FD /* Thread switch control on others */ 485#define SPRN_TST 0x3FC /* Thread switch timeout on others */ 486#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) 487#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 488#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 489#endif 490#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 491#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 492#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 493#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 494#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 495#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 496#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 497#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 498#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 499#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 500#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 501#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 502#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 503#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 504#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 505#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 506#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 507#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 508#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 509#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 510#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 511#define ICTRL_EICP 0x00000100 /* enable icache par. check */ 512#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 513#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 514#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 515#define SPRN_L2CR2 0x3f8 516#define L2CR_L2E 0x80000000 /* L2 enable */ 517#define L2CR_L2PE 0x40000000 /* L2 parity enable */ 518#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ 519#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ 520#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ 521#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ 522#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ 523#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ 524#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ 525#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ 526#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ 527#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ 528#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ 529#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ 530#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ 531#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ 532#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ 533#define L2CR_L2DO 0x00400000 /* L2 data only */ 534#define L2CR_L2I 0x00200000 /* L2 global invalidate */ 535#define L2CR_L2CTL 0x00100000 /* L2 RAM control */ 536#define L2CR_L2WT 0x00080000 /* L2 write-through */ 537#define L2CR_L2TS 0x00040000 /* L2 test support */ 538#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ 539#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ 540#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ 541#define L2CR_L2SL 0x00008000 /* L2 DLL slow */ 542#define L2CR_L2DF 0x00004000 /* L2 differential clock */ 543#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ 544#define L2CR_L2IP 0x00000001 /* L2 GI in progress */ 545#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ 546#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ 547#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ 548#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ 549#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ 550#define L3CR_L3E 0x80000000 /* L3 enable */ 551#define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 552#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 553#define L3CR_L3SIZ 0x10000000 /* L3 size */ 554#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 555#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 556#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 557#define L3CR_L3IO 0x00400000 /* L3 instruction only */ 558#define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 559#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 560#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 561#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 562#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 563#define L3CR_L3I 0x00000400 /* L3 global invalidate */ 564#define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 565#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 566#define L3CR_L3DO 0x00000040 /* L3 data only mode */ 567#define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 568#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ 569 570#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ 571#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ 572#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ 573#define SPRN_LDSTDB 0x3f4 /* */ 574#define SPRN_LR 0x008 /* Link Register */ 575#ifndef SPRN_PIR 576#define SPRN_PIR 0x3FF /* Processor Identification Register */ 577#endif 578#define SPRN_TIR 0x1BE /* Thread Identification Register */ 579#define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ 580#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 581#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 582#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 583#define SPRN_PVR 0x11F /* Processor Version Register */ 584#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 585#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 586#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 587#define SPRN_ASR 0x118 /* Address Space Register */ 588#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 589#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 590#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 591#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 592#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 593#define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ 594#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 595#define SPRN_USPRG4 0x104 /* SPRG4 userspace read */ 596#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 597#define SPRN_USPRG5 0x105 /* SPRG5 userspace read */ 598#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 599#define SPRN_USPRG6 0x106 /* SPRG6 userspace read */ 600#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 601#define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ 602#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 603#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 604#define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ 605#define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ 606#define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ 607#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 608#define SRR1_WAKESYSERR 0x00300000 /* System error */ 609#define SRR1_WAKEEE 0x00200000 /* External interrupt */ 610#define SRR1_WAKEMT 0x00280000 /* mtctrl */ 611#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ 612#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 613#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 614#define SRR1_WAKERESET 0x00100000 /* System reset */ 615#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */ 616#define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained, 617 * may not be recoverable */ 618#define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */ 619#define SRR1_WS_DEEP 0x00010000 /* All resources maintained */ 620#define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ 621#define SRR1_PROGILL 0x00080000 /* Illegal instruction */ 622#define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ 623#define SRR1_PROGTRAP 0x00020000 /* Trap */ 624#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ 625 626#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 627#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 628#define HSRR1_DENORM 0x00100000 /* Denorm exception */ 629 630#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ 631#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ 632#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ 633#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ 634#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ 635 636#ifndef SPRN_SVR 637#define SPRN_SVR 0x11E /* System Version Register */ 638#endif 639#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 640/* these bits were defined in inverted endian sense originally, ugh, confusing */ 641#define THRM1_TIN (1 << 31) 642#define THRM1_TIV (1 << 30) 643#define THRM1_THRES(x) ((x&0x7f)<<23) 644#define THRM3_SITV(x) ((x&0x3fff)<<1) 645#define THRM1_TID (1<<2) 646#define THRM1_TIE (1<<1) 647#define THRM1_V (1<<0) 648#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 649#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 650#define THRM3_E (1<<0) 651#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 652#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 653#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 654#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 655#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 656#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 657#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 658#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 659#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ 660#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 661 662#define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ 663#define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ 664#define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ 665#define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ 666#define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ 667#define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ 668#define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ 669 670#define SPRN_SCOMC 0x114 /* SCOM Access Control */ 671#define SPRN_SCOMD 0x115 /* SCOM Access DATA */ 672 673/* Performance monitor SPRs */ 674#ifdef CONFIG_PPC64 675#define SPRN_MMCR0 795 676#define MMCR0_FC 0x80000000UL /* freeze counters */ 677#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 678#define MMCR0_KERNEL_DISABLE MMCR0_FCS 679#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 680#define MMCR0_PROBLEM_DISABLE MMCR0_FCP 681#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 682#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 683#define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */ 684#define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */ 685#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 686#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */ 687#define MMCR0_EBE 0x00100000UL /* Event based branch enable */ 688#define MMCR0_PMCC 0x000c0000UL /* PMC control */ 689#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ 690#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 691#define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/ 692#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 693#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */ 694#define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */ 695/* performance monitor alert has occurred, set to 0 after handling exception */ 696#define MMCR0_PMAO ASM_CONST(0x00000080) 697#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 698#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */ 699#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 700#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 701#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 702#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 703#define SPRN_MMCR1 798 704#define SPRN_MMCR2 769 705#define SPRN_MMCRA 0x312 706#define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ 707#define MMCRA_SDAR_DCACHE_MISS 0x40000000UL 708#define MMCRA_SDAR_ERAT_MISS 0x20000000UL 709#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 710#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 711#define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 712#define MMCRA_SLOT_SHIFT 24 713#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 714#define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ 715#define POWER6_MMCRA_SIHV 0x0000040000000000ULL 716#define POWER6_MMCRA_SIPR 0x0000020000000000ULL 717#define POWER6_MMCRA_THRM 0x00000020UL 718#define POWER6_MMCRA_OTHER 0x0000000EUL 719 720#define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */ 721#define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */ 722 723#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ 724#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ 725#define SPRN_MMCRC 851 /* Core monitor mode control register */ 726#define SPRN_EBBHR 804 /* Event based branch handler register */ 727#define SPRN_EBBRR 805 /* Event based branch return register */ 728#define SPRN_BESCR 806 /* Branch event status and control register */ 729#define BESCR_GE 0x8000000000000000ULL /* Global Enable */ 730#define SPRN_WORT 895 /* Workload optimization register - thread */ 731 732#define SPRN_PMC1 787 733#define SPRN_PMC2 788 734#define SPRN_PMC3 789 735#define SPRN_PMC4 790 736#define SPRN_PMC5 791 737#define SPRN_PMC6 792 738#define SPRN_PMC7 793 739#define SPRN_PMC8 794 740#define SPRN_SIAR 780 741#define SPRN_SDAR 781 742#define SPRN_SIER 784 743#define SIER_SIPR 0x2000000 /* Sampled MSR_PR */ 744#define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ 745#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ 746#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ 747#define SPRN_TACR 888 748#define SPRN_TCSCR 889 749#define SPRN_CSIGR 890 750#define SPRN_SPMC1 892 751#define SPRN_SPMC2 893 752 753/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */ 754#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO) 755#define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */ 756#define SIER_USER_MASK 0x7fffffUL 757 758#define SPRN_PA6T_MMCR0 795 759#define PA6T_MMCR0_EN0 0x0000000000000001UL 760#define PA6T_MMCR0_EN1 0x0000000000000002UL 761#define PA6T_MMCR0_EN2 0x0000000000000004UL 762#define PA6T_MMCR0_EN3 0x0000000000000008UL 763#define PA6T_MMCR0_EN4 0x0000000000000010UL 764#define PA6T_MMCR0_EN5 0x0000000000000020UL 765#define PA6T_MMCR0_SUPEN 0x0000000000000040UL 766#define PA6T_MMCR0_PREN 0x0000000000000080UL 767#define PA6T_MMCR0_HYPEN 0x0000000000000100UL 768#define PA6T_MMCR0_FCM0 0x0000000000000200UL 769#define PA6T_MMCR0_FCM1 0x0000000000000400UL 770#define PA6T_MMCR0_INTGEN 0x0000000000000800UL 771#define PA6T_MMCR0_INTEN0 0x0000000000001000UL 772#define PA6T_MMCR0_INTEN1 0x0000000000002000UL 773#define PA6T_MMCR0_INTEN2 0x0000000000004000UL 774#define PA6T_MMCR0_INTEN3 0x0000000000008000UL 775#define PA6T_MMCR0_INTEN4 0x0000000000010000UL 776#define PA6T_MMCR0_INTEN5 0x0000000000020000UL 777#define PA6T_MMCR0_DISCNT 0x0000000000040000UL 778#define PA6T_MMCR0_UOP 0x0000000000080000UL 779#define PA6T_MMCR0_TRG 0x0000000000100000UL 780#define PA6T_MMCR0_TRGEN 0x0000000000200000UL 781#define PA6T_MMCR0_TRGREG 0x0000000001600000UL 782#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL 783#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL 784#define PA6T_MMCR0_PROEN 0x0000000008000000UL 785#define PA6T_MMCR0_PROLOG 0x0000000010000000UL 786#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL 787#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL 788#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL 789#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL 790#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL 791#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL 792#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL 793#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL 794#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL 795#define PA6T_MMCR0_PCTEN 0x0000004000000000UL 796#define PA6T_MMCR0_SOCEN 0x0000008000000000UL 797#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL 798 799#define SPRN_PA6T_MMCR1 798 800#define PA6T_MMCR1_ES2 0x00000000000000ffUL 801#define PA6T_MMCR1_ES3 0x000000000000ff00UL 802#define PA6T_MMCR1_ES4 0x0000000000ff0000UL 803#define PA6T_MMCR1_ES5 0x00000000ff000000UL 804 805#define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ 806#define SPRN_PA6T_UPMC1 772 /* ... */ 807#define SPRN_PA6T_UPMC2 773 808#define SPRN_PA6T_UPMC3 774 809#define SPRN_PA6T_UPMC4 775 810#define SPRN_PA6T_UPMC5 776 811#define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ 812#define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ 813#define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ 814#define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ 815#define SPRN_PA6T_PMC0 787 816#define SPRN_PA6T_PMC1 788 817#define SPRN_PA6T_PMC2 789 818#define SPRN_PA6T_PMC3 790 819#define SPRN_PA6T_PMC4 791 820#define SPRN_PA6T_PMC5 792 821#define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ 822#define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ 823#define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ 824#define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ 825 826#define SPRN_PA6T_IER 981 /* Icache Error Register */ 827#define SPRN_PA6T_DER 982 /* Dcache Error Register */ 828#define SPRN_PA6T_BER 862 /* BIU Error Address Register */ 829#define SPRN_PA6T_MER 849 /* MMU Error Register */ 830 831#define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ 832#define SPRN_PA6T_IMA1 881 /* ... */ 833#define SPRN_PA6T_IMA2 882 834#define SPRN_PA6T_IMA3 883 835#define SPRN_PA6T_IMA4 884 836#define SPRN_PA6T_IMA5 885 837#define SPRN_PA6T_IMA6 886 838#define SPRN_PA6T_IMA7 887 839#define SPRN_PA6T_IMA8 888 840#define SPRN_PA6T_IMA9 889 841#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 842#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 843#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 844#define SPRN_BKMK 1020 /* Cell Bookmark Register */ 845#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 846 847 848#else /* 32-bit */ 849#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 850#define MMCR0_FC 0x80000000UL /* freeze counters */ 851#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 852#define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 853#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 854#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 855#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 856#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 857#define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 858#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 859#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ 860#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 861#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ 862#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ 863 864#define SPRN_MMCR1 956 865#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ 866#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ 867#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ 868#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ 869#define SPRN_MMCR2 944 870#define SPRN_PMC1 953 /* Performance Counter Register 1 */ 871#define SPRN_PMC2 954 /* Performance Counter Register 2 */ 872#define SPRN_PMC3 957 /* Performance Counter Register 3 */ 873#define SPRN_PMC4 958 /* Performance Counter Register 4 */ 874#define SPRN_PMC5 945 /* Performance Counter Register 5 */ 875#define SPRN_PMC6 946 /* Performance Counter Register 6 */ 876 877#define SPRN_SIAR 955 /* Sampled Instruction Address Register */ 878 879/* Bit definitions for MMCR0 and PMC1 / PMC2. */ 880#define MMCR0_PMC1_CYCLES (1 << 7) 881#define MMCR0_PMC1_ICACHEMISS (5 << 7) 882#define MMCR0_PMC1_DTLB (6 << 7) 883#define MMCR0_PMC2_DCACHEMISS 0x6 884#define MMCR0_PMC2_CYCLES 0x1 885#define MMCR0_PMC2_ITLB 0x7 886#define MMCR0_PMC2_LOADMISSTIME 0x5 887#endif 888 889/* 890 * SPRG usage: 891 * 892 * All 64-bit: 893 * - SPRG1 stores PACA pointer except 64-bit server in 894 * HV mode in which case it is HSPRG0 895 * 896 * 64-bit server: 897 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4) 898 * - SPRG2 scratch for exception vectors 899 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) 900 * - HSPRG0 stores PACA in HV mode 901 * - HSPRG1 scratch for "HV" exceptions 902 * 903 * 64-bit embedded 904 * - SPRG0 generic exception scratch 905 * - SPRG2 TLB exception stack 906 * - SPRG3 critical exception scratch (user visible, sorry!) 907 * - SPRG4 unused (user visible) 908 * - SPRG6 TLB miss scratch (user visible, sorry !) 909 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible) 910 * - SPRG8 machine check exception scratch 911 * - SPRG9 debug exception scratch 912 * 913 * All 32-bit: 914 * - SPRG3 current thread_info pointer 915 * (virtual on BookE, physical on others) 916 * 917 * 32-bit classic: 918 * - SPRG0 scratch for exception vectors 919 * - SPRG1 scratch for exception vectors 920 * - SPRG2 indicator that we are in RTAS 921 * - SPRG4 (603 only) pseudo TLB LRU data 922 * 923 * 32-bit 40x: 924 * - SPRG0 scratch for exception vectors 925 * - SPRG1 scratch for exception vectors 926 * - SPRG2 scratch for exception vectors 927 * - SPRG4 scratch for exception vectors (not 403) 928 * - SPRG5 scratch for exception vectors (not 403) 929 * - SPRG6 scratch for exception vectors (not 403) 930 * - SPRG7 scratch for exception vectors (not 403) 931 * 932 * 32-bit 440 and FSL BookE: 933 * - SPRG0 scratch for exception vectors 934 * - SPRG1 scratch for exception vectors (*) 935 * - SPRG2 scratch for crit interrupts handler 936 * - SPRG4 scratch for exception vectors 937 * - SPRG5 scratch for exception vectors 938 * - SPRG6 scratch for machine check handler 939 * - SPRG7 scratch for exception vectors 940 * - SPRG9 scratch for debug vectors (e500 only) 941 * 942 * Additionally, BookE separates "read" and "write" 943 * of those registers. That allows to use the userspace 944 * readable variant for reads, which can avoid a fault 945 * with KVM type virtualization. 946 * 947 * (*) Under KVM, the host SPRG1 is used to point to 948 * the current VCPU data structure 949 * 950 * 32-bit 8xx: 951 * - SPRG0 scratch for exception vectors 952 * - SPRG1 scratch for exception vectors 953 * - SPRG2 apparently unused but initialized 954 * 955 */ 956#ifdef CONFIG_PPC64 957#define SPRN_SPRG_PACA SPRN_SPRG1 958#else 959#define SPRN_SPRG_THREAD SPRN_SPRG3 960#endif 961 962#ifdef CONFIG_PPC_BOOK3S_64 963#define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 964#define SPRN_SPRG_HPACA SPRN_HSPRG0 965#define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 966#define SPRN_SPRG_VDSO_READ SPRN_USPRG3 967#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3 968 969#define GET_PACA(rX) \ 970 BEGIN_FTR_SECTION_NESTED(66); \ 971 mfspr rX,SPRN_SPRG_PACA; \ 972 FTR_SECTION_ELSE_NESTED(66); \ 973 mfspr rX,SPRN_SPRG_HPACA; \ 974 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 975 976#define SET_PACA(rX) \ 977 BEGIN_FTR_SECTION_NESTED(66); \ 978 mtspr SPRN_SPRG_PACA,rX; \ 979 FTR_SECTION_ELSE_NESTED(66); \ 980 mtspr SPRN_SPRG_HPACA,rX; \ 981 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 982 983#define GET_SCRATCH0(rX) \ 984 BEGIN_FTR_SECTION_NESTED(66); \ 985 mfspr rX,SPRN_SPRG_SCRATCH0; \ 986 FTR_SECTION_ELSE_NESTED(66); \ 987 mfspr rX,SPRN_SPRG_HSCRATCH0; \ 988 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 989 990#define SET_SCRATCH0(rX) \ 991 BEGIN_FTR_SECTION_NESTED(66); \ 992 mtspr SPRN_SPRG_SCRATCH0,rX; \ 993 FTR_SECTION_ELSE_NESTED(66); \ 994 mtspr SPRN_SPRG_HSCRATCH0,rX; \ 995 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) 996 997#else /* CONFIG_PPC_BOOK3S_64 */ 998#define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0 999#define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX 1000 1001#endif 1002 1003#ifdef CONFIG_PPC_BOOK3E_64 1004#define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 1005#define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3 1006#define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 1007#define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 1008#define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 1009#define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 1010#define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH 1011#define SPRN_SPRG_VDSO_READ SPRN_USPRG7 1012#define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7 1013 1014#define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX 1015#define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA 1016 1017#endif 1018 1019#ifdef CONFIG_PPC_BOOK3S_32 1020#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1021#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1022#define SPRN_SPRG_RTAS SPRN_SPRG2 1023#define SPRN_SPRG_603_LRU SPRN_SPRG4 1024#endif 1025 1026#ifdef CONFIG_40x 1027#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1028#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1029#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 1030#define SPRN_SPRG_SCRATCH3 SPRN_SPRG4 1031#define SPRN_SPRG_SCRATCH4 SPRN_SPRG5 1032#define SPRN_SPRG_SCRATCH5 SPRN_SPRG6 1033#define SPRN_SPRG_SCRATCH6 SPRN_SPRG7 1034#endif 1035 1036#ifdef CONFIG_BOOKE 1037#define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0 1038#define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0 1039#define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1 1040#define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1 1041#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2 1042#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2 1043#define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R 1044#define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W 1045#define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R 1046#define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W 1047#define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1 1048#define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1 1049#define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R 1050#define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W 1051#ifdef CONFIG_E200 1052#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R 1053#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W 1054#else 1055#define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9 1056#define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9 1057#endif 1058#endif 1059 1060#ifdef CONFIG_8xx 1061#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1062#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1063#endif 1064 1065 1066 1067/* 1068 * An mtfsf instruction with the L bit set. On CPUs that support this a 1069 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 1070 * 1071 * Until binutils gets the new form of mtfsf, hardwire the instruction. 1072 */ 1073#ifdef CONFIG_PPC64 1074#define MTFSF_L(REG) \ 1075 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) 1076#else 1077#define MTFSF_L(REG) mtfsf 0xff, (REG) 1078#endif 1079 1080/* Processor Version Register (PVR) field extraction */ 1081 1082#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 1083#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 1084 1085#define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr)) 1086 1087/* 1088 * IBM has further subdivided the standard PowerPC 16-bit version and 1089 * revision subfields of the PVR for the PowerPC 403s into the following: 1090 */ 1091 1092#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 1093#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 1094#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 1095#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 1096#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 1097#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 1098 1099/* Processor Version Numbers */ 1100 1101#define PVR_403GA 0x00200000 1102#define PVR_403GB 0x00200100 1103#define PVR_403GC 0x00200200 1104#define PVR_403GCX 0x00201400 1105#define PVR_405GP 0x40110000 1106#define PVR_476 0x11a52000 1107#define PVR_476FPE 0x7ff50000 1108#define PVR_STB03XXX 0x40310000 1109#define PVR_NP405H 0x41410000 1110#define PVR_NP405L 0x41610000 1111#define PVR_601 0x00010000 1112#define PVR_602 0x00050000 1113#define PVR_603 0x00030000 1114#define PVR_603e 0x00060000 1115#define PVR_603ev 0x00070000 1116#define PVR_603r 0x00071000 1117#define PVR_604 0x00040000 1118#define PVR_604e 0x00090000 1119#define PVR_604r 0x000A0000 1120#define PVR_620 0x00140000 1121#define PVR_740 0x00080000 1122#define PVR_750 PVR_740 1123#define PVR_740P 0x10080000 1124#define PVR_750P PVR_740P 1125#define PVR_7400 0x000C0000 1126#define PVR_7410 0x800C0000 1127#define PVR_7450 0x80000000 1128#define PVR_8540 0x80200000 1129#define PVR_8560 0x80200000 1130#define PVR_VER_E500V1 0x8020 1131#define PVR_VER_E500V2 0x8021 1132#define PVR_VER_E500MC 0x8023 1133#define PVR_VER_E5500 0x8024 1134#define PVR_VER_E6500 0x8040 1135 1136/* 1137 * For the 8xx processors, all of them report the same PVR family for 1138 * the PowerPC core. The various versions of these processors must be 1139 * differentiated by the version number in the Communication Processor 1140 * Module (CPM). 1141 */ 1142#define PVR_821 0x00500000 1143#define PVR_823 PVR_821 1144#define PVR_850 PVR_821 1145#define PVR_860 PVR_821 1146#define PVR_8240 0x00810100 1147#define PVR_8245 0x80811014 1148#define PVR_8260 PVR_8240 1149 1150/* 476 Simulator seems to currently have the PVR of the 602... */ 1151#define PVR_476_ISS 0x00052000 1152 1153/* 64-bit processors */ 1154#define PVR_NORTHSTAR 0x0033 1155#define PVR_PULSAR 0x0034 1156#define PVR_POWER4 0x0035 1157#define PVR_ICESTAR 0x0036 1158#define PVR_SSTAR 0x0037 1159#define PVR_POWER4p 0x0038 1160#define PVR_970 0x0039 1161#define PVR_POWER5 0x003A 1162#define PVR_POWER5p 0x003B 1163#define PVR_970FX 0x003C 1164#define PVR_POWER6 0x003E 1165#define PVR_POWER7 0x003F 1166#define PVR_630 0x0040 1167#define PVR_630p 0x0041 1168#define PVR_970MP 0x0044 1169#define PVR_970GX 0x0045 1170#define PVR_POWER7p 0x004A 1171#define PVR_POWER8E 0x004B 1172#define PVR_POWER8 0x004D 1173#define PVR_BE 0x0070 1174#define PVR_PA6T 0x0090 1175 1176/* "Logical" PVR values defined in PAPR, representing architecture levels */ 1177#define PVR_ARCH_204 0x0f000001 1178#define PVR_ARCH_205 0x0f000002 1179#define PVR_ARCH_206 0x0f000003 1180#define PVR_ARCH_206p 0x0f100003 1181#define PVR_ARCH_207 0x0f000004 1182 1183/* Macros for setting and retrieving special purpose registers */ 1184#ifndef __ASSEMBLY__ 1185#define mfmsr() ({unsigned long rval; \ 1186 asm volatile("mfmsr %0" : "=r" (rval) : \ 1187 : "memory"); rval;}) 1188#ifdef CONFIG_PPC_BOOK3S_64 1189#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 1190 : : "r" (v) : "memory") 1191#define mtmsrd(v) __mtmsrd((v), 0) 1192#define mtmsr(v) mtmsrd(v) 1193#else 1194#define mtmsr(v) asm volatile("mtmsr %0" : \ 1195 : "r" ((unsigned long)(v)) \ 1196 : "memory") 1197#endif 1198 1199#define mfspr(rn) ({unsigned long rval; \ 1200 asm volatile("mfspr %0," __stringify(rn) \ 1201 : "=r" (rval)); rval;}) 1202#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ 1203 : "r" ((unsigned long)(v)) \ 1204 : "memory") 1205 1206static inline unsigned long mfvtb (void) 1207{ 1208#ifdef CONFIG_PPC_BOOK3S_64 1209 if (cpu_has_feature(CPU_FTR_ARCH_207S)) 1210 return mfspr(SPRN_VTB); 1211#endif 1212 return 0; 1213} 1214 1215#ifdef __powerpc64__ 1216#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 1217#define mftb() ({unsigned long rval; \ 1218 asm volatile( \ 1219 "90: mfspr %0, %2;\n" \ 1220 "97: cmpwi %0,0;\n" \ 1221 " beq- 90b;\n" \ 1222 "99:\n" \ 1223 ".section __ftr_fixup,\"a\"\n" \ 1224 ".align 3\n" \ 1225 "98:\n" \ 1226 " .llong %1\n" \ 1227 " .llong %1\n" \ 1228 " .llong 97b-98b\n" \ 1229 " .llong 99b-98b\n" \ 1230 " .llong 0\n" \ 1231 " .llong 0\n" \ 1232 ".previous" \ 1233 : "=r" (rval) \ 1234 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \ 1235 rval;}) 1236#else 1237#define mftb() ({unsigned long rval; \ 1238 asm volatile("mfspr %0, %1" : \ 1239 "=r" (rval) : "i" (SPRN_TBRL)); rval;}) 1240#endif /* !CONFIG_PPC_CELL */ 1241 1242#else /* __powerpc64__ */ 1243 1244#if defined(CONFIG_8xx) 1245#define mftbl() ({unsigned long rval; \ 1246 asm volatile("mftbl %0" : "=r" (rval)); rval;}) 1247#define mftbu() ({unsigned long rval; \ 1248 asm volatile("mftbu %0" : "=r" (rval)); rval;}) 1249#else 1250#define mftbl() ({unsigned long rval; \ 1251 asm volatile("mfspr %0, %1" : "=r" (rval) : \ 1252 "i" (SPRN_TBRL)); rval;}) 1253#define mftbu() ({unsigned long rval; \ 1254 asm volatile("mfspr %0, %1" : "=r" (rval) : \ 1255 "i" (SPRN_TBRU)); rval;}) 1256#endif 1257#endif /* !__powerpc64__ */ 1258 1259#define mttbl(v) asm volatile("mttbl %0":: "r"(v)) 1260#define mttbu(v) asm volatile("mttbu %0":: "r"(v)) 1261 1262#ifdef CONFIG_PPC32 1263#define mfsrin(v) ({unsigned int rval; \ 1264 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ 1265 rval;}) 1266#endif 1267 1268#define proc_trap() asm volatile("trap") 1269 1270#define __get_SP() ({unsigned long sp; \ 1271 asm volatile("mr %0,1": "=r" (sp)); sp;}) 1272 1273extern unsigned long scom970_read(unsigned int address); 1274extern void scom970_write(unsigned int address, unsigned long value); 1275 1276struct pt_regs; 1277 1278extern void ppc_save_regs(struct pt_regs *regs); 1279 1280#endif /* __ASSEMBLY__ */ 1281#endif /* __KERNEL__ */ 1282#endif /* _ASM_POWERPC_REG_H */ 1283