1/* 2 * Derived from arch/i386/kernel/irq.c 3 * Copyright (C) 1992 Linus Torvalds 4 * Adapted from arch/i386 by Gary Thomas 5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Updated and modified by Cort Dougan <cort@fsmlabs.com> 7 * Copyright (C) 1996-2001 Cort Dougan 8 * Adapted for Power Macintosh by Paul Mackerras 9 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au) 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 * 16 * This file contains the code used by various IRQ handling routines: 17 * asking for different IRQ's should be done through these routines 18 * instead of just grabbing them. Thus setups with different IRQ numbers 19 * shouldn't result in any weird surprises, and installing new handlers 20 * should be easier. 21 * 22 * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the 23 * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit 24 * mask register (of which only 16 are defined), hence the weird shifting 25 * and complement of the cached_irq_mask. I want to be able to stuff 26 * this right into the SIU SMASK register. 27 * Many of the prep/chrp functions are conditional compiled on CONFIG_8xx 28 * to reduce code space and undefined function references. 29 */ 30 31#undef DEBUG 32 33#include <linux/export.h> 34#include <linux/threads.h> 35#include <linux/kernel_stat.h> 36#include <linux/signal.h> 37#include <linux/sched.h> 38#include <linux/ptrace.h> 39#include <linux/ioport.h> 40#include <linux/interrupt.h> 41#include <linux/timex.h> 42#include <linux/init.h> 43#include <linux/slab.h> 44#include <linux/delay.h> 45#include <linux/irq.h> 46#include <linux/seq_file.h> 47#include <linux/cpumask.h> 48#include <linux/profile.h> 49#include <linux/bitops.h> 50#include <linux/list.h> 51#include <linux/radix-tree.h> 52#include <linux/mutex.h> 53#include <linux/bootmem.h> 54#include <linux/pci.h> 55#include <linux/debugfs.h> 56#include <linux/of.h> 57#include <linux/of_irq.h> 58 59#include <asm/uaccess.h> 60#include <asm/io.h> 61#include <asm/pgtable.h> 62#include <asm/irq.h> 63#include <asm/cache.h> 64#include <asm/prom.h> 65#include <asm/ptrace.h> 66#include <asm/machdep.h> 67#include <asm/udbg.h> 68#include <asm/smp.h> 69#include <asm/debug.h> 70 71#ifdef CONFIG_PPC64 72#include <asm/paca.h> 73#include <asm/firmware.h> 74#include <asm/lv1call.h> 75#endif 76#define CREATE_TRACE_POINTS 77#include <asm/trace.h> 78 79DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); 80EXPORT_PER_CPU_SYMBOL(irq_stat); 81 82int __irq_offset_value; 83 84#ifdef CONFIG_PPC32 85EXPORT_SYMBOL(__irq_offset_value); 86atomic_t ppc_n_lost_interrupts; 87 88#ifdef CONFIG_TAU_INT 89extern int tau_initialized; 90extern int tau_interrupts(int); 91#endif 92#endif /* CONFIG_PPC32 */ 93 94#ifdef CONFIG_PPC64 95 96int distribute_irqs = 1; 97 98static inline notrace unsigned long get_irq_happened(void) 99{ 100 unsigned long happened; 101 102 __asm__ __volatile__("lbz %0,%1(13)" 103 : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened))); 104 105 return happened; 106} 107 108static inline notrace void set_soft_enabled(unsigned long enable) 109{ 110 __asm__ __volatile__("stb %0,%1(13)" 111 : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled))); 112} 113 114static inline notrace int decrementer_check_overflow(void) 115{ 116 u64 now = get_tb_or_rtc(); 117 u64 *next_tb = &__get_cpu_var(decrementers_next_tb); 118 119 return now >= *next_tb; 120} 121 122/* This is called whenever we are re-enabling interrupts 123 * and returns either 0 (nothing to do) or 500/900/280/a00/e80 if 124 * there's an EE, DEC or DBELL to generate. 125 * 126 * This is called in two contexts: From arch_local_irq_restore() 127 * before soft-enabling interrupts, and from the exception exit 128 * path when returning from an interrupt from a soft-disabled to 129 * a soft enabled context. In both case we have interrupts hard 130 * disabled. 131 * 132 * We take care of only clearing the bits we handled in the 133 * PACA irq_happened field since we can only re-emit one at a 134 * time and we don't want to "lose" one. 135 */ 136notrace unsigned int __check_irq_replay(void) 137{ 138 /* 139 * We use local_paca rather than get_paca() to avoid all 140 * the debug_smp_processor_id() business in this low level 141 * function 142 */ 143 unsigned char happened = local_paca->irq_happened; 144 145 /* Clear bit 0 which we wouldn't clear otherwise */ 146 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; 147 148 /* 149 * Force the delivery of pending soft-disabled interrupts on PS3. 150 * Any HV call will have this side effect. 151 */ 152 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { 153 u64 tmp, tmp2; 154 lv1_get_version_info(&tmp, &tmp2); 155 } 156 157 /* 158 * We may have missed a decrementer interrupt. We check the 159 * decrementer itself rather than the paca irq_happened field 160 * in case we also had a rollover while hard disabled 161 */ 162 local_paca->irq_happened &= ~PACA_IRQ_DEC; 163 if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow()) 164 return 0x900; 165 166 /* Finally check if an external interrupt happened */ 167 local_paca->irq_happened &= ~PACA_IRQ_EE; 168 if (happened & PACA_IRQ_EE) 169 return 0x500; 170 171#ifdef CONFIG_PPC_BOOK3E 172 /* Finally check if an EPR external interrupt happened 173 * this bit is typically set if we need to handle another 174 * "edge" interrupt from within the MPIC "EPR" handler 175 */ 176 local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE; 177 if (happened & PACA_IRQ_EE_EDGE) 178 return 0x500; 179 180 local_paca->irq_happened &= ~PACA_IRQ_DBELL; 181 if (happened & PACA_IRQ_DBELL) 182 return 0x280; 183#else 184 local_paca->irq_happened &= ~PACA_IRQ_DBELL; 185 if (happened & PACA_IRQ_DBELL) { 186 if (cpu_has_feature(CPU_FTR_HVMODE)) 187 return 0xe80; 188 return 0xa00; 189 } 190#endif /* CONFIG_PPC_BOOK3E */ 191 192 /* Check if an hypervisor Maintenance interrupt happened */ 193 local_paca->irq_happened &= ~PACA_IRQ_HMI; 194 if (happened & PACA_IRQ_HMI) 195 return 0xe60; 196 197 /* There should be nothing left ! */ 198 BUG_ON(local_paca->irq_happened != 0); 199 200 return 0; 201} 202 203notrace void arch_local_irq_restore(unsigned long en) 204{ 205 unsigned char irq_happened; 206 unsigned int replay; 207 208 /* Write the new soft-enabled value */ 209 set_soft_enabled(en); 210 if (!en) 211 return; 212 /* 213 * From this point onward, we can take interrupts, preempt, 214 * etc... unless we got hard-disabled. We check if an event 215 * happened. If none happened, we know we can just return. 216 * 217 * We may have preempted before the check below, in which case 218 * we are checking the "new" CPU instead of the old one. This 219 * is only a problem if an event happened on the "old" CPU. 220 * 221 * External interrupt events will have caused interrupts to 222 * be hard-disabled, so there is no problem, we 223 * cannot have preempted. 224 */ 225 irq_happened = get_irq_happened(); 226 if (!irq_happened) 227 return; 228 229 /* 230 * We need to hard disable to get a trusted value from 231 * __check_irq_replay(). We also need to soft-disable 232 * again to avoid warnings in there due to the use of 233 * per-cpu variables. 234 * 235 * We know that if the value in irq_happened is exactly 0x01 236 * then we are already hard disabled (there are other less 237 * common cases that we'll ignore for now), so we skip the 238 * (expensive) mtmsrd. 239 */ 240 if (unlikely(irq_happened != PACA_IRQ_HARD_DIS)) 241 __hard_irq_disable(); 242#ifdef CONFIG_TRACE_IRQFLAGS 243 else { 244 /* 245 * We should already be hard disabled here. We had bugs 246 * where that wasn't the case so let's dbl check it and 247 * warn if we are wrong. Only do that when IRQ tracing 248 * is enabled as mfmsr() can be costly. 249 */ 250 if (WARN_ON(mfmsr() & MSR_EE)) 251 __hard_irq_disable(); 252 } 253#endif /* CONFIG_TRACE_IRQFLAG */ 254 255 set_soft_enabled(0); 256 257 /* 258 * Check if anything needs to be re-emitted. We haven't 259 * soft-enabled yet to avoid warnings in decrementer_check_overflow 260 * accessing per-cpu variables 261 */ 262 replay = __check_irq_replay(); 263 264 /* We can soft-enable now */ 265 set_soft_enabled(1); 266 267 /* 268 * And replay if we have to. This will return with interrupts 269 * hard-enabled. 270 */ 271 if (replay) { 272 __replay_interrupt(replay); 273 return; 274 } 275 276 /* Finally, let's ensure we are hard enabled */ 277 __hard_irq_enable(); 278} 279EXPORT_SYMBOL(arch_local_irq_restore); 280 281/* 282 * This is specifically called by assembly code to re-enable interrupts 283 * if they are currently disabled. This is typically called before 284 * schedule() or do_signal() when returning to userspace. We do it 285 * in C to avoid the burden of dealing with lockdep etc... 286 * 287 * NOTE: This is called with interrupts hard disabled but not marked 288 * as such in paca->irq_happened, so we need to resync this. 289 */ 290void notrace restore_interrupts(void) 291{ 292 if (irqs_disabled()) { 293 local_paca->irq_happened |= PACA_IRQ_HARD_DIS; 294 local_irq_enable(); 295 } else 296 __hard_irq_enable(); 297} 298 299/* 300 * This is a helper to use when about to go into idle low-power 301 * when the latter has the side effect of re-enabling interrupts 302 * (such as calling H_CEDE under pHyp). 303 * 304 * You call this function with interrupts soft-disabled (this is 305 * already the case when ppc_md.power_save is called). The function 306 * will return whether to enter power save or just return. 307 * 308 * In the former case, it will have notified lockdep of interrupts 309 * being re-enabled and generally sanitized the lazy irq state, 310 * and in the latter case it will leave with interrupts hard 311 * disabled and marked as such, so the local_irq_enable() call 312 * in arch_cpu_idle() will properly re-enable everything. 313 */ 314bool prep_irq_for_idle(void) 315{ 316 /* 317 * First we need to hard disable to ensure no interrupt 318 * occurs before we effectively enter the low power state 319 */ 320 hard_irq_disable(); 321 322 /* 323 * If anything happened while we were soft-disabled, 324 * we return now and do not enter the low power state. 325 */ 326 if (lazy_irq_pending()) 327 return false; 328 329 /* Tell lockdep we are about to re-enable */ 330 trace_hardirqs_on(); 331 332 /* 333 * Mark interrupts as soft-enabled and clear the 334 * PACA_IRQ_HARD_DIS from the pending mask since we 335 * are about to hard enable as well as a side effect 336 * of entering the low power state. 337 */ 338 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; 339 local_paca->soft_enabled = 1; 340 341 /* Tell the caller to enter the low power state */ 342 return true; 343} 344 345#endif /* CONFIG_PPC64 */ 346 347int arch_show_interrupts(struct seq_file *p, int prec) 348{ 349 int j; 350 351#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT) 352 if (tau_initialized) { 353 seq_printf(p, "%*s: ", prec, "TAU"); 354 for_each_online_cpu(j) 355 seq_printf(p, "%10u ", tau_interrupts(j)); 356 seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n"); 357 } 358#endif /* CONFIG_PPC32 && CONFIG_TAU_INT */ 359 360 seq_printf(p, "%*s: ", prec, "LOC"); 361 for_each_online_cpu(j) 362 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event); 363 seq_printf(p, " Local timer interrupts for timer event device\n"); 364 365 seq_printf(p, "%*s: ", prec, "LOC"); 366 for_each_online_cpu(j) 367 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others); 368 seq_printf(p, " Local timer interrupts for others\n"); 369 370 seq_printf(p, "%*s: ", prec, "SPU"); 371 for_each_online_cpu(j) 372 seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs); 373 seq_printf(p, " Spurious interrupts\n"); 374 375 seq_printf(p, "%*s: ", prec, "PMI"); 376 for_each_online_cpu(j) 377 seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs); 378 seq_printf(p, " Performance monitoring interrupts\n"); 379 380 seq_printf(p, "%*s: ", prec, "MCE"); 381 for_each_online_cpu(j) 382 seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions); 383 seq_printf(p, " Machine check exceptions\n"); 384 385 if (cpu_has_feature(CPU_FTR_HVMODE)) { 386 seq_printf(p, "%*s: ", prec, "HMI"); 387 for_each_online_cpu(j) 388 seq_printf(p, "%10u ", 389 per_cpu(irq_stat, j).hmi_exceptions); 390 seq_printf(p, " Hypervisor Maintenance Interrupts\n"); 391 } 392 393#ifdef CONFIG_PPC_DOORBELL 394 if (cpu_has_feature(CPU_FTR_DBELL)) { 395 seq_printf(p, "%*s: ", prec, "DBL"); 396 for_each_online_cpu(j) 397 seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs); 398 seq_printf(p, " Doorbell interrupts\n"); 399 } 400#endif 401 402 return 0; 403} 404 405/* 406 * /proc/stat helpers 407 */ 408u64 arch_irq_stat_cpu(unsigned int cpu) 409{ 410 u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event; 411 412 sum += per_cpu(irq_stat, cpu).pmu_irqs; 413 sum += per_cpu(irq_stat, cpu).mce_exceptions; 414 sum += per_cpu(irq_stat, cpu).spurious_irqs; 415 sum += per_cpu(irq_stat, cpu).timer_irqs_others; 416 sum += per_cpu(irq_stat, cpu).hmi_exceptions; 417#ifdef CONFIG_PPC_DOORBELL 418 sum += per_cpu(irq_stat, cpu).doorbell_irqs; 419#endif 420 421 return sum; 422} 423 424#ifdef CONFIG_HOTPLUG_CPU 425void migrate_irqs(void) 426{ 427 struct irq_desc *desc; 428 unsigned int irq; 429 static int warned; 430 cpumask_var_t mask; 431 const struct cpumask *map = cpu_online_mask; 432 433 alloc_cpumask_var(&mask, GFP_KERNEL); 434 435 for_each_irq_desc(irq, desc) { 436 struct irq_data *data; 437 struct irq_chip *chip; 438 439 data = irq_desc_get_irq_data(desc); 440 if (irqd_is_per_cpu(data)) 441 continue; 442 443 chip = irq_data_get_irq_chip(data); 444 445 cpumask_and(mask, data->affinity, map); 446 if (cpumask_any(mask) >= nr_cpu_ids) { 447 pr_warn("Breaking affinity for irq %i\n", irq); 448 cpumask_copy(mask, map); 449 } 450 if (chip->irq_set_affinity) 451 chip->irq_set_affinity(data, mask, true); 452 else if (desc->action && !(warned++)) 453 pr_err("Cannot set affinity for irq %i\n", irq); 454 } 455 456 free_cpumask_var(mask); 457 458 local_irq_enable(); 459 mdelay(1); 460 local_irq_disable(); 461} 462#endif 463 464static inline void check_stack_overflow(void) 465{ 466#ifdef CONFIG_DEBUG_STACKOVERFLOW 467 long sp; 468 469 sp = current_stack_pointer() & (THREAD_SIZE-1); 470 471 /* check for stack overflow: is there less than 2KB free? */ 472 if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { 473 pr_err("do_IRQ: stack overflow: %ld\n", 474 sp - sizeof(struct thread_info)); 475 dump_stack(); 476 } 477#endif 478} 479 480void __do_irq(struct pt_regs *regs) 481{ 482 unsigned int irq; 483 484 irq_enter(); 485 486 trace_irq_entry(regs); 487 488 check_stack_overflow(); 489 490 /* 491 * Query the platform PIC for the interrupt & ack it. 492 * 493 * This will typically lower the interrupt line to the CPU 494 */ 495 irq = ppc_md.get_irq(); 496 497 /* We can hard enable interrupts now to allow perf interrupts */ 498 may_hard_irq_enable(); 499 500 /* And finally process it */ 501 if (unlikely(irq == NO_IRQ)) 502 __get_cpu_var(irq_stat).spurious_irqs++; 503 else 504 generic_handle_irq(irq); 505 506 trace_irq_exit(regs); 507 508 irq_exit(); 509} 510 511void do_IRQ(struct pt_regs *regs) 512{ 513 struct pt_regs *old_regs = set_irq_regs(regs); 514 struct thread_info *curtp, *irqtp, *sirqtp; 515 516 /* Switch to the irq stack to handle this */ 517 curtp = current_thread_info(); 518 irqtp = hardirq_ctx[raw_smp_processor_id()]; 519 sirqtp = softirq_ctx[raw_smp_processor_id()]; 520 521 /* Already there ? */ 522 if (unlikely(curtp == irqtp || curtp == sirqtp)) { 523 __do_irq(regs); 524 set_irq_regs(old_regs); 525 return; 526 } 527 528 /* Prepare the thread_info in the irq stack */ 529 irqtp->task = curtp->task; 530 irqtp->flags = 0; 531 532 /* Copy the preempt_count so that the [soft]irq checks work. */ 533 irqtp->preempt_count = curtp->preempt_count; 534 535 /* Switch stack and call */ 536 call_do_irq(regs, irqtp); 537 538 /* Restore stack limit */ 539 irqtp->task = NULL; 540 541 /* Copy back updates to the thread_info */ 542 if (irqtp->flags) 543 set_bits(irqtp->flags, &curtp->flags); 544 545 set_irq_regs(old_regs); 546} 547 548void __init init_IRQ(void) 549{ 550 if (ppc_md.init_IRQ) 551 ppc_md.init_IRQ(); 552 553 exc_lvl_ctx_init(); 554 555 irq_ctx_init(); 556} 557 558#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 559struct thread_info *critirq_ctx[NR_CPUS] __read_mostly; 560struct thread_info *dbgirq_ctx[NR_CPUS] __read_mostly; 561struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly; 562 563void exc_lvl_ctx_init(void) 564{ 565 struct thread_info *tp; 566 int i, cpu_nr; 567 568 for_each_possible_cpu(i) { 569#ifdef CONFIG_PPC64 570 cpu_nr = i; 571#else 572#ifdef CONFIG_SMP 573 cpu_nr = get_hard_smp_processor_id(i); 574#else 575 cpu_nr = 0; 576#endif 577#endif 578 579 memset((void *)critirq_ctx[cpu_nr], 0, THREAD_SIZE); 580 tp = critirq_ctx[cpu_nr]; 581 tp->cpu = cpu_nr; 582 tp->preempt_count = 0; 583 584#ifdef CONFIG_BOOKE 585 memset((void *)dbgirq_ctx[cpu_nr], 0, THREAD_SIZE); 586 tp = dbgirq_ctx[cpu_nr]; 587 tp->cpu = cpu_nr; 588 tp->preempt_count = 0; 589 590 memset((void *)mcheckirq_ctx[cpu_nr], 0, THREAD_SIZE); 591 tp = mcheckirq_ctx[cpu_nr]; 592 tp->cpu = cpu_nr; 593 tp->preempt_count = HARDIRQ_OFFSET; 594#endif 595 } 596} 597#endif 598 599struct thread_info *softirq_ctx[NR_CPUS] __read_mostly; 600struct thread_info *hardirq_ctx[NR_CPUS] __read_mostly; 601 602void irq_ctx_init(void) 603{ 604 struct thread_info *tp; 605 int i; 606 607 for_each_possible_cpu(i) { 608 memset((void *)softirq_ctx[i], 0, THREAD_SIZE); 609 tp = softirq_ctx[i]; 610 tp->cpu = i; 611 612 memset((void *)hardirq_ctx[i], 0, THREAD_SIZE); 613 tp = hardirq_ctx[i]; 614 tp->cpu = i; 615 } 616} 617 618void do_softirq_own_stack(void) 619{ 620 struct thread_info *curtp, *irqtp; 621 622 curtp = current_thread_info(); 623 irqtp = softirq_ctx[smp_processor_id()]; 624 irqtp->task = curtp->task; 625 irqtp->flags = 0; 626 call_do_softirq(irqtp); 627 irqtp->task = NULL; 628 629 /* Set any flag that may have been set on the 630 * alternate stack 631 */ 632 if (irqtp->flags) 633 set_bits(irqtp->flags, &curtp->flags); 634} 635 636irq_hw_number_t virq_to_hw(unsigned int virq) 637{ 638 struct irq_data *irq_data = irq_get_irq_data(virq); 639 return WARN_ON(!irq_data) ? 0 : irq_data->hwirq; 640} 641EXPORT_SYMBOL_GPL(virq_to_hw); 642 643#ifdef CONFIG_SMP 644int irq_choose_cpu(const struct cpumask *mask) 645{ 646 int cpuid; 647 648 if (cpumask_equal(mask, cpu_online_mask)) { 649 static int irq_rover; 650 static DEFINE_RAW_SPINLOCK(irq_rover_lock); 651 unsigned long flags; 652 653 /* Round-robin distribution... */ 654do_round_robin: 655 raw_spin_lock_irqsave(&irq_rover_lock, flags); 656 657 irq_rover = cpumask_next(irq_rover, cpu_online_mask); 658 if (irq_rover >= nr_cpu_ids) 659 irq_rover = cpumask_first(cpu_online_mask); 660 661 cpuid = irq_rover; 662 663 raw_spin_unlock_irqrestore(&irq_rover_lock, flags); 664 } else { 665 cpuid = cpumask_first_and(mask, cpu_online_mask); 666 if (cpuid >= nr_cpu_ids) 667 goto do_round_robin; 668 } 669 670 return get_hard_smp_processor_id(cpuid); 671} 672#else 673int irq_choose_cpu(const struct cpumask *mask) 674{ 675 return hard_smp_processor_id(); 676} 677#endif 678 679int arch_early_irq_init(void) 680{ 681 return 0; 682} 683 684#ifdef CONFIG_PPC64 685static int __init setup_noirqdistrib(char *str) 686{ 687 distribute_irqs = 0; 688 return 1; 689} 690 691__setup("noirqdistrib", setup_noirqdistrib); 692#endif /* CONFIG_PPC64 */ 693