pci-common.c revision 6a040ce72598159a74969a2d01ab0ba5ee6536b3
1/* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/string.h> 22#include <linux/init.h> 23#include <linux/bootmem.h> 24#include <linux/export.h> 25#include <linux/of_address.h> 26#include <linux/of_pci.h> 27#include <linux/mm.h> 28#include <linux/list.h> 29#include <linux/syscalls.h> 30#include <linux/irq.h> 31#include <linux/vmalloc.h> 32#include <linux/slab.h> 33 34#include <asm/processor.h> 35#include <asm/io.h> 36#include <asm/prom.h> 37#include <asm/pci-bridge.h> 38#include <asm/byteorder.h> 39#include <asm/machdep.h> 40#include <asm/ppc-pci.h> 41#include <asm/eeh.h> 42 43static DEFINE_SPINLOCK(hose_spinlock); 44LIST_HEAD(hose_list); 45 46/* XXX kill that some day ... */ 47static int global_phb_number; /* Global phb counter */ 48 49/* ISA Memory physical address */ 50resource_size_t isa_mem_base; 51 52 53static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 54 55void set_pci_dma_ops(struct dma_map_ops *dma_ops) 56{ 57 pci_dma_ops = dma_ops; 58} 59 60struct dma_map_ops *get_pci_dma_ops(void) 61{ 62 return pci_dma_ops; 63} 64EXPORT_SYMBOL(get_pci_dma_ops); 65 66struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 67{ 68 struct pci_controller *phb; 69 70 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 71 if (phb == NULL) 72 return NULL; 73 spin_lock(&hose_spinlock); 74 phb->global_number = global_phb_number++; 75 list_add_tail(&phb->list_node, &hose_list); 76 spin_unlock(&hose_spinlock); 77 phb->dn = dev; 78 phb->is_dynamic = mem_init_done; 79#ifdef CONFIG_PPC64 80 if (dev) { 81 int nid = of_node_to_nid(dev); 82 83 if (nid < 0 || !node_online(nid)) 84 nid = -1; 85 86 PHB_SET_NODE(phb, nid); 87 } 88#endif 89 return phb; 90} 91 92void pcibios_free_controller(struct pci_controller *phb) 93{ 94 spin_lock(&hose_spinlock); 95 list_del(&phb->list_node); 96 spin_unlock(&hose_spinlock); 97 98 if (phb->is_dynamic) 99 kfree(phb); 100} 101 102/* 103 * The function is used to return the minimal alignment 104 * for memory or I/O windows of the associated P2P bridge. 105 * By default, 4KiB alignment for I/O windows and 1MiB for 106 * memory windows. 107 */ 108resource_size_t pcibios_window_alignment(struct pci_bus *bus, 109 unsigned long type) 110{ 111 if (ppc_md.pcibios_window_alignment) 112 return ppc_md.pcibios_window_alignment(bus, type); 113 114 /* 115 * PCI core will figure out the default 116 * alignment: 4KiB for I/O and 1MiB for 117 * memory window. 118 */ 119 return 1; 120} 121 122static resource_size_t pcibios_io_size(const struct pci_controller *hose) 123{ 124#ifdef CONFIG_PPC64 125 return hose->pci_io_size; 126#else 127 return resource_size(&hose->io_resource); 128#endif 129} 130 131int pcibios_vaddr_is_ioport(void __iomem *address) 132{ 133 int ret = 0; 134 struct pci_controller *hose; 135 resource_size_t size; 136 137 spin_lock(&hose_spinlock); 138 list_for_each_entry(hose, &hose_list, list_node) { 139 size = pcibios_io_size(hose); 140 if (address >= hose->io_base_virt && 141 address < (hose->io_base_virt + size)) { 142 ret = 1; 143 break; 144 } 145 } 146 spin_unlock(&hose_spinlock); 147 return ret; 148} 149 150unsigned long pci_address_to_pio(phys_addr_t address) 151{ 152 struct pci_controller *hose; 153 resource_size_t size; 154 unsigned long ret = ~0; 155 156 spin_lock(&hose_spinlock); 157 list_for_each_entry(hose, &hose_list, list_node) { 158 size = pcibios_io_size(hose); 159 if (address >= hose->io_base_phys && 160 address < (hose->io_base_phys + size)) { 161 unsigned long base = 162 (unsigned long)hose->io_base_virt - _IO_BASE; 163 ret = base + (address - hose->io_base_phys); 164 break; 165 } 166 } 167 spin_unlock(&hose_spinlock); 168 169 return ret; 170} 171EXPORT_SYMBOL_GPL(pci_address_to_pio); 172 173/* 174 * Return the domain number for this bus. 175 */ 176int pci_domain_nr(struct pci_bus *bus) 177{ 178 struct pci_controller *hose = pci_bus_to_host(bus); 179 180 return hose->global_number; 181} 182EXPORT_SYMBOL(pci_domain_nr); 183 184/* This routine is meant to be used early during boot, when the 185 * PCI bus numbers have not yet been assigned, and you need to 186 * issue PCI config cycles to an OF device. 187 * It could also be used to "fix" RTAS config cycles if you want 188 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 189 * config cycles. 190 */ 191struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 192{ 193 while(node) { 194 struct pci_controller *hose, *tmp; 195 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 196 if (hose->dn == node) 197 return hose; 198 node = node->parent; 199 } 200 return NULL; 201} 202 203static ssize_t pci_show_devspec(struct device *dev, 204 struct device_attribute *attr, char *buf) 205{ 206 struct pci_dev *pdev; 207 struct device_node *np; 208 209 pdev = to_pci_dev (dev); 210 np = pci_device_to_OF_node(pdev); 211 if (np == NULL || np->full_name == NULL) 212 return 0; 213 return sprintf(buf, "%s", np->full_name); 214} 215static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); 216 217/* Add sysfs properties */ 218int pcibios_add_platform_entries(struct pci_dev *pdev) 219{ 220 return device_create_file(&pdev->dev, &dev_attr_devspec); 221} 222 223/* 224 * Reads the interrupt pin to determine if interrupt is use by card. 225 * If the interrupt is used, then gets the interrupt line from the 226 * openfirmware and sets it in the pci_dev and pci_config line. 227 */ 228static int pci_read_irq_line(struct pci_dev *pci_dev) 229{ 230 struct of_irq oirq; 231 unsigned int virq; 232 233 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 234 235#ifdef DEBUG 236 memset(&oirq, 0xff, sizeof(oirq)); 237#endif 238 /* Try to get a mapping from the device-tree */ 239 if (of_irq_map_pci(pci_dev, &oirq)) { 240 u8 line, pin; 241 242 /* If that fails, lets fallback to what is in the config 243 * space and map that through the default controller. We 244 * also set the type to level low since that's what PCI 245 * interrupts are. If your platform does differently, then 246 * either provide a proper interrupt tree or don't use this 247 * function. 248 */ 249 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 250 return -1; 251 if (pin == 0) 252 return -1; 253 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 254 line == 0xff || line == 0) { 255 return -1; 256 } 257 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 258 line, pin); 259 260 virq = irq_create_mapping(NULL, line); 261 if (virq != NO_IRQ) 262 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 263 } else { 264 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 265 oirq.size, oirq.specifier[0], oirq.specifier[1], 266 of_node_full_name(oirq.controller)); 267 268 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 269 oirq.size); 270 } 271 if(virq == NO_IRQ) { 272 pr_debug(" Failed to map !\n"); 273 return -1; 274 } 275 276 pr_debug(" Mapped to linux irq %d\n", virq); 277 278 pci_dev->irq = virq; 279 280 return 0; 281} 282 283/* 284 * Platform support for /proc/bus/pci/X/Y mmap()s, 285 * modelled on the sparc64 implementation by Dave Miller. 286 * -- paulus. 287 */ 288 289/* 290 * Adjust vm_pgoff of VMA such that it is the physical page offset 291 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 292 * 293 * Basically, the user finds the base address for his device which he wishes 294 * to mmap. They read the 32-bit value from the config space base register, 295 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 296 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 297 * 298 * Returns negative error code on failure, zero on success. 299 */ 300static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 301 resource_size_t *offset, 302 enum pci_mmap_state mmap_state) 303{ 304 struct pci_controller *hose = pci_bus_to_host(dev->bus); 305 unsigned long io_offset = 0; 306 int i, res_bit; 307 308 if (hose == 0) 309 return NULL; /* should never happen */ 310 311 /* If memory, add on the PCI bridge address offset */ 312 if (mmap_state == pci_mmap_mem) { 313#if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 314 *offset += hose->pci_mem_offset; 315#endif 316 res_bit = IORESOURCE_MEM; 317 } else { 318 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 319 *offset += io_offset; 320 res_bit = IORESOURCE_IO; 321 } 322 323 /* 324 * Check that the offset requested corresponds to one of the 325 * resources of the device. 326 */ 327 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 328 struct resource *rp = &dev->resource[i]; 329 int flags = rp->flags; 330 331 /* treat ROM as memory (should be already) */ 332 if (i == PCI_ROM_RESOURCE) 333 flags |= IORESOURCE_MEM; 334 335 /* Active and same type? */ 336 if ((flags & res_bit) == 0) 337 continue; 338 339 /* In the range of this resource? */ 340 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 341 continue; 342 343 /* found it! construct the final physical address */ 344 if (mmap_state == pci_mmap_io) 345 *offset += hose->io_base_phys - io_offset; 346 return rp; 347 } 348 349 return NULL; 350} 351 352/* 353 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 354 * device mapping. 355 */ 356static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 357 pgprot_t protection, 358 enum pci_mmap_state mmap_state, 359 int write_combine) 360{ 361 unsigned long prot = pgprot_val(protection); 362 363 /* Write combine is always 0 on non-memory space mappings. On 364 * memory space, if the user didn't pass 1, we check for a 365 * "prefetchable" resource. This is a bit hackish, but we use 366 * this to workaround the inability of /sysfs to provide a write 367 * combine bit 368 */ 369 if (mmap_state != pci_mmap_mem) 370 write_combine = 0; 371 else if (write_combine == 0) { 372 if (rp->flags & IORESOURCE_PREFETCH) 373 write_combine = 1; 374 } 375 376 /* XXX would be nice to have a way to ask for write-through */ 377 if (write_combine) 378 return pgprot_noncached_wc(prot); 379 else 380 return pgprot_noncached(prot); 381} 382 383/* 384 * This one is used by /dev/mem and fbdev who have no clue about the 385 * PCI device, it tries to find the PCI device first and calls the 386 * above routine 387 */ 388pgprot_t pci_phys_mem_access_prot(struct file *file, 389 unsigned long pfn, 390 unsigned long size, 391 pgprot_t prot) 392{ 393 struct pci_dev *pdev = NULL; 394 struct resource *found = NULL; 395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 396 int i; 397 398 if (page_is_ram(pfn)) 399 return prot; 400 401 prot = pgprot_noncached(prot); 402 for_each_pci_dev(pdev) { 403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 404 struct resource *rp = &pdev->resource[i]; 405 int flags = rp->flags; 406 407 /* Active and same type? */ 408 if ((flags & IORESOURCE_MEM) == 0) 409 continue; 410 /* In the range of this resource? */ 411 if (offset < (rp->start & PAGE_MASK) || 412 offset > rp->end) 413 continue; 414 found = rp; 415 break; 416 } 417 if (found) 418 break; 419 } 420 if (found) { 421 if (found->flags & IORESOURCE_PREFETCH) 422 prot = pgprot_noncached_wc(prot); 423 pci_dev_put(pdev); 424 } 425 426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 427 (unsigned long long)offset, pgprot_val(prot)); 428 429 return prot; 430} 431 432 433/* 434 * Perform the actual remap of the pages for a PCI device mapping, as 435 * appropriate for this architecture. The region in the process to map 436 * is described by vm_start and vm_end members of VMA, the base physical 437 * address is found in vm_pgoff. 438 * The pci device structure is provided so that architectures may make mapping 439 * decisions on a per-device or per-bus basis. 440 * 441 * Returns a negative error code on failure, zero on success. 442 */ 443int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 444 enum pci_mmap_state mmap_state, int write_combine) 445{ 446 resource_size_t offset = 447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 448 struct resource *rp; 449 int ret; 450 451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 452 if (rp == NULL) 453 return -EINVAL; 454 455 vma->vm_pgoff = offset >> PAGE_SHIFT; 456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 457 vma->vm_page_prot, 458 mmap_state, write_combine); 459 460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 461 vma->vm_end - vma->vm_start, vma->vm_page_prot); 462 463 return ret; 464} 465 466/* This provides legacy IO read access on a bus */ 467int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 468{ 469 unsigned long offset; 470 struct pci_controller *hose = pci_bus_to_host(bus); 471 struct resource *rp = &hose->io_resource; 472 void __iomem *addr; 473 474 /* Check if port can be supported by that bus. We only check 475 * the ranges of the PHB though, not the bus itself as the rules 476 * for forwarding legacy cycles down bridges are not our problem 477 * here. So if the host bridge supports it, we do it. 478 */ 479 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 480 offset += port; 481 482 if (!(rp->flags & IORESOURCE_IO)) 483 return -ENXIO; 484 if (offset < rp->start || (offset + size) > rp->end) 485 return -ENXIO; 486 addr = hose->io_base_virt + port; 487 488 switch(size) { 489 case 1: 490 *((u8 *)val) = in_8(addr); 491 return 1; 492 case 2: 493 if (port & 1) 494 return -EINVAL; 495 *((u16 *)val) = in_le16(addr); 496 return 2; 497 case 4: 498 if (port & 3) 499 return -EINVAL; 500 *((u32 *)val) = in_le32(addr); 501 return 4; 502 } 503 return -EINVAL; 504} 505 506/* This provides legacy IO write access on a bus */ 507int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 508{ 509 unsigned long offset; 510 struct pci_controller *hose = pci_bus_to_host(bus); 511 struct resource *rp = &hose->io_resource; 512 void __iomem *addr; 513 514 /* Check if port can be supported by that bus. We only check 515 * the ranges of the PHB though, not the bus itself as the rules 516 * for forwarding legacy cycles down bridges are not our problem 517 * here. So if the host bridge supports it, we do it. 518 */ 519 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 520 offset += port; 521 522 if (!(rp->flags & IORESOURCE_IO)) 523 return -ENXIO; 524 if (offset < rp->start || (offset + size) > rp->end) 525 return -ENXIO; 526 addr = hose->io_base_virt + port; 527 528 /* WARNING: The generic code is idiotic. It gets passed a pointer 529 * to what can be a 1, 2 or 4 byte quantity and always reads that 530 * as a u32, which means that we have to correct the location of 531 * the data read within those 32 bits for size 1 and 2 532 */ 533 switch(size) { 534 case 1: 535 out_8(addr, val >> 24); 536 return 1; 537 case 2: 538 if (port & 1) 539 return -EINVAL; 540 out_le16(addr, val >> 16); 541 return 2; 542 case 4: 543 if (port & 3) 544 return -EINVAL; 545 out_le32(addr, val); 546 return 4; 547 } 548 return -EINVAL; 549} 550 551/* This provides legacy IO or memory mmap access on a bus */ 552int pci_mmap_legacy_page_range(struct pci_bus *bus, 553 struct vm_area_struct *vma, 554 enum pci_mmap_state mmap_state) 555{ 556 struct pci_controller *hose = pci_bus_to_host(bus); 557 resource_size_t offset = 558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 559 resource_size_t size = vma->vm_end - vma->vm_start; 560 struct resource *rp; 561 562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 563 pci_domain_nr(bus), bus->number, 564 mmap_state == pci_mmap_mem ? "MEM" : "IO", 565 (unsigned long long)offset, 566 (unsigned long long)(offset + size - 1)); 567 568 if (mmap_state == pci_mmap_mem) { 569 /* Hack alert ! 570 * 571 * Because X is lame and can fail starting if it gets an error trying 572 * to mmap legacy_mem (instead of just moving on without legacy memory 573 * access) we fake it here by giving it anonymous memory, effectively 574 * behaving just like /dev/zero 575 */ 576 if ((offset + size) > hose->isa_mem_size) { 577 printk(KERN_DEBUG 578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 579 current->comm, current->pid, pci_domain_nr(bus), bus->number); 580 if (vma->vm_flags & VM_SHARED) 581 return shmem_zero_setup(vma); 582 return 0; 583 } 584 offset += hose->isa_mem_phys; 585 } else { 586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 587 unsigned long roffset = offset + io_offset; 588 rp = &hose->io_resource; 589 if (!(rp->flags & IORESOURCE_IO)) 590 return -ENXIO; 591 if (roffset < rp->start || (roffset + size) > rp->end) 592 return -ENXIO; 593 offset += hose->io_base_phys; 594 } 595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 596 597 vma->vm_pgoff = offset >> PAGE_SHIFT; 598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 600 vma->vm_end - vma->vm_start, 601 vma->vm_page_prot); 602} 603 604void pci_resource_to_user(const struct pci_dev *dev, int bar, 605 const struct resource *rsrc, 606 resource_size_t *start, resource_size_t *end) 607{ 608 struct pci_controller *hose = pci_bus_to_host(dev->bus); 609 resource_size_t offset = 0; 610 611 if (hose == NULL) 612 return; 613 614 if (rsrc->flags & IORESOURCE_IO) 615 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 616 617 /* We pass a fully fixed up address to userland for MMIO instead of 618 * a BAR value because X is lame and expects to be able to use that 619 * to pass to /dev/mem ! 620 * 621 * That means that we'll have potentially 64 bits values where some 622 * userland apps only expect 32 (like X itself since it thinks only 623 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 624 * 32 bits CHRPs :-( 625 * 626 * Hopefully, the sysfs insterface is immune to that gunk. Once X 627 * has been fixed (and the fix spread enough), we can re-enable the 628 * 2 lines below and pass down a BAR value to userland. In that case 629 * we'll also have to re-enable the matching code in 630 * __pci_mmap_make_offset(). 631 * 632 * BenH. 633 */ 634#if 0 635 else if (rsrc->flags & IORESOURCE_MEM) 636 offset = hose->pci_mem_offset; 637#endif 638 639 *start = rsrc->start - offset; 640 *end = rsrc->end - offset; 641} 642 643/** 644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 645 * @hose: newly allocated pci_controller to be setup 646 * @dev: device node of the host bridge 647 * @primary: set if primary bus (32 bits only, soon to be deprecated) 648 * 649 * This function will parse the "ranges" property of a PCI host bridge device 650 * node and setup the resource mapping of a pci controller based on its 651 * content. 652 * 653 * Life would be boring if it wasn't for a few issues that we have to deal 654 * with here: 655 * 656 * - We can only cope with one IO space range and up to 3 Memory space 657 * ranges. However, some machines (thanks Apple !) tend to split their 658 * space into lots of small contiguous ranges. So we have to coalesce. 659 * 660 * - We can only cope with all memory ranges having the same offset 661 * between CPU addresses and PCI addresses. Unfortunately, some bridges 662 * are setup for a large 1:1 mapping along with a small "window" which 663 * maps PCI address 0 to some arbitrary high address of the CPU space in 664 * order to give access to the ISA memory hole. 665 * The way out of here that I've chosen for now is to always set the 666 * offset based on the first resource found, then override it if we 667 * have a different offset and the previous was set by an ISA hole. 668 * 669 * - Some busses have IO space not starting at 0, which causes trouble with 670 * the way we do our IO resource renumbering. The code somewhat deals with 671 * it for 64 bits but I would expect problems on 32 bits. 672 * 673 * - Some 32 bits platforms such as 4xx can have physical space larger than 674 * 32 bits so we need to use 64 bits values for the parsing 675 */ 676void pci_process_bridge_OF_ranges(struct pci_controller *hose, 677 struct device_node *dev, int primary) 678{ 679 const u32 *ranges; 680 int rlen; 681 int pna = of_n_addr_cells(dev); 682 int np = pna + 5; 683 int memno = 0, isa_hole = -1; 684 u32 pci_space; 685 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; 686 unsigned long long isa_mb = 0; 687 struct resource *res; 688 689 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 690 dev->full_name, primary ? "(primary)" : ""); 691 692 /* Get ranges property */ 693 ranges = of_get_property(dev, "ranges", &rlen); 694 if (ranges == NULL) 695 return; 696 697 /* Parse it */ 698 while ((rlen -= np * 4) >= 0) { 699 /* Read next ranges element */ 700 pci_space = ranges[0]; 701 pci_addr = of_read_number(ranges + 1, 2); 702 cpu_addr = of_translate_address(dev, ranges + 3); 703 size = of_read_number(ranges + pna + 3, 2); 704 ranges += np; 705 706 /* If we failed translation or got a zero-sized region 707 * (some FW try to feed us with non sensical zero sized regions 708 * such as power3 which look like some kind of attempt at exposing 709 * the VGA memory hole) 710 */ 711 if (cpu_addr == OF_BAD_ADDR || size == 0) 712 continue; 713 714 /* Now consume following elements while they are contiguous */ 715 for (; rlen >= np * sizeof(u32); 716 ranges += np, rlen -= np * 4) { 717 if (ranges[0] != pci_space) 718 break; 719 pci_next = of_read_number(ranges + 1, 2); 720 cpu_next = of_translate_address(dev, ranges + 3); 721 if (pci_next != pci_addr + size || 722 cpu_next != cpu_addr + size) 723 break; 724 size += of_read_number(ranges + pna + 3, 2); 725 } 726 727 /* Act based on address space type */ 728 res = NULL; 729 switch ((pci_space >> 24) & 0x3) { 730 case 1: /* PCI IO space */ 731 printk(KERN_INFO 732 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 733 cpu_addr, cpu_addr + size - 1, pci_addr); 734 735 /* We support only one IO range */ 736 if (hose->pci_io_size) { 737 printk(KERN_INFO 738 " \\--> Skipped (too many) !\n"); 739 continue; 740 } 741#ifdef CONFIG_PPC32 742 /* On 32 bits, limit I/O space to 16MB */ 743 if (size > 0x01000000) 744 size = 0x01000000; 745 746 /* 32 bits needs to map IOs here */ 747 hose->io_base_virt = ioremap(cpu_addr, size); 748 749 /* Expect trouble if pci_addr is not 0 */ 750 if (primary) 751 isa_io_base = 752 (unsigned long)hose->io_base_virt; 753#endif /* CONFIG_PPC32 */ 754 /* pci_io_size and io_base_phys always represent IO 755 * space starting at 0 so we factor in pci_addr 756 */ 757 hose->pci_io_size = pci_addr + size; 758 hose->io_base_phys = cpu_addr - pci_addr; 759 760 /* Build resource */ 761 res = &hose->io_resource; 762 res->flags = IORESOURCE_IO; 763 res->start = pci_addr; 764 break; 765 case 2: /* PCI Memory space */ 766 case 3: /* PCI 64 bits Memory space */ 767 printk(KERN_INFO 768 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 769 cpu_addr, cpu_addr + size - 1, pci_addr, 770 (pci_space & 0x40000000) ? "Prefetch" : ""); 771 772 /* We support only 3 memory ranges */ 773 if (memno >= 3) { 774 printk(KERN_INFO 775 " \\--> Skipped (too many) !\n"); 776 continue; 777 } 778 /* Handles ISA memory hole space here */ 779 if (pci_addr == 0) { 780 isa_mb = cpu_addr; 781 isa_hole = memno; 782 if (primary || isa_mem_base == 0) 783 isa_mem_base = cpu_addr; 784 hose->isa_mem_phys = cpu_addr; 785 hose->isa_mem_size = size; 786 } 787 788 /* We get the PCI/Mem offset from the first range or 789 * the, current one if the offset came from an ISA 790 * hole. If they don't match, bugger. 791 */ 792 if (memno == 0 || 793 (isa_hole >= 0 && pci_addr != 0 && 794 hose->pci_mem_offset == isa_mb)) 795 hose->pci_mem_offset = cpu_addr - pci_addr; 796 else if (pci_addr != 0 && 797 hose->pci_mem_offset != cpu_addr - pci_addr) { 798 printk(KERN_INFO 799 " \\--> Skipped (offset mismatch) !\n"); 800 continue; 801 } 802 803 /* Build resource */ 804 res = &hose->mem_resources[memno++]; 805 res->flags = IORESOURCE_MEM; 806 if (pci_space & 0x40000000) 807 res->flags |= IORESOURCE_PREFETCH; 808 res->start = cpu_addr; 809 break; 810 } 811 if (res != NULL) { 812 res->name = dev->full_name; 813 res->end = res->start + size - 1; 814 res->parent = NULL; 815 res->sibling = NULL; 816 res->child = NULL; 817 } 818 } 819 820 /* If there's an ISA hole and the pci_mem_offset is -not- matching 821 * the ISA hole offset, then we need to remove the ISA hole from 822 * the resource list for that brige 823 */ 824 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { 825 unsigned int next = isa_hole + 1; 826 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); 827 if (next < memno) 828 memmove(&hose->mem_resources[isa_hole], 829 &hose->mem_resources[next], 830 sizeof(struct resource) * (memno - next)); 831 hose->mem_resources[--memno].flags = 0; 832 } 833} 834 835/* Decide whether to display the domain number in /proc */ 836int pci_proc_domain(struct pci_bus *bus) 837{ 838 struct pci_controller *hose = pci_bus_to_host(bus); 839 840 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 841 return 0; 842 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 843 return hose->global_number != 0; 844 return 1; 845} 846 847/* This header fixup will do the resource fixup for all devices as they are 848 * probed, but not for bridge ranges 849 */ 850static void pcibios_fixup_resources(struct pci_dev *dev) 851{ 852 struct pci_controller *hose = pci_bus_to_host(dev->bus); 853 int i; 854 855 if (!hose) { 856 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 857 pci_name(dev)); 858 return; 859 } 860 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 861 struct resource *res = dev->resource + i; 862 if (!res->flags) 863 continue; 864 865 /* If we're going to re-assign everything, we mark all resources 866 * as unset (and 0-base them). In addition, we mark BARs starting 867 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 868 * since in that case, we don't want to re-assign anything 869 */ 870 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 871 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 872 /* Only print message if not re-assigning */ 873 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 874 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 875 "is unassigned\n", 876 pci_name(dev), i, 877 (unsigned long long)res->start, 878 (unsigned long long)res->end, 879 (unsigned int)res->flags); 880 res->end -= res->start; 881 res->start = 0; 882 res->flags |= IORESOURCE_UNSET; 883 continue; 884 } 885 886 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 887 pci_name(dev), i, 888 (unsigned long long)res->start,\ 889 (unsigned long long)res->end, 890 (unsigned int)res->flags); 891 } 892 893 /* Call machine specific resource fixup */ 894 if (ppc_md.pcibios_fixup_resources) 895 ppc_md.pcibios_fixup_resources(dev); 896} 897DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 898 899/* This function tries to figure out if a bridge resource has been initialized 900 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 901 * things go more smoothly when it gets it right. It should covers cases such 902 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 903 */ 904static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 905 struct resource *res) 906{ 907 struct pci_controller *hose = pci_bus_to_host(bus); 908 struct pci_dev *dev = bus->self; 909 resource_size_t offset; 910 u16 command; 911 int i; 912 913 /* We don't do anything if PCI_PROBE_ONLY is set */ 914 if (pci_has_flag(PCI_PROBE_ONLY)) 915 return 0; 916 917 /* Job is a bit different between memory and IO */ 918 if (res->flags & IORESOURCE_MEM) { 919 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been 920 * initialized by somebody 921 */ 922 if (res->start != hose->pci_mem_offset) 923 return 0; 924 925 /* The BAR is 0, let's check if memory decoding is enabled on 926 * the bridge. If not, we consider it unassigned 927 */ 928 pci_read_config_word(dev, PCI_COMMAND, &command); 929 if ((command & PCI_COMMAND_MEMORY) == 0) 930 return 1; 931 932 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 933 * resources covers that starting address (0 then it's good enough for 934 * us for memory 935 */ 936 for (i = 0; i < 3; i++) { 937 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 938 hose->mem_resources[i].start == hose->pci_mem_offset) 939 return 0; 940 } 941 942 /* Well, it starts at 0 and we know it will collide so we may as 943 * well consider it as unassigned. That covers the Apple case. 944 */ 945 return 1; 946 } else { 947 /* If the BAR is non-0, then we consider it assigned */ 948 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 949 if (((res->start - offset) & 0xfffffffful) != 0) 950 return 0; 951 952 /* Here, we are a bit different than memory as typically IO space 953 * starting at low addresses -is- valid. What we do instead if that 954 * we consider as unassigned anything that doesn't have IO enabled 955 * in the PCI command register, and that's it. 956 */ 957 pci_read_config_word(dev, PCI_COMMAND, &command); 958 if (command & PCI_COMMAND_IO) 959 return 0; 960 961 /* It's starting at 0 and IO is disabled in the bridge, consider 962 * it unassigned 963 */ 964 return 1; 965 } 966} 967 968/* Fixup resources of a PCI<->PCI bridge */ 969static void pcibios_fixup_bridge(struct pci_bus *bus) 970{ 971 struct resource *res; 972 int i; 973 974 struct pci_dev *dev = bus->self; 975 976 pci_bus_for_each_resource(bus, res, i) { 977 if (!res || !res->flags) 978 continue; 979 if (i >= 3 && bus->self->transparent) 980 continue; 981 982 /* If we're going to reassign everything, we can 983 * shrink the P2P resource to have size as being 984 * of 0 in order to save space. 985 */ 986 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 987 res->flags |= IORESOURCE_UNSET; 988 res->start = 0; 989 res->end = -1; 990 continue; 991 } 992 993 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 994 pci_name(dev), i, 995 (unsigned long long)res->start,\ 996 (unsigned long long)res->end, 997 (unsigned int)res->flags); 998 999 /* Try to detect uninitialized P2P bridge resources, 1000 * and clear them out so they get re-assigned later 1001 */ 1002 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1003 res->flags = 0; 1004 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1005 } 1006 } 1007} 1008 1009void pcibios_setup_bus_self(struct pci_bus *bus) 1010{ 1011 /* Fix up the bus resources for P2P bridges */ 1012 if (bus->self != NULL) 1013 pcibios_fixup_bridge(bus); 1014 1015 /* Platform specific bus fixups. This is currently only used 1016 * by fsl_pci and I'm hoping to get rid of it at some point 1017 */ 1018 if (ppc_md.pcibios_fixup_bus) 1019 ppc_md.pcibios_fixup_bus(bus); 1020 1021 /* Setup bus DMA mappings */ 1022 if (ppc_md.pci_dma_bus_setup) 1023 ppc_md.pci_dma_bus_setup(bus); 1024} 1025 1026void pcibios_setup_bus_devices(struct pci_bus *bus) 1027{ 1028 struct pci_dev *dev; 1029 1030 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1031 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1032 1033 list_for_each_entry(dev, &bus->devices, bus_list) { 1034 /* Cardbus can call us to add new devices to a bus, so ignore 1035 * those who are already fully discovered 1036 */ 1037 if (dev->is_added) 1038 continue; 1039 1040 /* Fixup NUMA node as it may not be setup yet by the generic 1041 * code and is needed by the DMA init 1042 */ 1043 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1044 1045 /* Hook up default DMA ops */ 1046 set_dma_ops(&dev->dev, pci_dma_ops); 1047 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 1048 1049 /* Additional platform DMA/iommu setup */ 1050 if (ppc_md.pci_dma_dev_setup) 1051 ppc_md.pci_dma_dev_setup(dev); 1052 1053 /* Read default IRQs and fixup if necessary */ 1054 pci_read_irq_line(dev); 1055 if (ppc_md.pci_irq_fixup) 1056 ppc_md.pci_irq_fixup(dev); 1057 } 1058} 1059 1060void pcibios_set_master(struct pci_dev *dev) 1061{ 1062 /* No special bus mastering setup handling */ 1063} 1064 1065void pcibios_fixup_bus(struct pci_bus *bus) 1066{ 1067 /* When called from the generic PCI probe, read PCI<->PCI bridge 1068 * bases. This is -not- called when generating the PCI tree from 1069 * the OF device-tree. 1070 */ 1071 if (bus->self != NULL) 1072 pci_read_bridge_bases(bus); 1073 1074 /* Now fixup the bus bus */ 1075 pcibios_setup_bus_self(bus); 1076 1077 /* Now fixup devices on that bus */ 1078 pcibios_setup_bus_devices(bus); 1079} 1080EXPORT_SYMBOL(pcibios_fixup_bus); 1081 1082void pci_fixup_cardbus(struct pci_bus *bus) 1083{ 1084 /* Now fixup devices on that bus */ 1085 pcibios_setup_bus_devices(bus); 1086} 1087 1088 1089static int skip_isa_ioresource_align(struct pci_dev *dev) 1090{ 1091 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1092 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1093 return 1; 1094 return 0; 1095} 1096 1097/* 1098 * We need to avoid collisions with `mirrored' VGA ports 1099 * and other strange ISA hardware, so we always want the 1100 * addresses to be allocated in the 0x000-0x0ff region 1101 * modulo 0x400. 1102 * 1103 * Why? Because some silly external IO cards only decode 1104 * the low 10 bits of the IO address. The 0x00-0xff region 1105 * is reserved for motherboard devices that decode all 16 1106 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1107 * but we want to try to avoid allocating at 0x2900-0x2bff 1108 * which might have be mirrored at 0x0100-0x03ff.. 1109 */ 1110resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1111 resource_size_t size, resource_size_t align) 1112{ 1113 struct pci_dev *dev = data; 1114 resource_size_t start = res->start; 1115 1116 if (res->flags & IORESOURCE_IO) { 1117 if (skip_isa_ioresource_align(dev)) 1118 return start; 1119 if (start & 0x300) 1120 start = (start + 0x3ff) & ~0x3ff; 1121 } 1122 1123 return start; 1124} 1125EXPORT_SYMBOL(pcibios_align_resource); 1126 1127/* 1128 * Reparent resource children of pr that conflict with res 1129 * under res, and make res replace those children. 1130 */ 1131static int reparent_resources(struct resource *parent, 1132 struct resource *res) 1133{ 1134 struct resource *p, **pp; 1135 struct resource **firstpp = NULL; 1136 1137 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1138 if (p->end < res->start) 1139 continue; 1140 if (res->end < p->start) 1141 break; 1142 if (p->start < res->start || p->end > res->end) 1143 return -1; /* not completely contained */ 1144 if (firstpp == NULL) 1145 firstpp = pp; 1146 } 1147 if (firstpp == NULL) 1148 return -1; /* didn't find any conflicting entries? */ 1149 res->parent = parent; 1150 res->child = *firstpp; 1151 res->sibling = *pp; 1152 *firstpp = res; 1153 *pp = NULL; 1154 for (p = res->child; p != NULL; p = p->sibling) { 1155 p->parent = res; 1156 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1157 p->name, 1158 (unsigned long long)p->start, 1159 (unsigned long long)p->end, res->name); 1160 } 1161 return 0; 1162} 1163 1164/* 1165 * Handle resources of PCI devices. If the world were perfect, we could 1166 * just allocate all the resource regions and do nothing more. It isn't. 1167 * On the other hand, we cannot just re-allocate all devices, as it would 1168 * require us to know lots of host bridge internals. So we attempt to 1169 * keep as much of the original configuration as possible, but tweak it 1170 * when it's found to be wrong. 1171 * 1172 * Known BIOS problems we have to work around: 1173 * - I/O or memory regions not configured 1174 * - regions configured, but not enabled in the command register 1175 * - bogus I/O addresses above 64K used 1176 * - expansion ROMs left enabled (this may sound harmless, but given 1177 * the fact the PCI specs explicitly allow address decoders to be 1178 * shared between expansion ROMs and other resource regions, it's 1179 * at least dangerous) 1180 * 1181 * Our solution: 1182 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1183 * This gives us fixed barriers on where we can allocate. 1184 * (2) Allocate resources for all enabled devices. If there is 1185 * a collision, just mark the resource as unallocated. Also 1186 * disable expansion ROMs during this step. 1187 * (3) Try to allocate resources for disabled devices. If the 1188 * resources were assigned correctly, everything goes well, 1189 * if they weren't, they won't disturb allocation of other 1190 * resources. 1191 * (4) Assign new addresses to resources which were either 1192 * not configured at all or misconfigured. If explicitly 1193 * requested by the user, configure expansion ROM address 1194 * as well. 1195 */ 1196 1197void pcibios_allocate_bus_resources(struct pci_bus *bus) 1198{ 1199 struct pci_bus *b; 1200 int i; 1201 struct resource *res, *pr; 1202 1203 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1204 pci_domain_nr(bus), bus->number); 1205 1206 pci_bus_for_each_resource(bus, res, i) { 1207 if (!res || !res->flags || res->start > res->end || res->parent) 1208 continue; 1209 1210 /* If the resource was left unset at this point, we clear it */ 1211 if (res->flags & IORESOURCE_UNSET) 1212 goto clear_resource; 1213 1214 if (bus->parent == NULL) 1215 pr = (res->flags & IORESOURCE_IO) ? 1216 &ioport_resource : &iomem_resource; 1217 else { 1218 pr = pci_find_parent_resource(bus->self, res); 1219 if (pr == res) { 1220 /* this happens when the generic PCI 1221 * code (wrongly) decides that this 1222 * bridge is transparent -- paulus 1223 */ 1224 continue; 1225 } 1226 } 1227 1228 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1229 "[0x%x], parent %p (%s)\n", 1230 bus->self ? pci_name(bus->self) : "PHB", 1231 bus->number, i, 1232 (unsigned long long)res->start, 1233 (unsigned long long)res->end, 1234 (unsigned int)res->flags, 1235 pr, (pr && pr->name) ? pr->name : "nil"); 1236 1237 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1238 if (request_resource(pr, res) == 0) 1239 continue; 1240 /* 1241 * Must be a conflict with an existing entry. 1242 * Move that entry (or entries) under the 1243 * bridge resource and try again. 1244 */ 1245 if (reparent_resources(pr, res) == 0) 1246 continue; 1247 } 1248 pr_warning("PCI: Cannot allocate resource region " 1249 "%d of PCI bridge %d, will remap\n", i, bus->number); 1250 clear_resource: 1251 /* The resource might be figured out when doing 1252 * reassignment based on the resources required 1253 * by the downstream PCI devices. Here we set 1254 * the size of the resource to be 0 in order to 1255 * save more space. 1256 */ 1257 res->start = 0; 1258 res->end = -1; 1259 res->flags = 0; 1260 } 1261 1262 list_for_each_entry(b, &bus->children, node) 1263 pcibios_allocate_bus_resources(b); 1264} 1265 1266static inline void alloc_resource(struct pci_dev *dev, int idx) 1267{ 1268 struct resource *pr, *r = &dev->resource[idx]; 1269 1270 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1271 pci_name(dev), idx, 1272 (unsigned long long)r->start, 1273 (unsigned long long)r->end, 1274 (unsigned int)r->flags); 1275 1276 pr = pci_find_parent_resource(dev, r); 1277 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1278 request_resource(pr, r) < 0) { 1279 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1280 " of device %s, will remap\n", idx, pci_name(dev)); 1281 if (pr) 1282 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1283 pr, 1284 (unsigned long long)pr->start, 1285 (unsigned long long)pr->end, 1286 (unsigned int)pr->flags); 1287 /* We'll assign a new address later */ 1288 r->flags |= IORESOURCE_UNSET; 1289 r->end -= r->start; 1290 r->start = 0; 1291 } 1292} 1293 1294static void __init pcibios_allocate_resources(int pass) 1295{ 1296 struct pci_dev *dev = NULL; 1297 int idx, disabled; 1298 u16 command; 1299 struct resource *r; 1300 1301 for_each_pci_dev(dev) { 1302 pci_read_config_word(dev, PCI_COMMAND, &command); 1303 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1304 r = &dev->resource[idx]; 1305 if (r->parent) /* Already allocated */ 1306 continue; 1307 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1308 continue; /* Not assigned at all */ 1309 /* We only allocate ROMs on pass 1 just in case they 1310 * have been screwed up by firmware 1311 */ 1312 if (idx == PCI_ROM_RESOURCE ) 1313 disabled = 1; 1314 if (r->flags & IORESOURCE_IO) 1315 disabled = !(command & PCI_COMMAND_IO); 1316 else 1317 disabled = !(command & PCI_COMMAND_MEMORY); 1318 if (pass == disabled) 1319 alloc_resource(dev, idx); 1320 } 1321 if (pass) 1322 continue; 1323 r = &dev->resource[PCI_ROM_RESOURCE]; 1324 if (r->flags) { 1325 /* Turn the ROM off, leave the resource region, 1326 * but keep it unregistered. 1327 */ 1328 u32 reg; 1329 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1330 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1331 pr_debug("PCI: Switching off ROM of %s\n", 1332 pci_name(dev)); 1333 r->flags &= ~IORESOURCE_ROM_ENABLE; 1334 pci_write_config_dword(dev, dev->rom_base_reg, 1335 reg & ~PCI_ROM_ADDRESS_ENABLE); 1336 } 1337 } 1338 } 1339} 1340 1341static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1342{ 1343 struct pci_controller *hose = pci_bus_to_host(bus); 1344 resource_size_t offset; 1345 struct resource *res, *pres; 1346 int i; 1347 1348 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1349 1350 /* Check for IO */ 1351 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1352 goto no_io; 1353 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1354 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1355 BUG_ON(res == NULL); 1356 res->name = "Legacy IO"; 1357 res->flags = IORESOURCE_IO; 1358 res->start = offset; 1359 res->end = (offset + 0xfff) & 0xfffffffful; 1360 pr_debug("Candidate legacy IO: %pR\n", res); 1361 if (request_resource(&hose->io_resource, res)) { 1362 printk(KERN_DEBUG 1363 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1364 pci_domain_nr(bus), bus->number, res); 1365 kfree(res); 1366 } 1367 1368 no_io: 1369 /* Check for memory */ 1370 offset = hose->pci_mem_offset; 1371 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); 1372 for (i = 0; i < 3; i++) { 1373 pres = &hose->mem_resources[i]; 1374 if (!(pres->flags & IORESOURCE_MEM)) 1375 continue; 1376 pr_debug("hose mem res: %pR\n", pres); 1377 if ((pres->start - offset) <= 0xa0000 && 1378 (pres->end - offset) >= 0xbffff) 1379 break; 1380 } 1381 if (i >= 3) 1382 return; 1383 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1384 BUG_ON(res == NULL); 1385 res->name = "Legacy VGA memory"; 1386 res->flags = IORESOURCE_MEM; 1387 res->start = 0xa0000 + offset; 1388 res->end = 0xbffff + offset; 1389 pr_debug("Candidate VGA memory: %pR\n", res); 1390 if (request_resource(pres, res)) { 1391 printk(KERN_DEBUG 1392 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1393 pci_domain_nr(bus), bus->number, res); 1394 kfree(res); 1395 } 1396} 1397 1398void __init pcibios_resource_survey(void) 1399{ 1400 struct pci_bus *b; 1401 1402 /* Allocate and assign resources */ 1403 list_for_each_entry(b, &pci_root_buses, node) 1404 pcibios_allocate_bus_resources(b); 1405 pcibios_allocate_resources(0); 1406 pcibios_allocate_resources(1); 1407 1408 /* Before we start assigning unassigned resource, we try to reserve 1409 * the low IO area and the VGA memory area if they intersect the 1410 * bus available resources to avoid allocating things on top of them 1411 */ 1412 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1413 list_for_each_entry(b, &pci_root_buses, node) 1414 pcibios_reserve_legacy_regions(b); 1415 } 1416 1417 /* Now, if the platform didn't decide to blindly trust the firmware, 1418 * we proceed to assigning things that were left unassigned 1419 */ 1420 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1421 pr_debug("PCI: Assigning unassigned resources...\n"); 1422 pci_assign_unassigned_resources(); 1423 } 1424 1425 /* Call machine dependent fixup */ 1426 if (ppc_md.pcibios_fixup) 1427 ppc_md.pcibios_fixup(); 1428} 1429 1430/* This is used by the PCI hotplug driver to allocate resource 1431 * of newly plugged busses. We can try to consolidate with the 1432 * rest of the code later, for now, keep it as-is as our main 1433 * resource allocation function doesn't deal with sub-trees yet. 1434 */ 1435void pcibios_claim_one_bus(struct pci_bus *bus) 1436{ 1437 struct pci_dev *dev; 1438 struct pci_bus *child_bus; 1439 1440 list_for_each_entry(dev, &bus->devices, bus_list) { 1441 int i; 1442 1443 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1444 struct resource *r = &dev->resource[i]; 1445 1446 if (r->parent || !r->start || !r->flags) 1447 continue; 1448 1449 pr_debug("PCI: Claiming %s: " 1450 "Resource %d: %016llx..%016llx [%x]\n", 1451 pci_name(dev), i, 1452 (unsigned long long)r->start, 1453 (unsigned long long)r->end, 1454 (unsigned int)r->flags); 1455 1456 pci_claim_resource(dev, i); 1457 } 1458 } 1459 1460 list_for_each_entry(child_bus, &bus->children, node) 1461 pcibios_claim_one_bus(child_bus); 1462} 1463 1464 1465/* pcibios_finish_adding_to_bus 1466 * 1467 * This is to be called by the hotplug code after devices have been 1468 * added to a bus, this include calling it for a PHB that is just 1469 * being added 1470 */ 1471void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1472{ 1473 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1474 pci_domain_nr(bus), bus->number); 1475 1476 /* Allocate bus and devices resources */ 1477 pcibios_allocate_bus_resources(bus); 1478 pcibios_claim_one_bus(bus); 1479 1480 /* Fixup EEH */ 1481 eeh_add_device_tree_late(bus); 1482 1483 /* Add new devices to global lists. Register in proc, sysfs. */ 1484 pci_bus_add_devices(bus); 1485 1486 /* sysfs files should only be added after devices are added */ 1487 eeh_add_sysfs_files(bus); 1488} 1489EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1490 1491int pcibios_enable_device(struct pci_dev *dev, int mask) 1492{ 1493 if (ppc_md.pcibios_enable_device_hook) 1494 if (ppc_md.pcibios_enable_device_hook(dev)) 1495 return -EINVAL; 1496 1497 return pci_enable_resources(dev, mask); 1498} 1499 1500resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1501{ 1502 return (unsigned long) hose->io_base_virt - _IO_BASE; 1503} 1504 1505static void pcibios_setup_phb_resources(struct pci_controller *hose, 1506 struct list_head *resources) 1507{ 1508 struct resource *res; 1509 int i; 1510 1511 /* Hookup PHB IO resource */ 1512 res = &hose->io_resource; 1513 1514 if (!res->flags) { 1515 printk(KERN_WARNING "PCI: I/O resource not set for host" 1516 " bridge %s (domain %d)\n", 1517 hose->dn->full_name, hose->global_number); 1518#ifdef CONFIG_PPC32 1519 /* Workaround for lack of IO resource only on 32-bit */ 1520 res->start = (unsigned long)hose->io_base_virt - isa_io_base; 1521 res->end = res->start + IO_SPACE_LIMIT; 1522 res->flags = IORESOURCE_IO; 1523#endif /* CONFIG_PPC32 */ 1524 } 1525 1526 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", 1527 (unsigned long long)res->start, 1528 (unsigned long long)res->end, 1529 (unsigned long)res->flags); 1530 pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose)); 1531 1532 /* Hookup PHB Memory resources */ 1533 for (i = 0; i < 3; ++i) { 1534 res = &hose->mem_resources[i]; 1535 if (!res->flags) { 1536 if (i > 0) 1537 continue; 1538 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1539 "host bridge %s (domain %d)\n", 1540 hose->dn->full_name, hose->global_number); 1541#ifdef CONFIG_PPC32 1542 /* Workaround for lack of MEM resource only on 32-bit */ 1543 res->start = hose->pci_mem_offset; 1544 res->end = (resource_size_t)-1LL; 1545 res->flags = IORESOURCE_MEM; 1546#endif /* CONFIG_PPC32 */ 1547 } 1548 1549 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i, 1550 (unsigned long long)res->start, 1551 (unsigned long long)res->end, 1552 (unsigned long)res->flags); 1553 pci_add_resource_offset(resources, res, hose->pci_mem_offset); 1554 } 1555 1556 pr_debug("PCI: PHB MEM offset = %016llx\n", 1557 (unsigned long long)hose->pci_mem_offset); 1558 pr_debug("PCI: PHB IO offset = %08lx\n", 1559 (unsigned long)hose->io_base_virt - _IO_BASE); 1560 1561} 1562 1563/* 1564 * Null PCI config access functions, for the case when we can't 1565 * find a hose. 1566 */ 1567#define NULL_PCI_OP(rw, size, type) \ 1568static int \ 1569null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1570{ \ 1571 return PCIBIOS_DEVICE_NOT_FOUND; \ 1572} 1573 1574static int 1575null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1576 int len, u32 *val) 1577{ 1578 return PCIBIOS_DEVICE_NOT_FOUND; 1579} 1580 1581static int 1582null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1583 int len, u32 val) 1584{ 1585 return PCIBIOS_DEVICE_NOT_FOUND; 1586} 1587 1588static struct pci_ops null_pci_ops = 1589{ 1590 .read = null_read_config, 1591 .write = null_write_config, 1592}; 1593 1594/* 1595 * These functions are used early on before PCI scanning is done 1596 * and all of the pci_dev and pci_bus structures have been created. 1597 */ 1598static struct pci_bus * 1599fake_pci_bus(struct pci_controller *hose, int busnr) 1600{ 1601 static struct pci_bus bus; 1602 1603 if (hose == 0) { 1604 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1605 } 1606 bus.number = busnr; 1607 bus.sysdata = hose; 1608 bus.ops = hose? hose->ops: &null_pci_ops; 1609 return &bus; 1610} 1611 1612#define EARLY_PCI_OP(rw, size, type) \ 1613int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1614 int devfn, int offset, type value) \ 1615{ \ 1616 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1617 devfn, offset, value); \ 1618} 1619 1620EARLY_PCI_OP(read, byte, u8 *) 1621EARLY_PCI_OP(read, word, u16 *) 1622EARLY_PCI_OP(read, dword, u32 *) 1623EARLY_PCI_OP(write, byte, u8) 1624EARLY_PCI_OP(write, word, u16) 1625EARLY_PCI_OP(write, dword, u32) 1626 1627extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); 1628int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1629 int cap) 1630{ 1631 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1632} 1633 1634struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1635{ 1636 struct pci_controller *hose = bus->sysdata; 1637 1638 return of_node_get(hose->dn); 1639} 1640 1641/** 1642 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1643 * @hose: Pointer to the PCI host controller instance structure 1644 */ 1645void pcibios_scan_phb(struct pci_controller *hose) 1646{ 1647 LIST_HEAD(resources); 1648 struct pci_bus *bus; 1649 struct device_node *node = hose->dn; 1650 int mode; 1651 1652 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1653 1654 /* Get some IO space for the new PHB */ 1655 pcibios_setup_phb_io_space(hose); 1656 1657 /* Wire up PHB bus resources */ 1658 pcibios_setup_phb_resources(hose, &resources); 1659 1660 hose->busn.start = hose->first_busno; 1661 hose->busn.end = hose->last_busno; 1662 hose->busn.flags = IORESOURCE_BUS; 1663 pci_add_resource(&resources, &hose->busn); 1664 1665 /* Create an empty bus for the toplevel */ 1666 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1667 hose->ops, hose, &resources); 1668 if (bus == NULL) { 1669 pr_err("Failed to create bus for PCI domain %04x\n", 1670 hose->global_number); 1671 pci_free_resource_list(&resources); 1672 return; 1673 } 1674 hose->bus = bus; 1675 1676 /* Get probe mode and perform scan */ 1677 mode = PCI_PROBE_NORMAL; 1678 if (node && ppc_md.pci_probe_mode) 1679 mode = ppc_md.pci_probe_mode(bus); 1680 pr_debug(" probe mode: %d\n", mode); 1681 if (mode == PCI_PROBE_DEVTREE) 1682 of_scan_bus(node, bus); 1683 1684 if (mode == PCI_PROBE_NORMAL) { 1685 pci_bus_update_busn_res_end(bus, 255); 1686 hose->last_busno = pci_scan_child_bus(bus); 1687 pci_bus_update_busn_res_end(bus, hose->last_busno); 1688 } 1689 1690 /* Platform gets a chance to do some global fixups before 1691 * we proceed to resource allocation 1692 */ 1693 if (ppc_md.pcibios_fixup_phb) 1694 ppc_md.pcibios_fixup_phb(hose); 1695 1696 /* Configure PCI Express settings */ 1697 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1698 struct pci_bus *child; 1699 list_for_each_entry(child, &bus->children, node) { 1700 struct pci_dev *self = child->self; 1701 if (!self) 1702 continue; 1703 pcie_bus_configure_settings(child, self->pcie_mpss); 1704 } 1705 } 1706} 1707 1708static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1709{ 1710 int i, class = dev->class >> 8; 1711 /* When configured as agent, programing interface = 1 */ 1712 int prog_if = dev->class & 0xf; 1713 1714 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1715 class == PCI_CLASS_BRIDGE_OTHER) && 1716 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1717 (prog_if == 0) && 1718 (dev->bus->parent == NULL)) { 1719 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1720 dev->resource[i].start = 0; 1721 dev->resource[i].end = 0; 1722 dev->resource[i].flags = 0; 1723 } 1724 } 1725} 1726DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1727DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1728