setup_64.c revision 160c73243350304c09e69cbcc4fa34ff89868b68
1/* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#define DEBUG 14 15#include <linux/export.h> 16#include <linux/string.h> 17#include <linux/sched.h> 18#include <linux/init.h> 19#include <linux/kernel.h> 20#include <linux/reboot.h> 21#include <linux/delay.h> 22#include <linux/initrd.h> 23#include <linux/seq_file.h> 24#include <linux/ioport.h> 25#include <linux/console.h> 26#include <linux/utsname.h> 27#include <linux/tty.h> 28#include <linux/root_dev.h> 29#include <linux/notifier.h> 30#include <linux/cpu.h> 31#include <linux/unistd.h> 32#include <linux/serial.h> 33#include <linux/serial_8250.h> 34#include <linux/bootmem.h> 35#include <linux/pci.h> 36#include <linux/lockdep.h> 37#include <linux/memblock.h> 38#include <linux/hugetlb.h> 39 40#include <asm/io.h> 41#include <asm/kdump.h> 42#include <asm/prom.h> 43#include <asm/processor.h> 44#include <asm/pgtable.h> 45#include <asm/smp.h> 46#include <asm/elf.h> 47#include <asm/machdep.h> 48#include <asm/paca.h> 49#include <asm/time.h> 50#include <asm/cputable.h> 51#include <asm/sections.h> 52#include <asm/btext.h> 53#include <asm/nvram.h> 54#include <asm/setup.h> 55#include <asm/rtas.h> 56#include <asm/iommu.h> 57#include <asm/serial.h> 58#include <asm/cache.h> 59#include <asm/page.h> 60#include <asm/mmu.h> 61#include <asm/firmware.h> 62#include <asm/xmon.h> 63#include <asm/udbg.h> 64#include <asm/kexec.h> 65#include <asm/mmu_context.h> 66#include <asm/code-patching.h> 67#include <asm/kvm_ppc.h> 68#include <asm/hugetlb.h> 69#include <asm/epapr_hcalls.h> 70 71#ifdef DEBUG 72#define DBG(fmt...) udbg_printf(fmt) 73#else 74#define DBG(fmt...) 75#endif 76 77int boot_cpuid = 0; 78int spinning_secondaries; 79u64 ppc64_pft_size; 80 81/* Pick defaults since we might want to patch instructions 82 * before we've read this from the device tree. 83 */ 84struct ppc64_caches ppc64_caches = { 85 .dline_size = 0x40, 86 .log_dline_size = 6, 87 .iline_size = 0x40, 88 .log_iline_size = 6 89}; 90EXPORT_SYMBOL_GPL(ppc64_caches); 91 92/* 93 * These are used in binfmt_elf.c to put aux entries on the stack 94 * for each elf executable being started. 95 */ 96int dcache_bsize; 97int icache_bsize; 98int ucache_bsize; 99 100#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 101static void setup_tlb_core_data(void) 102{ 103 int cpu; 104 105 for_each_possible_cpu(cpu) { 106 int first = cpu_first_thread_sibling(cpu); 107 108 paca[cpu].tcd_ptr = &paca[first].tcd; 109 110 /* 111 * If we have threads, we need either tlbsrx. 112 * or e6500 tablewalk mode, or else TLB handlers 113 * will be racy and could produce duplicate entries. 114 */ 115 if (smt_enabled_at_boot >= 2 && 116 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 117 book3e_htw_mode != PPC_HTW_E6500) { 118 /* Should we panic instead? */ 119 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", 120 __func__); 121 } 122 } 123} 124#else 125static void setup_tlb_core_data(void) 126{ 127} 128#endif 129 130#ifdef CONFIG_SMP 131 132static char *smt_enabled_cmdline; 133 134/* Look for ibm,smt-enabled OF option */ 135static void check_smt_enabled(void) 136{ 137 struct device_node *dn; 138 const char *smt_option; 139 140 /* Default to enabling all threads */ 141 smt_enabled_at_boot = threads_per_core; 142 143 /* Allow the command line to overrule the OF option */ 144 if (smt_enabled_cmdline) { 145 if (!strcmp(smt_enabled_cmdline, "on")) 146 smt_enabled_at_boot = threads_per_core; 147 else if (!strcmp(smt_enabled_cmdline, "off")) 148 smt_enabled_at_boot = 0; 149 else { 150 long smt; 151 int rc; 152 153 rc = strict_strtol(smt_enabled_cmdline, 10, &smt); 154 if (!rc) 155 smt_enabled_at_boot = 156 min(threads_per_core, (int)smt); 157 } 158 } else { 159 dn = of_find_node_by_path("/options"); 160 if (dn) { 161 smt_option = of_get_property(dn, "ibm,smt-enabled", 162 NULL); 163 164 if (smt_option) { 165 if (!strcmp(smt_option, "on")) 166 smt_enabled_at_boot = threads_per_core; 167 else if (!strcmp(smt_option, "off")) 168 smt_enabled_at_boot = 0; 169 } 170 171 of_node_put(dn); 172 } 173 } 174} 175 176/* Look for smt-enabled= cmdline option */ 177static int __init early_smt_enabled(char *p) 178{ 179 smt_enabled_cmdline = p; 180 return 0; 181} 182early_param("smt-enabled", early_smt_enabled); 183 184#else 185#define check_smt_enabled() 186#endif /* CONFIG_SMP */ 187 188/** Fix up paca fields required for the boot cpu */ 189static void fixup_boot_paca(void) 190{ 191 /* The boot cpu is started */ 192 get_paca()->cpu_start = 1; 193 /* Allow percpu accesses to work until we setup percpu data */ 194 get_paca()->data_offset = 0; 195} 196 197/* 198 * Early initialization entry point. This is called by head.S 199 * with MMU translation disabled. We rely on the "feature" of 200 * the CPU that ignores the top 2 bits of the address in real 201 * mode so we can access kernel globals normally provided we 202 * only toy with things in the RMO region. From here, we do 203 * some early parsing of the device-tree to setup out MEMBLOCK 204 * data structures, and allocate & initialize the hash table 205 * and segment tables so we can start running with translation 206 * enabled. 207 * 208 * It is this function which will call the probe() callback of 209 * the various platform types and copy the matching one to the 210 * global ppc_md structure. Your platform can eventually do 211 * some very early initializations from the probe() routine, but 212 * this is not recommended, be very careful as, for example, the 213 * device-tree is not accessible via normal means at this point. 214 */ 215 216void __init early_setup(unsigned long dt_ptr) 217{ 218 static __initdata struct paca_struct boot_paca; 219 220 /* -------- printk is _NOT_ safe to use here ! ------- */ 221 222 /* Identify CPU type */ 223 identify_cpu(0, mfspr(SPRN_PVR)); 224 225 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 226 initialise_paca(&boot_paca, 0); 227 setup_paca(&boot_paca); 228 fixup_boot_paca(); 229 230 /* Initialize lockdep early or else spinlocks will blow */ 231 lockdep_init(); 232 233 /* -------- printk is now safe to use ------- */ 234 235 /* Enable early debugging if any specified (see udbg.h) */ 236 udbg_early_init(); 237 238 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 239 240 /* 241 * Do early initialization using the flattened device 242 * tree, such as retrieving the physical memory map or 243 * calculating/retrieving the hash table size. 244 */ 245 early_init_devtree(__va(dt_ptr)); 246 247 epapr_paravirt_early_init(); 248 249 /* Now we know the logical id of our boot cpu, setup the paca. */ 250 setup_paca(&paca[boot_cpuid]); 251 fixup_boot_paca(); 252 253 /* Probe the machine type */ 254 probe_machine(); 255 256 setup_kdump_trampoline(); 257 258 DBG("Found, Initializing memory management...\n"); 259 260 /* Initialize the hash table or TLB handling */ 261 early_init_mmu(); 262 263 kvm_cma_reserve(); 264 265 /* 266 * Reserve any gigantic pages requested on the command line. 267 * memblock needs to have been initialized by the time this is 268 * called since this will reserve memory. 269 */ 270 reserve_hugetlb_gpages(); 271 272 DBG(" <- early_setup()\n"); 273 274#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 275 /* 276 * This needs to be done *last* (after the above DBG() even) 277 * 278 * Right after we return from this function, we turn on the MMU 279 * which means the real-mode access trick that btext does will 280 * no longer work, it needs to switch to using a real MMU 281 * mapping. This call will ensure that it does 282 */ 283 btext_map(); 284#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 285} 286 287#ifdef CONFIG_SMP 288void early_setup_secondary(void) 289{ 290 /* Mark interrupts enabled in PACA */ 291 get_paca()->soft_enabled = 0; 292 293 /* Initialize the hash table or TLB handling */ 294 early_init_mmu_secondary(); 295} 296 297#endif /* CONFIG_SMP */ 298 299#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 300void smp_release_cpus(void) 301{ 302 unsigned long *ptr; 303 int i; 304 305 DBG(" -> smp_release_cpus()\n"); 306 307 /* All secondary cpus are spinning on a common spinloop, release them 308 * all now so they can start to spin on their individual paca 309 * spinloops. For non SMP kernels, the secondary cpus never get out 310 * of the common spinloop. 311 */ 312 313 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 314 - PHYSICAL_START); 315 *ptr = __pa(generic_secondary_smp_init); 316 317 /* And wait a bit for them to catch up */ 318 for (i = 0; i < 100000; i++) { 319 mb(); 320 HMT_low(); 321 if (spinning_secondaries == 0) 322 break; 323 udelay(1); 324 } 325 DBG("spinning_secondaries = %d\n", spinning_secondaries); 326 327 DBG(" <- smp_release_cpus()\n"); 328} 329#endif /* CONFIG_SMP || CONFIG_KEXEC */ 330 331/* 332 * Initialize some remaining members of the ppc64_caches and systemcfg 333 * structures 334 * (at least until we get rid of them completely). This is mostly some 335 * cache informations about the CPU that will be used by cache flush 336 * routines and/or provided to userland 337 */ 338static void __init initialize_cache_info(void) 339{ 340 struct device_node *np; 341 unsigned long num_cpus = 0; 342 343 DBG(" -> initialize_cache_info()\n"); 344 345 for_each_node_by_type(np, "cpu") { 346 num_cpus += 1; 347 348 /* 349 * We're assuming *all* of the CPUs have the same 350 * d-cache and i-cache sizes... -Peter 351 */ 352 if (num_cpus == 1) { 353 const __be32 *sizep, *lsizep; 354 u32 size, lsize; 355 356 size = 0; 357 lsize = cur_cpu_spec->dcache_bsize; 358 sizep = of_get_property(np, "d-cache-size", NULL); 359 if (sizep != NULL) 360 size = be32_to_cpu(*sizep); 361 lsizep = of_get_property(np, "d-cache-block-size", 362 NULL); 363 /* fallback if block size missing */ 364 if (lsizep == NULL) 365 lsizep = of_get_property(np, 366 "d-cache-line-size", 367 NULL); 368 if (lsizep != NULL) 369 lsize = be32_to_cpu(*lsizep); 370 if (sizep == NULL || lsizep == NULL) 371 DBG("Argh, can't find dcache properties ! " 372 "sizep: %p, lsizep: %p\n", sizep, lsizep); 373 374 ppc64_caches.dsize = size; 375 ppc64_caches.dline_size = lsize; 376 ppc64_caches.log_dline_size = __ilog2(lsize); 377 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 378 379 size = 0; 380 lsize = cur_cpu_spec->icache_bsize; 381 sizep = of_get_property(np, "i-cache-size", NULL); 382 if (sizep != NULL) 383 size = be32_to_cpu(*sizep); 384 lsizep = of_get_property(np, "i-cache-block-size", 385 NULL); 386 if (lsizep == NULL) 387 lsizep = of_get_property(np, 388 "i-cache-line-size", 389 NULL); 390 if (lsizep != NULL) 391 lsize = be32_to_cpu(*lsizep); 392 if (sizep == NULL || lsizep == NULL) 393 DBG("Argh, can't find icache properties ! " 394 "sizep: %p, lsizep: %p\n", sizep, lsizep); 395 396 ppc64_caches.isize = size; 397 ppc64_caches.iline_size = lsize; 398 ppc64_caches.log_iline_size = __ilog2(lsize); 399 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 400 } 401 } 402 403 DBG(" <- initialize_cache_info()\n"); 404} 405 406 407/* 408 * Do some initial setup of the system. The parameters are those which 409 * were passed in from the bootloader. 410 */ 411void __init setup_system(void) 412{ 413 DBG(" -> setup_system()\n"); 414 415 /* Apply the CPUs-specific and firmware specific fixups to kernel 416 * text (nop out sections not relevant to this CPU or this firmware) 417 */ 418 do_feature_fixups(cur_cpu_spec->cpu_features, 419 &__start___ftr_fixup, &__stop___ftr_fixup); 420 do_feature_fixups(cur_cpu_spec->mmu_features, 421 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 422 do_feature_fixups(powerpc_firmware_features, 423 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 424 do_lwsync_fixups(cur_cpu_spec->cpu_features, 425 &__start___lwsync_fixup, &__stop___lwsync_fixup); 426 do_final_fixups(); 427 428 /* 429 * Unflatten the device-tree passed by prom_init or kexec 430 */ 431 unflatten_device_tree(); 432 433 /* 434 * Fill the ppc64_caches & systemcfg structures with informations 435 * retrieved from the device-tree. 436 */ 437 initialize_cache_info(); 438 439#ifdef CONFIG_PPC_RTAS 440 /* 441 * Initialize RTAS if available 442 */ 443 rtas_initialize(); 444#endif /* CONFIG_PPC_RTAS */ 445 446 /* 447 * Check if we have an initrd provided via the device-tree 448 */ 449 check_for_initrd(); 450 451 /* 452 * Do some platform specific early initializations, that includes 453 * setting up the hash table pointers. It also sets up some interrupt-mapping 454 * related options that will be used by finish_device_tree() 455 */ 456 if (ppc_md.init_early) 457 ppc_md.init_early(); 458 459 /* 460 * We can discover serial ports now since the above did setup the 461 * hash table management for us, thus ioremap works. We do that early 462 * so that further code can be debugged 463 */ 464 find_legacy_serial_ports(); 465 466 /* 467 * Register early console 468 */ 469 register_early_udbg_console(); 470 471 /* 472 * Initialize xmon 473 */ 474 xmon_setup(); 475 476 smp_setup_cpu_maps(); 477 check_smt_enabled(); 478 setup_tlb_core_data(); 479 480#ifdef CONFIG_SMP 481 /* Release secondary cpus out of their spinloops at 0x60 now that 482 * we can map physical -> logical CPU ids 483 */ 484 smp_release_cpus(); 485#endif 486 487 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 488 489 printk("-----------------------------------------------------\n"); 490 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 491 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); 492 if (ppc64_caches.dline_size != 0x80) 493 printk("ppc64_caches.dcache_line_size = 0x%x\n", 494 ppc64_caches.dline_size); 495 if (ppc64_caches.iline_size != 0x80) 496 printk("ppc64_caches.icache_line_size = 0x%x\n", 497 ppc64_caches.iline_size); 498#ifdef CONFIG_PPC_STD_MMU_64 499 if (htab_address) 500 printk("htab_address = 0x%p\n", htab_address); 501 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 502#endif /* CONFIG_PPC_STD_MMU_64 */ 503 if (PHYSICAL_START > 0) 504 printk("physical_start = 0x%llx\n", 505 (unsigned long long)PHYSICAL_START); 506 printk("-----------------------------------------------------\n"); 507 508 DBG(" <- setup_system()\n"); 509} 510 511/* This returns the limit below which memory accesses to the linear 512 * mapping are guarnateed not to cause a TLB or SLB miss. This is 513 * used to allocate interrupt or emergency stacks for which our 514 * exception entry path doesn't deal with being interrupted. 515 */ 516static u64 safe_stack_limit(void) 517{ 518#ifdef CONFIG_PPC_BOOK3E 519 /* Freescale BookE bolts the entire linear mapping */ 520 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 521 return linear_map_top; 522 /* Other BookE, we assume the first GB is bolted */ 523 return 1ul << 30; 524#else 525 /* BookS, the first segment is bolted */ 526 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 527 return 1UL << SID_SHIFT_1T; 528 return 1UL << SID_SHIFT; 529#endif 530} 531 532static void __init irqstack_early_init(void) 533{ 534 u64 limit = safe_stack_limit(); 535 unsigned int i; 536 537 /* 538 * Interrupt stacks must be in the first segment since we 539 * cannot afford to take SLB misses on them. 540 */ 541 for_each_possible_cpu(i) { 542 softirq_ctx[i] = (struct thread_info *) 543 __va(memblock_alloc_base(THREAD_SIZE, 544 THREAD_SIZE, limit)); 545 hardirq_ctx[i] = (struct thread_info *) 546 __va(memblock_alloc_base(THREAD_SIZE, 547 THREAD_SIZE, limit)); 548 } 549} 550 551#ifdef CONFIG_PPC_BOOK3E 552static void __init exc_lvl_early_init(void) 553{ 554 unsigned int i; 555 unsigned long sp; 556 557 for_each_possible_cpu(i) { 558 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 559 critirq_ctx[i] = (struct thread_info *)__va(sp); 560 paca[i].crit_kstack = __va(sp + THREAD_SIZE); 561 562 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 563 dbgirq_ctx[i] = (struct thread_info *)__va(sp); 564 paca[i].dbg_kstack = __va(sp + THREAD_SIZE); 565 566 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 567 mcheckirq_ctx[i] = (struct thread_info *)__va(sp); 568 paca[i].mc_kstack = __va(sp + THREAD_SIZE); 569 } 570 571 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 572 patch_exception(0x040, exc_debug_debug_book3e); 573} 574#else 575#define exc_lvl_early_init() 576#endif 577 578/* 579 * Stack space used when we detect a bad kernel stack pointer, and 580 * early in SMP boots before relocation is enabled. Exclusive emergency 581 * stack for machine checks. 582 */ 583static void __init emergency_stack_init(void) 584{ 585 u64 limit; 586 unsigned int i; 587 588 /* 589 * Emergency stacks must be under 256MB, we cannot afford to take 590 * SLB misses on them. The ABI also requires them to be 128-byte 591 * aligned. 592 * 593 * Since we use these as temporary stacks during secondary CPU 594 * bringup, we need to get at them in real mode. This means they 595 * must also be within the RMO region. 596 */ 597 limit = min(safe_stack_limit(), ppc64_rma_size); 598 599 for_each_possible_cpu(i) { 600 unsigned long sp; 601 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 602 sp += THREAD_SIZE; 603 paca[i].emergency_sp = __va(sp); 604 605#ifdef CONFIG_PPC_BOOK3S_64 606 /* emergency stack for machine check exception handling. */ 607 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 608 sp += THREAD_SIZE; 609 paca[i].mc_emergency_sp = __va(sp); 610#endif 611 } 612} 613 614/* 615 * Called into from start_kernel this initializes bootmem, which is used 616 * to manage page allocation until mem_init is called. 617 */ 618void __init setup_arch(char **cmdline_p) 619{ 620 ppc64_boot_msg(0x12, "Setup Arch"); 621 622 *cmdline_p = cmd_line; 623 624 /* 625 * Set cache line size based on type of cpu as a default. 626 * Systems with OF can look in the properties on the cpu node(s) 627 * for a possibly more accurate value. 628 */ 629 dcache_bsize = ppc64_caches.dline_size; 630 icache_bsize = ppc64_caches.iline_size; 631 632 if (ppc_md.panic) 633 setup_panic(); 634 635 init_mm.start_code = (unsigned long)_stext; 636 init_mm.end_code = (unsigned long) _etext; 637 init_mm.end_data = (unsigned long) _edata; 638 init_mm.brk = klimit; 639#ifdef CONFIG_PPC_64K_PAGES 640 init_mm.context.pte_frag = NULL; 641#endif 642 irqstack_early_init(); 643 exc_lvl_early_init(); 644 emergency_stack_init(); 645 646#ifdef CONFIG_PPC_STD_MMU_64 647 stabs_alloc(); 648#endif 649 /* set up the bootmem stuff with available memory */ 650 do_init_bootmem(); 651 sparse_init(); 652 653#ifdef CONFIG_DUMMY_CONSOLE 654 conswitchp = &dummy_con; 655#endif 656 657 if (ppc_md.setup_arch) 658 ppc_md.setup_arch(); 659 660 paging_init(); 661 662 /* Initialize the MMU context management stuff */ 663 mmu_context_init(); 664 665 /* Interrupt code needs to be 64K-aligned */ 666 if ((unsigned long)_stext & 0xffff) 667 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 668 (unsigned long)_stext); 669 670 ppc64_boot_msg(0x15, "Setup Done"); 671} 672 673 674/* ToDo: do something useful if ppc_md is not yet setup. */ 675#define PPC64_LINUX_FUNCTION 0x0f000000 676#define PPC64_IPL_MESSAGE 0xc0000000 677#define PPC64_TERM_MESSAGE 0xb0000000 678 679static void ppc64_do_msg(unsigned int src, const char *msg) 680{ 681 if (ppc_md.progress) { 682 char buf[128]; 683 684 sprintf(buf, "%08X\n", src); 685 ppc_md.progress(buf, 0); 686 snprintf(buf, 128, "%s", msg); 687 ppc_md.progress(buf, 0); 688 } 689} 690 691/* Print a boot progress message. */ 692void ppc64_boot_msg(unsigned int src, const char *msg) 693{ 694 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); 695 printk("[boot]%04x %s\n", src, msg); 696} 697 698#ifdef CONFIG_SMP 699#define PCPU_DYN_SIZE () 700 701static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 702{ 703 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 704 __pa(MAX_DMA_ADDRESS)); 705} 706 707static void __init pcpu_fc_free(void *ptr, size_t size) 708{ 709 free_bootmem(__pa(ptr), size); 710} 711 712static int pcpu_cpu_distance(unsigned int from, unsigned int to) 713{ 714 if (cpu_to_node(from) == cpu_to_node(to)) 715 return LOCAL_DISTANCE; 716 else 717 return REMOTE_DISTANCE; 718} 719 720unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 721EXPORT_SYMBOL(__per_cpu_offset); 722 723void __init setup_per_cpu_areas(void) 724{ 725 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 726 size_t atom_size; 727 unsigned long delta; 728 unsigned int cpu; 729 int rc; 730 731 /* 732 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 733 * to group units. For larger mappings, use 1M atom which 734 * should be large enough to contain a number of units. 735 */ 736 if (mmu_linear_psize == MMU_PAGE_4K) 737 atom_size = PAGE_SIZE; 738 else 739 atom_size = 1 << 20; 740 741 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 742 pcpu_fc_alloc, pcpu_fc_free); 743 if (rc < 0) 744 panic("cannot initialize percpu area (err=%d)", rc); 745 746 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 747 for_each_possible_cpu(cpu) { 748 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 749 paca[cpu].data_offset = __per_cpu_offset[cpu]; 750 } 751} 752#endif 753 754 755#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 756struct ppc_pci_io ppc_pci_io; 757EXPORT_SYMBOL(ppc_pci_io); 758#endif 759