setup_64.c revision 4b16f8e2d6d64249f0ed3ca7fe2a319d0dde2719
1/* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#undef DEBUG 14 15#include <linux/export.h> 16#include <linux/string.h> 17#include <linux/sched.h> 18#include <linux/init.h> 19#include <linux/kernel.h> 20#include <linux/reboot.h> 21#include <linux/delay.h> 22#include <linux/initrd.h> 23#include <linux/seq_file.h> 24#include <linux/ioport.h> 25#include <linux/console.h> 26#include <linux/utsname.h> 27#include <linux/tty.h> 28#include <linux/root_dev.h> 29#include <linux/notifier.h> 30#include <linux/cpu.h> 31#include <linux/unistd.h> 32#include <linux/serial.h> 33#include <linux/serial_8250.h> 34#include <linux/bootmem.h> 35#include <linux/pci.h> 36#include <linux/lockdep.h> 37#include <linux/memblock.h> 38#include <asm/io.h> 39#include <asm/kdump.h> 40#include <asm/prom.h> 41#include <asm/processor.h> 42#include <asm/pgtable.h> 43#include <asm/smp.h> 44#include <asm/elf.h> 45#include <asm/machdep.h> 46#include <asm/paca.h> 47#include <asm/time.h> 48#include <asm/cputable.h> 49#include <asm/sections.h> 50#include <asm/btext.h> 51#include <asm/nvram.h> 52#include <asm/setup.h> 53#include <asm/system.h> 54#include <asm/rtas.h> 55#include <asm/iommu.h> 56#include <asm/serial.h> 57#include <asm/cache.h> 58#include <asm/page.h> 59#include <asm/mmu.h> 60#include <asm/firmware.h> 61#include <asm/xmon.h> 62#include <asm/udbg.h> 63#include <asm/kexec.h> 64#include <asm/mmu_context.h> 65#include <asm/code-patching.h> 66#include <asm/kvm_ppc.h> 67 68#include "setup.h" 69 70#ifdef DEBUG 71#define DBG(fmt...) udbg_printf(fmt) 72#else 73#define DBG(fmt...) 74#endif 75 76int boot_cpuid = 0; 77int __initdata spinning_secondaries; 78u64 ppc64_pft_size; 79 80/* Pick defaults since we might want to patch instructions 81 * before we've read this from the device tree. 82 */ 83struct ppc64_caches ppc64_caches = { 84 .dline_size = 0x40, 85 .log_dline_size = 6, 86 .iline_size = 0x40, 87 .log_iline_size = 6 88}; 89EXPORT_SYMBOL_GPL(ppc64_caches); 90 91/* 92 * These are used in binfmt_elf.c to put aux entries on the stack 93 * for each elf executable being started. 94 */ 95int dcache_bsize; 96int icache_bsize; 97int ucache_bsize; 98 99#ifdef CONFIG_SMP 100 101static char *smt_enabled_cmdline; 102 103/* Look for ibm,smt-enabled OF option */ 104static void check_smt_enabled(void) 105{ 106 struct device_node *dn; 107 const char *smt_option; 108 109 /* Default to enabling all threads */ 110 smt_enabled_at_boot = threads_per_core; 111 112 /* Allow the command line to overrule the OF option */ 113 if (smt_enabled_cmdline) { 114 if (!strcmp(smt_enabled_cmdline, "on")) 115 smt_enabled_at_boot = threads_per_core; 116 else if (!strcmp(smt_enabled_cmdline, "off")) 117 smt_enabled_at_boot = 0; 118 else { 119 long smt; 120 int rc; 121 122 rc = strict_strtol(smt_enabled_cmdline, 10, &smt); 123 if (!rc) 124 smt_enabled_at_boot = 125 min(threads_per_core, (int)smt); 126 } 127 } else { 128 dn = of_find_node_by_path("/options"); 129 if (dn) { 130 smt_option = of_get_property(dn, "ibm,smt-enabled", 131 NULL); 132 133 if (smt_option) { 134 if (!strcmp(smt_option, "on")) 135 smt_enabled_at_boot = threads_per_core; 136 else if (!strcmp(smt_option, "off")) 137 smt_enabled_at_boot = 0; 138 } 139 140 of_node_put(dn); 141 } 142 } 143} 144 145/* Look for smt-enabled= cmdline option */ 146static int __init early_smt_enabled(char *p) 147{ 148 smt_enabled_cmdline = p; 149 return 0; 150} 151early_param("smt-enabled", early_smt_enabled); 152 153#else 154#define check_smt_enabled() 155#endif /* CONFIG_SMP */ 156 157/* 158 * Early initialization entry point. This is called by head.S 159 * with MMU translation disabled. We rely on the "feature" of 160 * the CPU that ignores the top 2 bits of the address in real 161 * mode so we can access kernel globals normally provided we 162 * only toy with things in the RMO region. From here, we do 163 * some early parsing of the device-tree to setup out MEMBLOCK 164 * data structures, and allocate & initialize the hash table 165 * and segment tables so we can start running with translation 166 * enabled. 167 * 168 * It is this function which will call the probe() callback of 169 * the various platform types and copy the matching one to the 170 * global ppc_md structure. Your platform can eventually do 171 * some very early initializations from the probe() routine, but 172 * this is not recommended, be very careful as, for example, the 173 * device-tree is not accessible via normal means at this point. 174 */ 175 176void __init early_setup(unsigned long dt_ptr) 177{ 178 /* -------- printk is _NOT_ safe to use here ! ------- */ 179 180 /* Identify CPU type */ 181 identify_cpu(0, mfspr(SPRN_PVR)); 182 183 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 184 initialise_paca(&boot_paca, 0); 185 setup_paca(&boot_paca); 186 187 /* Initialize lockdep early or else spinlocks will blow */ 188 lockdep_init(); 189 190 /* -------- printk is now safe to use ------- */ 191 192 /* Enable early debugging if any specified (see udbg.h) */ 193 udbg_early_init(); 194 195 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 196 197 /* 198 * Do early initialization using the flattened device 199 * tree, such as retrieving the physical memory map or 200 * calculating/retrieving the hash table size. 201 */ 202 early_init_devtree(__va(dt_ptr)); 203 204 /* Now we know the logical id of our boot cpu, setup the paca. */ 205 setup_paca(&paca[boot_cpuid]); 206 207 /* Fix up paca fields required for the boot cpu */ 208 get_paca()->cpu_start = 1; 209 210 /* Probe the machine type */ 211 probe_machine(); 212 213 setup_kdump_trampoline(); 214 215 DBG("Found, Initializing memory management...\n"); 216 217 /* Initialize the hash table or TLB handling */ 218 early_init_mmu(); 219 220 DBG(" <- early_setup()\n"); 221} 222 223#ifdef CONFIG_SMP 224void early_setup_secondary(void) 225{ 226 /* Mark interrupts enabled in PACA */ 227 get_paca()->soft_enabled = 0; 228 229 /* Initialize the hash table or TLB handling */ 230 early_init_mmu_secondary(); 231} 232 233#endif /* CONFIG_SMP */ 234 235#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 236void smp_release_cpus(void) 237{ 238 unsigned long *ptr; 239 int i; 240 241 DBG(" -> smp_release_cpus()\n"); 242 243 /* All secondary cpus are spinning on a common spinloop, release them 244 * all now so they can start to spin on their individual paca 245 * spinloops. For non SMP kernels, the secondary cpus never get out 246 * of the common spinloop. 247 */ 248 249 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 250 - PHYSICAL_START); 251 *ptr = __pa(generic_secondary_smp_init); 252 253 /* And wait a bit for them to catch up */ 254 for (i = 0; i < 100000; i++) { 255 mb(); 256 HMT_low(); 257 if (spinning_secondaries == 0) 258 break; 259 udelay(1); 260 } 261 DBG("spinning_secondaries = %d\n", spinning_secondaries); 262 263 DBG(" <- smp_release_cpus()\n"); 264} 265#endif /* CONFIG_SMP || CONFIG_KEXEC */ 266 267/* 268 * Initialize some remaining members of the ppc64_caches and systemcfg 269 * structures 270 * (at least until we get rid of them completely). This is mostly some 271 * cache informations about the CPU that will be used by cache flush 272 * routines and/or provided to userland 273 */ 274static void __init initialize_cache_info(void) 275{ 276 struct device_node *np; 277 unsigned long num_cpus = 0; 278 279 DBG(" -> initialize_cache_info()\n"); 280 281 for (np = NULL; (np = of_find_node_by_type(np, "cpu"));) { 282 num_cpus += 1; 283 284 /* We're assuming *all* of the CPUs have the same 285 * d-cache and i-cache sizes... -Peter 286 */ 287 288 if ( num_cpus == 1 ) { 289 const u32 *sizep, *lsizep; 290 u32 size, lsize; 291 292 size = 0; 293 lsize = cur_cpu_spec->dcache_bsize; 294 sizep = of_get_property(np, "d-cache-size", NULL); 295 if (sizep != NULL) 296 size = *sizep; 297 lsizep = of_get_property(np, "d-cache-block-size", NULL); 298 /* fallback if block size missing */ 299 if (lsizep == NULL) 300 lsizep = of_get_property(np, "d-cache-line-size", NULL); 301 if (lsizep != NULL) 302 lsize = *lsizep; 303 if (sizep == 0 || lsizep == 0) 304 DBG("Argh, can't find dcache properties ! " 305 "sizep: %p, lsizep: %p\n", sizep, lsizep); 306 307 ppc64_caches.dsize = size; 308 ppc64_caches.dline_size = lsize; 309 ppc64_caches.log_dline_size = __ilog2(lsize); 310 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 311 312 size = 0; 313 lsize = cur_cpu_spec->icache_bsize; 314 sizep = of_get_property(np, "i-cache-size", NULL); 315 if (sizep != NULL) 316 size = *sizep; 317 lsizep = of_get_property(np, "i-cache-block-size", NULL); 318 if (lsizep == NULL) 319 lsizep = of_get_property(np, "i-cache-line-size", NULL); 320 if (lsizep != NULL) 321 lsize = *lsizep; 322 if (sizep == 0 || lsizep == 0) 323 DBG("Argh, can't find icache properties ! " 324 "sizep: %p, lsizep: %p\n", sizep, lsizep); 325 326 ppc64_caches.isize = size; 327 ppc64_caches.iline_size = lsize; 328 ppc64_caches.log_iline_size = __ilog2(lsize); 329 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 330 } 331 } 332 333 DBG(" <- initialize_cache_info()\n"); 334} 335 336 337/* 338 * Do some initial setup of the system. The parameters are those which 339 * were passed in from the bootloader. 340 */ 341void __init setup_system(void) 342{ 343 DBG(" -> setup_system()\n"); 344 345 /* Apply the CPUs-specific and firmware specific fixups to kernel 346 * text (nop out sections not relevant to this CPU or this firmware) 347 */ 348 do_feature_fixups(cur_cpu_spec->cpu_features, 349 &__start___ftr_fixup, &__stop___ftr_fixup); 350 do_feature_fixups(cur_cpu_spec->mmu_features, 351 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 352 do_feature_fixups(powerpc_firmware_features, 353 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 354 do_lwsync_fixups(cur_cpu_spec->cpu_features, 355 &__start___lwsync_fixup, &__stop___lwsync_fixup); 356 357 /* 358 * Unflatten the device-tree passed by prom_init or kexec 359 */ 360 unflatten_device_tree(); 361 362 /* 363 * Fill the ppc64_caches & systemcfg structures with informations 364 * retrieved from the device-tree. 365 */ 366 initialize_cache_info(); 367 368#ifdef CONFIG_PPC_RTAS 369 /* 370 * Initialize RTAS if available 371 */ 372 rtas_initialize(); 373#endif /* CONFIG_PPC_RTAS */ 374 375 /* 376 * Check if we have an initrd provided via the device-tree 377 */ 378 check_for_initrd(); 379 380 /* 381 * Do some platform specific early initializations, that includes 382 * setting up the hash table pointers. It also sets up some interrupt-mapping 383 * related options that will be used by finish_device_tree() 384 */ 385 if (ppc_md.init_early) 386 ppc_md.init_early(); 387 388 /* 389 * We can discover serial ports now since the above did setup the 390 * hash table management for us, thus ioremap works. We do that early 391 * so that further code can be debugged 392 */ 393 find_legacy_serial_ports(); 394 395 /* 396 * Register early console 397 */ 398 register_early_udbg_console(); 399 400 /* 401 * Initialize xmon 402 */ 403 xmon_setup(); 404 405 smp_setup_cpu_maps(); 406 check_smt_enabled(); 407 408#ifdef CONFIG_SMP 409 /* Release secondary cpus out of their spinloops at 0x60 now that 410 * we can map physical -> logical CPU ids 411 */ 412 smp_release_cpus(); 413#endif 414 415 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 416 417 printk("-----------------------------------------------------\n"); 418 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 419 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); 420 if (ppc64_caches.dline_size != 0x80) 421 printk("ppc64_caches.dcache_line_size = 0x%x\n", 422 ppc64_caches.dline_size); 423 if (ppc64_caches.iline_size != 0x80) 424 printk("ppc64_caches.icache_line_size = 0x%x\n", 425 ppc64_caches.iline_size); 426#ifdef CONFIG_PPC_STD_MMU_64 427 if (htab_address) 428 printk("htab_address = 0x%p\n", htab_address); 429 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 430#endif /* CONFIG_PPC_STD_MMU_64 */ 431 if (PHYSICAL_START > 0) 432 printk("physical_start = 0x%llx\n", 433 (unsigned long long)PHYSICAL_START); 434 printk("-----------------------------------------------------\n"); 435 436 DBG(" <- setup_system()\n"); 437} 438 439/* This returns the limit below which memory accesses to the linear 440 * mapping are guarnateed not to cause a TLB or SLB miss. This is 441 * used to allocate interrupt or emergency stacks for which our 442 * exception entry path doesn't deal with being interrupted. 443 */ 444static u64 safe_stack_limit(void) 445{ 446#ifdef CONFIG_PPC_BOOK3E 447 /* Freescale BookE bolts the entire linear mapping */ 448 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 449 return linear_map_top; 450 /* Other BookE, we assume the first GB is bolted */ 451 return 1ul << 30; 452#else 453 /* BookS, the first segment is bolted */ 454 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 455 return 1UL << SID_SHIFT_1T; 456 return 1UL << SID_SHIFT; 457#endif 458} 459 460static void __init irqstack_early_init(void) 461{ 462 u64 limit = safe_stack_limit(); 463 unsigned int i; 464 465 /* 466 * Interrupt stacks must be in the first segment since we 467 * cannot afford to take SLB misses on them. 468 */ 469 for_each_possible_cpu(i) { 470 softirq_ctx[i] = (struct thread_info *) 471 __va(memblock_alloc_base(THREAD_SIZE, 472 THREAD_SIZE, limit)); 473 hardirq_ctx[i] = (struct thread_info *) 474 __va(memblock_alloc_base(THREAD_SIZE, 475 THREAD_SIZE, limit)); 476 } 477} 478 479#ifdef CONFIG_PPC_BOOK3E 480static void __init exc_lvl_early_init(void) 481{ 482 extern unsigned int interrupt_base_book3e; 483 extern unsigned int exc_debug_debug_book3e; 484 485 unsigned int i; 486 487 for_each_possible_cpu(i) { 488 critirq_ctx[i] = (struct thread_info *) 489 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 490 dbgirq_ctx[i] = (struct thread_info *) 491 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 492 mcheckirq_ctx[i] = (struct thread_info *) 493 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 494 } 495 496 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 497 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1, 498 (unsigned long)&exc_debug_debug_book3e, 0); 499} 500#else 501#define exc_lvl_early_init() 502#endif 503 504/* 505 * Stack space used when we detect a bad kernel stack pointer, and 506 * early in SMP boots before relocation is enabled. 507 */ 508static void __init emergency_stack_init(void) 509{ 510 u64 limit; 511 unsigned int i; 512 513 /* 514 * Emergency stacks must be under 256MB, we cannot afford to take 515 * SLB misses on them. The ABI also requires them to be 128-byte 516 * aligned. 517 * 518 * Since we use these as temporary stacks during secondary CPU 519 * bringup, we need to get at them in real mode. This means they 520 * must also be within the RMO region. 521 */ 522 limit = min(safe_stack_limit(), ppc64_rma_size); 523 524 for_each_possible_cpu(i) { 525 unsigned long sp; 526 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 527 sp += THREAD_SIZE; 528 paca[i].emergency_sp = __va(sp); 529 } 530} 531 532/* 533 * Called into from start_kernel this initializes bootmem, which is used 534 * to manage page allocation until mem_init is called. 535 */ 536void __init setup_arch(char **cmdline_p) 537{ 538 ppc64_boot_msg(0x12, "Setup Arch"); 539 540 *cmdline_p = cmd_line; 541 542 /* 543 * Set cache line size based on type of cpu as a default. 544 * Systems with OF can look in the properties on the cpu node(s) 545 * for a possibly more accurate value. 546 */ 547 dcache_bsize = ppc64_caches.dline_size; 548 icache_bsize = ppc64_caches.iline_size; 549 550 /* reboot on panic */ 551 panic_timeout = 180; 552 553 if (ppc_md.panic) 554 setup_panic(); 555 556 init_mm.start_code = (unsigned long)_stext; 557 init_mm.end_code = (unsigned long) _etext; 558 init_mm.end_data = (unsigned long) _edata; 559 init_mm.brk = klimit; 560 561 irqstack_early_init(); 562 exc_lvl_early_init(); 563 emergency_stack_init(); 564 565#ifdef CONFIG_PPC_STD_MMU_64 566 stabs_alloc(); 567#endif 568 /* set up the bootmem stuff with available memory */ 569 do_init_bootmem(); 570 sparse_init(); 571 572#ifdef CONFIG_DUMMY_CONSOLE 573 conswitchp = &dummy_con; 574#endif 575 576 if (ppc_md.setup_arch) 577 ppc_md.setup_arch(); 578 579 paging_init(); 580 581 /* Initialize the MMU context management stuff */ 582 mmu_context_init(); 583 584 kvm_rma_init(); 585 586 ppc64_boot_msg(0x15, "Setup Done"); 587} 588 589 590/* ToDo: do something useful if ppc_md is not yet setup. */ 591#define PPC64_LINUX_FUNCTION 0x0f000000 592#define PPC64_IPL_MESSAGE 0xc0000000 593#define PPC64_TERM_MESSAGE 0xb0000000 594 595static void ppc64_do_msg(unsigned int src, const char *msg) 596{ 597 if (ppc_md.progress) { 598 char buf[128]; 599 600 sprintf(buf, "%08X\n", src); 601 ppc_md.progress(buf, 0); 602 snprintf(buf, 128, "%s", msg); 603 ppc_md.progress(buf, 0); 604 } 605} 606 607/* Print a boot progress message. */ 608void ppc64_boot_msg(unsigned int src, const char *msg) 609{ 610 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); 611 printk("[boot]%04x %s\n", src, msg); 612} 613 614#ifdef CONFIG_SMP 615#define PCPU_DYN_SIZE () 616 617static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 618{ 619 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 620 __pa(MAX_DMA_ADDRESS)); 621} 622 623static void __init pcpu_fc_free(void *ptr, size_t size) 624{ 625 free_bootmem(__pa(ptr), size); 626} 627 628static int pcpu_cpu_distance(unsigned int from, unsigned int to) 629{ 630 if (cpu_to_node(from) == cpu_to_node(to)) 631 return LOCAL_DISTANCE; 632 else 633 return REMOTE_DISTANCE; 634} 635 636unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 637EXPORT_SYMBOL(__per_cpu_offset); 638 639void __init setup_per_cpu_areas(void) 640{ 641 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 642 size_t atom_size; 643 unsigned long delta; 644 unsigned int cpu; 645 int rc; 646 647 /* 648 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 649 * to group units. For larger mappings, use 1M atom which 650 * should be large enough to contain a number of units. 651 */ 652 if (mmu_linear_psize == MMU_PAGE_4K) 653 atom_size = PAGE_SIZE; 654 else 655 atom_size = 1 << 20; 656 657 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 658 pcpu_fc_alloc, pcpu_fc_free); 659 if (rc < 0) 660 panic("cannot initialize percpu area (err=%d)", rc); 661 662 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 663 for_each_possible_cpu(cpu) { 664 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 665 paca[cpu].data_offset = __per_cpu_offset[cpu]; 666 } 667} 668#endif 669 670 671#ifdef CONFIG_PPC_INDIRECT_IO 672struct ppc_pci_io ppc_pci_io; 673EXPORT_SYMBOL(ppc_pci_io); 674#endif /* CONFIG_PPC_INDIRECT_IO */ 675 676