setup_64.c revision 5c1f6ee9a31cbdac90bbb8ae1ba4475031ac74b4
1/* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#undef DEBUG 14 15#include <linux/export.h> 16#include <linux/string.h> 17#include <linux/sched.h> 18#include <linux/init.h> 19#include <linux/kernel.h> 20#include <linux/reboot.h> 21#include <linux/delay.h> 22#include <linux/initrd.h> 23#include <linux/seq_file.h> 24#include <linux/ioport.h> 25#include <linux/console.h> 26#include <linux/utsname.h> 27#include <linux/tty.h> 28#include <linux/root_dev.h> 29#include <linux/notifier.h> 30#include <linux/cpu.h> 31#include <linux/unistd.h> 32#include <linux/serial.h> 33#include <linux/serial_8250.h> 34#include <linux/bootmem.h> 35#include <linux/pci.h> 36#include <linux/lockdep.h> 37#include <linux/memblock.h> 38#include <linux/hugetlb.h> 39 40#include <asm/io.h> 41#include <asm/kdump.h> 42#include <asm/prom.h> 43#include <asm/processor.h> 44#include <asm/pgtable.h> 45#include <asm/smp.h> 46#include <asm/elf.h> 47#include <asm/machdep.h> 48#include <asm/paca.h> 49#include <asm/time.h> 50#include <asm/cputable.h> 51#include <asm/sections.h> 52#include <asm/btext.h> 53#include <asm/nvram.h> 54#include <asm/setup.h> 55#include <asm/rtas.h> 56#include <asm/iommu.h> 57#include <asm/serial.h> 58#include <asm/cache.h> 59#include <asm/page.h> 60#include <asm/mmu.h> 61#include <asm/firmware.h> 62#include <asm/xmon.h> 63#include <asm/udbg.h> 64#include <asm/kexec.h> 65#include <asm/mmu_context.h> 66#include <asm/code-patching.h> 67#include <asm/kvm_ppc.h> 68#include <asm/hugetlb.h> 69 70#include "setup.h" 71 72#ifdef DEBUG 73#define DBG(fmt...) udbg_printf(fmt) 74#else 75#define DBG(fmt...) 76#endif 77 78int boot_cpuid = 0; 79int __initdata spinning_secondaries; 80u64 ppc64_pft_size; 81 82/* Pick defaults since we might want to patch instructions 83 * before we've read this from the device tree. 84 */ 85struct ppc64_caches ppc64_caches = { 86 .dline_size = 0x40, 87 .log_dline_size = 6, 88 .iline_size = 0x40, 89 .log_iline_size = 6 90}; 91EXPORT_SYMBOL_GPL(ppc64_caches); 92 93/* 94 * These are used in binfmt_elf.c to put aux entries on the stack 95 * for each elf executable being started. 96 */ 97int dcache_bsize; 98int icache_bsize; 99int ucache_bsize; 100 101#ifdef CONFIG_SMP 102 103static char *smt_enabled_cmdline; 104 105/* Look for ibm,smt-enabled OF option */ 106static void check_smt_enabled(void) 107{ 108 struct device_node *dn; 109 const char *smt_option; 110 111 /* Default to enabling all threads */ 112 smt_enabled_at_boot = threads_per_core; 113 114 /* Allow the command line to overrule the OF option */ 115 if (smt_enabled_cmdline) { 116 if (!strcmp(smt_enabled_cmdline, "on")) 117 smt_enabled_at_boot = threads_per_core; 118 else if (!strcmp(smt_enabled_cmdline, "off")) 119 smt_enabled_at_boot = 0; 120 else { 121 long smt; 122 int rc; 123 124 rc = strict_strtol(smt_enabled_cmdline, 10, &smt); 125 if (!rc) 126 smt_enabled_at_boot = 127 min(threads_per_core, (int)smt); 128 } 129 } else { 130 dn = of_find_node_by_path("/options"); 131 if (dn) { 132 smt_option = of_get_property(dn, "ibm,smt-enabled", 133 NULL); 134 135 if (smt_option) { 136 if (!strcmp(smt_option, "on")) 137 smt_enabled_at_boot = threads_per_core; 138 else if (!strcmp(smt_option, "off")) 139 smt_enabled_at_boot = 0; 140 } 141 142 of_node_put(dn); 143 } 144 } 145} 146 147/* Look for smt-enabled= cmdline option */ 148static int __init early_smt_enabled(char *p) 149{ 150 smt_enabled_cmdline = p; 151 return 0; 152} 153early_param("smt-enabled", early_smt_enabled); 154 155#else 156#define check_smt_enabled() 157#endif /* CONFIG_SMP */ 158 159/** Fix up paca fields required for the boot cpu */ 160static void fixup_boot_paca(void) 161{ 162 /* The boot cpu is started */ 163 get_paca()->cpu_start = 1; 164 /* Allow percpu accesses to work until we setup percpu data */ 165 get_paca()->data_offset = 0; 166} 167 168/* 169 * Early initialization entry point. This is called by head.S 170 * with MMU translation disabled. We rely on the "feature" of 171 * the CPU that ignores the top 2 bits of the address in real 172 * mode so we can access kernel globals normally provided we 173 * only toy with things in the RMO region. From here, we do 174 * some early parsing of the device-tree to setup out MEMBLOCK 175 * data structures, and allocate & initialize the hash table 176 * and segment tables so we can start running with translation 177 * enabled. 178 * 179 * It is this function which will call the probe() callback of 180 * the various platform types and copy the matching one to the 181 * global ppc_md structure. Your platform can eventually do 182 * some very early initializations from the probe() routine, but 183 * this is not recommended, be very careful as, for example, the 184 * device-tree is not accessible via normal means at this point. 185 */ 186 187void __init early_setup(unsigned long dt_ptr) 188{ 189 static __initdata struct paca_struct boot_paca; 190 191 /* -------- printk is _NOT_ safe to use here ! ------- */ 192 193 /* Identify CPU type */ 194 identify_cpu(0, mfspr(SPRN_PVR)); 195 196 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 197 initialise_paca(&boot_paca, 0); 198 setup_paca(&boot_paca); 199 fixup_boot_paca(); 200 201 /* Initialize lockdep early or else spinlocks will blow */ 202 lockdep_init(); 203 204 /* -------- printk is now safe to use ------- */ 205 206 /* Enable early debugging if any specified (see udbg.h) */ 207 udbg_early_init(); 208 209 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 210 211 /* 212 * Do early initialization using the flattened device 213 * tree, such as retrieving the physical memory map or 214 * calculating/retrieving the hash table size. 215 */ 216 early_init_devtree(__va(dt_ptr)); 217 218 /* Now we know the logical id of our boot cpu, setup the paca. */ 219 setup_paca(&paca[boot_cpuid]); 220 fixup_boot_paca(); 221 222 /* Probe the machine type */ 223 probe_machine(); 224 225 setup_kdump_trampoline(); 226 227 DBG("Found, Initializing memory management...\n"); 228 229 /* Initialize the hash table or TLB handling */ 230 early_init_mmu(); 231 232 /* 233 * Reserve any gigantic pages requested on the command line. 234 * memblock needs to have been initialized by the time this is 235 * called since this will reserve memory. 236 */ 237 reserve_hugetlb_gpages(); 238 239 DBG(" <- early_setup()\n"); 240} 241 242#ifdef CONFIG_SMP 243void early_setup_secondary(void) 244{ 245 /* Mark interrupts enabled in PACA */ 246 get_paca()->soft_enabled = 0; 247 248 /* Initialize the hash table or TLB handling */ 249 early_init_mmu_secondary(); 250} 251 252#endif /* CONFIG_SMP */ 253 254#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 255void smp_release_cpus(void) 256{ 257 unsigned long *ptr; 258 int i; 259 260 DBG(" -> smp_release_cpus()\n"); 261 262 /* All secondary cpus are spinning on a common spinloop, release them 263 * all now so they can start to spin on their individual paca 264 * spinloops. For non SMP kernels, the secondary cpus never get out 265 * of the common spinloop. 266 */ 267 268 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 269 - PHYSICAL_START); 270 *ptr = __pa(generic_secondary_smp_init); 271 272 /* And wait a bit for them to catch up */ 273 for (i = 0; i < 100000; i++) { 274 mb(); 275 HMT_low(); 276 if (spinning_secondaries == 0) 277 break; 278 udelay(1); 279 } 280 DBG("spinning_secondaries = %d\n", spinning_secondaries); 281 282 DBG(" <- smp_release_cpus()\n"); 283} 284#endif /* CONFIG_SMP || CONFIG_KEXEC */ 285 286/* 287 * Initialize some remaining members of the ppc64_caches and systemcfg 288 * structures 289 * (at least until we get rid of them completely). This is mostly some 290 * cache informations about the CPU that will be used by cache flush 291 * routines and/or provided to userland 292 */ 293static void __init initialize_cache_info(void) 294{ 295 struct device_node *np; 296 unsigned long num_cpus = 0; 297 298 DBG(" -> initialize_cache_info()\n"); 299 300 for_each_node_by_type(np, "cpu") { 301 num_cpus += 1; 302 303 /* 304 * We're assuming *all* of the CPUs have the same 305 * d-cache and i-cache sizes... -Peter 306 */ 307 if (num_cpus == 1) { 308 const u32 *sizep, *lsizep; 309 u32 size, lsize; 310 311 size = 0; 312 lsize = cur_cpu_spec->dcache_bsize; 313 sizep = of_get_property(np, "d-cache-size", NULL); 314 if (sizep != NULL) 315 size = *sizep; 316 lsizep = of_get_property(np, "d-cache-block-size", 317 NULL); 318 /* fallback if block size missing */ 319 if (lsizep == NULL) 320 lsizep = of_get_property(np, 321 "d-cache-line-size", 322 NULL); 323 if (lsizep != NULL) 324 lsize = *lsizep; 325 if (sizep == 0 || lsizep == 0) 326 DBG("Argh, can't find dcache properties ! " 327 "sizep: %p, lsizep: %p\n", sizep, lsizep); 328 329 ppc64_caches.dsize = size; 330 ppc64_caches.dline_size = lsize; 331 ppc64_caches.log_dline_size = __ilog2(lsize); 332 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 333 334 size = 0; 335 lsize = cur_cpu_spec->icache_bsize; 336 sizep = of_get_property(np, "i-cache-size", NULL); 337 if (sizep != NULL) 338 size = *sizep; 339 lsizep = of_get_property(np, "i-cache-block-size", 340 NULL); 341 if (lsizep == NULL) 342 lsizep = of_get_property(np, 343 "i-cache-line-size", 344 NULL); 345 if (lsizep != NULL) 346 lsize = *lsizep; 347 if (sizep == 0 || lsizep == 0) 348 DBG("Argh, can't find icache properties ! " 349 "sizep: %p, lsizep: %p\n", sizep, lsizep); 350 351 ppc64_caches.isize = size; 352 ppc64_caches.iline_size = lsize; 353 ppc64_caches.log_iline_size = __ilog2(lsize); 354 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 355 } 356 } 357 358 DBG(" <- initialize_cache_info()\n"); 359} 360 361 362/* 363 * Do some initial setup of the system. The parameters are those which 364 * were passed in from the bootloader. 365 */ 366void __init setup_system(void) 367{ 368 DBG(" -> setup_system()\n"); 369 370 /* Apply the CPUs-specific and firmware specific fixups to kernel 371 * text (nop out sections not relevant to this CPU or this firmware) 372 */ 373 do_feature_fixups(cur_cpu_spec->cpu_features, 374 &__start___ftr_fixup, &__stop___ftr_fixup); 375 do_feature_fixups(cur_cpu_spec->mmu_features, 376 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 377 do_feature_fixups(powerpc_firmware_features, 378 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 379 do_lwsync_fixups(cur_cpu_spec->cpu_features, 380 &__start___lwsync_fixup, &__stop___lwsync_fixup); 381 do_final_fixups(); 382 383 /* 384 * Unflatten the device-tree passed by prom_init or kexec 385 */ 386 unflatten_device_tree(); 387 388 /* 389 * Fill the ppc64_caches & systemcfg structures with informations 390 * retrieved from the device-tree. 391 */ 392 initialize_cache_info(); 393 394#ifdef CONFIG_PPC_RTAS 395 /* 396 * Initialize RTAS if available 397 */ 398 rtas_initialize(); 399#endif /* CONFIG_PPC_RTAS */ 400 401 /* 402 * Check if we have an initrd provided via the device-tree 403 */ 404 check_for_initrd(); 405 406 /* 407 * Do some platform specific early initializations, that includes 408 * setting up the hash table pointers. It also sets up some interrupt-mapping 409 * related options that will be used by finish_device_tree() 410 */ 411 if (ppc_md.init_early) 412 ppc_md.init_early(); 413 414 /* 415 * We can discover serial ports now since the above did setup the 416 * hash table management for us, thus ioremap works. We do that early 417 * so that further code can be debugged 418 */ 419 find_legacy_serial_ports(); 420 421 /* 422 * Register early console 423 */ 424 register_early_udbg_console(); 425 426 /* 427 * Initialize xmon 428 */ 429 xmon_setup(); 430 431 smp_setup_cpu_maps(); 432 check_smt_enabled(); 433 434#ifdef CONFIG_SMP 435 /* Release secondary cpus out of their spinloops at 0x60 now that 436 * we can map physical -> logical CPU ids 437 */ 438 smp_release_cpus(); 439#endif 440 441 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 442 443 printk("-----------------------------------------------------\n"); 444 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 445 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); 446 if (ppc64_caches.dline_size != 0x80) 447 printk("ppc64_caches.dcache_line_size = 0x%x\n", 448 ppc64_caches.dline_size); 449 if (ppc64_caches.iline_size != 0x80) 450 printk("ppc64_caches.icache_line_size = 0x%x\n", 451 ppc64_caches.iline_size); 452#ifdef CONFIG_PPC_STD_MMU_64 453 if (htab_address) 454 printk("htab_address = 0x%p\n", htab_address); 455 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 456#endif /* CONFIG_PPC_STD_MMU_64 */ 457 if (PHYSICAL_START > 0) 458 printk("physical_start = 0x%llx\n", 459 (unsigned long long)PHYSICAL_START); 460 printk("-----------------------------------------------------\n"); 461 462 DBG(" <- setup_system()\n"); 463} 464 465/* This returns the limit below which memory accesses to the linear 466 * mapping are guarnateed not to cause a TLB or SLB miss. This is 467 * used to allocate interrupt or emergency stacks for which our 468 * exception entry path doesn't deal with being interrupted. 469 */ 470static u64 safe_stack_limit(void) 471{ 472#ifdef CONFIG_PPC_BOOK3E 473 /* Freescale BookE bolts the entire linear mapping */ 474 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 475 return linear_map_top; 476 /* Other BookE, we assume the first GB is bolted */ 477 return 1ul << 30; 478#else 479 /* BookS, the first segment is bolted */ 480 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 481 return 1UL << SID_SHIFT_1T; 482 return 1UL << SID_SHIFT; 483#endif 484} 485 486static void __init irqstack_early_init(void) 487{ 488 u64 limit = safe_stack_limit(); 489 unsigned int i; 490 491 /* 492 * Interrupt stacks must be in the first segment since we 493 * cannot afford to take SLB misses on them. 494 */ 495 for_each_possible_cpu(i) { 496 softirq_ctx[i] = (struct thread_info *) 497 __va(memblock_alloc_base(THREAD_SIZE, 498 THREAD_SIZE, limit)); 499 hardirq_ctx[i] = (struct thread_info *) 500 __va(memblock_alloc_base(THREAD_SIZE, 501 THREAD_SIZE, limit)); 502 } 503} 504 505#ifdef CONFIG_PPC_BOOK3E 506static void __init exc_lvl_early_init(void) 507{ 508 extern unsigned int interrupt_base_book3e; 509 extern unsigned int exc_debug_debug_book3e; 510 511 unsigned int i; 512 513 for_each_possible_cpu(i) { 514 critirq_ctx[i] = (struct thread_info *) 515 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 516 dbgirq_ctx[i] = (struct thread_info *) 517 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 518 mcheckirq_ctx[i] = (struct thread_info *) 519 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 520 } 521 522 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 523 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1, 524 (unsigned long)&exc_debug_debug_book3e, 0); 525} 526#else 527#define exc_lvl_early_init() 528#endif 529 530/* 531 * Stack space used when we detect a bad kernel stack pointer, and 532 * early in SMP boots before relocation is enabled. 533 */ 534static void __init emergency_stack_init(void) 535{ 536 u64 limit; 537 unsigned int i; 538 539 /* 540 * Emergency stacks must be under 256MB, we cannot afford to take 541 * SLB misses on them. The ABI also requires them to be 128-byte 542 * aligned. 543 * 544 * Since we use these as temporary stacks during secondary CPU 545 * bringup, we need to get at them in real mode. This means they 546 * must also be within the RMO region. 547 */ 548 limit = min(safe_stack_limit(), ppc64_rma_size); 549 550 for_each_possible_cpu(i) { 551 unsigned long sp; 552 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 553 sp += THREAD_SIZE; 554 paca[i].emergency_sp = __va(sp); 555 } 556} 557 558/* 559 * Called into from start_kernel this initializes bootmem, which is used 560 * to manage page allocation until mem_init is called. 561 */ 562void __init setup_arch(char **cmdline_p) 563{ 564 ppc64_boot_msg(0x12, "Setup Arch"); 565 566 *cmdline_p = cmd_line; 567 568 /* 569 * Set cache line size based on type of cpu as a default. 570 * Systems with OF can look in the properties on the cpu node(s) 571 * for a possibly more accurate value. 572 */ 573 dcache_bsize = ppc64_caches.dline_size; 574 icache_bsize = ppc64_caches.iline_size; 575 576 /* reboot on panic */ 577 panic_timeout = 180; 578 579 if (ppc_md.panic) 580 setup_panic(); 581 582 init_mm.start_code = (unsigned long)_stext; 583 init_mm.end_code = (unsigned long) _etext; 584 init_mm.end_data = (unsigned long) _edata; 585 init_mm.brk = klimit; 586#ifdef CONFIG_PPC_64K_PAGES 587 init_mm.context.pte_frag = NULL; 588#endif 589 irqstack_early_init(); 590 exc_lvl_early_init(); 591 emergency_stack_init(); 592 593#ifdef CONFIG_PPC_STD_MMU_64 594 stabs_alloc(); 595#endif 596 /* set up the bootmem stuff with available memory */ 597 do_init_bootmem(); 598 sparse_init(); 599 600#ifdef CONFIG_DUMMY_CONSOLE 601 conswitchp = &dummy_con; 602#endif 603 604 if (ppc_md.setup_arch) 605 ppc_md.setup_arch(); 606 607 paging_init(); 608 609 /* Initialize the MMU context management stuff */ 610 mmu_context_init(); 611 612 kvm_linear_init(); 613 614 /* Interrupt code needs to be 64K-aligned */ 615 if ((unsigned long)_stext & 0xffff) 616 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 617 (unsigned long)_stext); 618 619 ppc64_boot_msg(0x15, "Setup Done"); 620} 621 622 623/* ToDo: do something useful if ppc_md is not yet setup. */ 624#define PPC64_LINUX_FUNCTION 0x0f000000 625#define PPC64_IPL_MESSAGE 0xc0000000 626#define PPC64_TERM_MESSAGE 0xb0000000 627 628static void ppc64_do_msg(unsigned int src, const char *msg) 629{ 630 if (ppc_md.progress) { 631 char buf[128]; 632 633 sprintf(buf, "%08X\n", src); 634 ppc_md.progress(buf, 0); 635 snprintf(buf, 128, "%s", msg); 636 ppc_md.progress(buf, 0); 637 } 638} 639 640/* Print a boot progress message. */ 641void ppc64_boot_msg(unsigned int src, const char *msg) 642{ 643 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); 644 printk("[boot]%04x %s\n", src, msg); 645} 646 647#ifdef CONFIG_SMP 648#define PCPU_DYN_SIZE () 649 650static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 651{ 652 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 653 __pa(MAX_DMA_ADDRESS)); 654} 655 656static void __init pcpu_fc_free(void *ptr, size_t size) 657{ 658 free_bootmem(__pa(ptr), size); 659} 660 661static int pcpu_cpu_distance(unsigned int from, unsigned int to) 662{ 663 if (cpu_to_node(from) == cpu_to_node(to)) 664 return LOCAL_DISTANCE; 665 else 666 return REMOTE_DISTANCE; 667} 668 669unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 670EXPORT_SYMBOL(__per_cpu_offset); 671 672void __init setup_per_cpu_areas(void) 673{ 674 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 675 size_t atom_size; 676 unsigned long delta; 677 unsigned int cpu; 678 int rc; 679 680 /* 681 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 682 * to group units. For larger mappings, use 1M atom which 683 * should be large enough to contain a number of units. 684 */ 685 if (mmu_linear_psize == MMU_PAGE_4K) 686 atom_size = PAGE_SIZE; 687 else 688 atom_size = 1 << 20; 689 690 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 691 pcpu_fc_alloc, pcpu_fc_free); 692 if (rc < 0) 693 panic("cannot initialize percpu area (err=%d)", rc); 694 695 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 696 for_each_possible_cpu(cpu) { 697 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 698 paca[cpu].data_offset = __per_cpu_offset[cpu]; 699 } 700} 701#endif 702 703 704#ifdef CONFIG_PPC_INDIRECT_IO 705struct ppc_pci_io ppc_pci_io; 706EXPORT_SYMBOL(ppc_pci_io); 707#endif /* CONFIG_PPC_INDIRECT_IO */ 708 709