setup_64.c revision a944a9c40b81a71609692c4909bb57e1d01f4bb7
1/* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#define DEBUG 14 15#include <linux/export.h> 16#include <linux/string.h> 17#include <linux/sched.h> 18#include <linux/init.h> 19#include <linux/kernel.h> 20#include <linux/reboot.h> 21#include <linux/delay.h> 22#include <linux/initrd.h> 23#include <linux/seq_file.h> 24#include <linux/ioport.h> 25#include <linux/console.h> 26#include <linux/utsname.h> 27#include <linux/tty.h> 28#include <linux/root_dev.h> 29#include <linux/notifier.h> 30#include <linux/cpu.h> 31#include <linux/unistd.h> 32#include <linux/serial.h> 33#include <linux/serial_8250.h> 34#include <linux/bootmem.h> 35#include <linux/pci.h> 36#include <linux/lockdep.h> 37#include <linux/memblock.h> 38#include <linux/hugetlb.h> 39 40#include <asm/io.h> 41#include <asm/kdump.h> 42#include <asm/prom.h> 43#include <asm/processor.h> 44#include <asm/pgtable.h> 45#include <asm/smp.h> 46#include <asm/elf.h> 47#include <asm/machdep.h> 48#include <asm/paca.h> 49#include <asm/time.h> 50#include <asm/cputable.h> 51#include <asm/sections.h> 52#include <asm/btext.h> 53#include <asm/nvram.h> 54#include <asm/setup.h> 55#include <asm/rtas.h> 56#include <asm/iommu.h> 57#include <asm/serial.h> 58#include <asm/cache.h> 59#include <asm/page.h> 60#include <asm/mmu.h> 61#include <asm/firmware.h> 62#include <asm/xmon.h> 63#include <asm/udbg.h> 64#include <asm/kexec.h> 65#include <asm/mmu_context.h> 66#include <asm/code-patching.h> 67#include <asm/kvm_ppc.h> 68#include <asm/hugetlb.h> 69#include <asm/epapr_hcalls.h> 70 71#ifdef DEBUG 72#define DBG(fmt...) udbg_printf(fmt) 73#else 74#define DBG(fmt...) 75#endif 76 77int spinning_secondaries; 78u64 ppc64_pft_size; 79 80/* Pick defaults since we might want to patch instructions 81 * before we've read this from the device tree. 82 */ 83struct ppc64_caches ppc64_caches = { 84 .dline_size = 0x40, 85 .log_dline_size = 6, 86 .iline_size = 0x40, 87 .log_iline_size = 6 88}; 89EXPORT_SYMBOL_GPL(ppc64_caches); 90 91/* 92 * These are used in binfmt_elf.c to put aux entries on the stack 93 * for each elf executable being started. 94 */ 95int dcache_bsize; 96int icache_bsize; 97int ucache_bsize; 98 99#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) 100static void setup_tlb_core_data(void) 101{ 102 int cpu; 103 104 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); 105 106 for_each_possible_cpu(cpu) { 107 int first = cpu_first_thread_sibling(cpu); 108 109 paca[cpu].tcd_ptr = &paca[first].tcd; 110 111 /* 112 * If we have threads, we need either tlbsrx. 113 * or e6500 tablewalk mode, or else TLB handlers 114 * will be racy and could produce duplicate entries. 115 */ 116 if (smt_enabled_at_boot >= 2 && 117 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && 118 book3e_htw_mode != PPC_HTW_E6500) { 119 /* Should we panic instead? */ 120 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", 121 __func__); 122 } 123 } 124} 125#else 126static void setup_tlb_core_data(void) 127{ 128} 129#endif 130 131#ifdef CONFIG_SMP 132 133static char *smt_enabled_cmdline; 134 135/* Look for ibm,smt-enabled OF option */ 136static void check_smt_enabled(void) 137{ 138 struct device_node *dn; 139 const char *smt_option; 140 141 /* Default to enabling all threads */ 142 smt_enabled_at_boot = threads_per_core; 143 144 /* Allow the command line to overrule the OF option */ 145 if (smt_enabled_cmdline) { 146 if (!strcmp(smt_enabled_cmdline, "on")) 147 smt_enabled_at_boot = threads_per_core; 148 else if (!strcmp(smt_enabled_cmdline, "off")) 149 smt_enabled_at_boot = 0; 150 else { 151 long smt; 152 int rc; 153 154 rc = strict_strtol(smt_enabled_cmdline, 10, &smt); 155 if (!rc) 156 smt_enabled_at_boot = 157 min(threads_per_core, (int)smt); 158 } 159 } else { 160 dn = of_find_node_by_path("/options"); 161 if (dn) { 162 smt_option = of_get_property(dn, "ibm,smt-enabled", 163 NULL); 164 165 if (smt_option) { 166 if (!strcmp(smt_option, "on")) 167 smt_enabled_at_boot = threads_per_core; 168 else if (!strcmp(smt_option, "off")) 169 smt_enabled_at_boot = 0; 170 } 171 172 of_node_put(dn); 173 } 174 } 175} 176 177/* Look for smt-enabled= cmdline option */ 178static int __init early_smt_enabled(char *p) 179{ 180 smt_enabled_cmdline = p; 181 return 0; 182} 183early_param("smt-enabled", early_smt_enabled); 184 185#else 186#define check_smt_enabled() 187#endif /* CONFIG_SMP */ 188 189/** Fix up paca fields required for the boot cpu */ 190static void fixup_boot_paca(void) 191{ 192 /* The boot cpu is started */ 193 get_paca()->cpu_start = 1; 194 /* Allow percpu accesses to work until we setup percpu data */ 195 get_paca()->data_offset = 0; 196} 197 198/* 199 * Early initialization entry point. This is called by head.S 200 * with MMU translation disabled. We rely on the "feature" of 201 * the CPU that ignores the top 2 bits of the address in real 202 * mode so we can access kernel globals normally provided we 203 * only toy with things in the RMO region. From here, we do 204 * some early parsing of the device-tree to setup out MEMBLOCK 205 * data structures, and allocate & initialize the hash table 206 * and segment tables so we can start running with translation 207 * enabled. 208 * 209 * It is this function which will call the probe() callback of 210 * the various platform types and copy the matching one to the 211 * global ppc_md structure. Your platform can eventually do 212 * some very early initializations from the probe() routine, but 213 * this is not recommended, be very careful as, for example, the 214 * device-tree is not accessible via normal means at this point. 215 */ 216 217void __init early_setup(unsigned long dt_ptr) 218{ 219 static __initdata struct paca_struct boot_paca; 220 221 /* -------- printk is _NOT_ safe to use here ! ------- */ 222 223 /* Identify CPU type */ 224 identify_cpu(0, mfspr(SPRN_PVR)); 225 226 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 227 initialise_paca(&boot_paca, 0); 228 setup_paca(&boot_paca); 229 fixup_boot_paca(); 230 231 /* Initialize lockdep early or else spinlocks will blow */ 232 lockdep_init(); 233 234 /* -------- printk is now safe to use ------- */ 235 236 /* Enable early debugging if any specified (see udbg.h) */ 237 udbg_early_init(); 238 239 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 240 241 /* 242 * Do early initialization using the flattened device 243 * tree, such as retrieving the physical memory map or 244 * calculating/retrieving the hash table size. 245 */ 246 early_init_devtree(__va(dt_ptr)); 247 248 epapr_paravirt_early_init(); 249 250 /* Now we know the logical id of our boot cpu, setup the paca. */ 251 setup_paca(&paca[boot_cpuid]); 252 fixup_boot_paca(); 253 254 /* Probe the machine type */ 255 probe_machine(); 256 257 setup_kdump_trampoline(); 258 259 DBG("Found, Initializing memory management...\n"); 260 261 /* Initialize the hash table or TLB handling */ 262 early_init_mmu(); 263 264 /* 265 * At this point, we can let interrupts switch to virtual mode 266 * (the MMU has been setup), so adjust the MSR in the PACA to 267 * have IR and DR set. 268 */ 269 get_paca()->kernel_msr = MSR_KERNEL; 270 271 /* Reserve large chunks of memory for use by CMA for KVM */ 272 kvm_cma_reserve(); 273 274 /* 275 * Reserve any gigantic pages requested on the command line. 276 * memblock needs to have been initialized by the time this is 277 * called since this will reserve memory. 278 */ 279 reserve_hugetlb_gpages(); 280 281 DBG(" <- early_setup()\n"); 282 283#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX 284 /* 285 * This needs to be done *last* (after the above DBG() even) 286 * 287 * Right after we return from this function, we turn on the MMU 288 * which means the real-mode access trick that btext does will 289 * no longer work, it needs to switch to using a real MMU 290 * mapping. This call will ensure that it does 291 */ 292 btext_map(); 293#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ 294} 295 296#ifdef CONFIG_SMP 297void early_setup_secondary(void) 298{ 299 /* Mark interrupts enabled in PACA */ 300 get_paca()->soft_enabled = 0; 301 302 /* Initialize the hash table or TLB handling */ 303 early_init_mmu_secondary(); 304 305 /* 306 * At this point, we can let interrupts switch to virtual mode 307 * (the MMU has been setup), so adjust the MSR in the PACA to 308 * have IR and DR set. 309 */ 310 get_paca()->kernel_msr = MSR_KERNEL; 311} 312 313#endif /* CONFIG_SMP */ 314 315#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 316void smp_release_cpus(void) 317{ 318 unsigned long *ptr; 319 int i; 320 321 DBG(" -> smp_release_cpus()\n"); 322 323 /* All secondary cpus are spinning on a common spinloop, release them 324 * all now so they can start to spin on their individual paca 325 * spinloops. For non SMP kernels, the secondary cpus never get out 326 * of the common spinloop. 327 */ 328 329 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 330 - PHYSICAL_START); 331 *ptr = __pa(generic_secondary_smp_init); 332 333 /* And wait a bit for them to catch up */ 334 for (i = 0; i < 100000; i++) { 335 mb(); 336 HMT_low(); 337 if (spinning_secondaries == 0) 338 break; 339 udelay(1); 340 } 341 DBG("spinning_secondaries = %d\n", spinning_secondaries); 342 343 DBG(" <- smp_release_cpus()\n"); 344} 345#endif /* CONFIG_SMP || CONFIG_KEXEC */ 346 347/* 348 * Initialize some remaining members of the ppc64_caches and systemcfg 349 * structures 350 * (at least until we get rid of them completely). This is mostly some 351 * cache informations about the CPU that will be used by cache flush 352 * routines and/or provided to userland 353 */ 354static void __init initialize_cache_info(void) 355{ 356 struct device_node *np; 357 unsigned long num_cpus = 0; 358 359 DBG(" -> initialize_cache_info()\n"); 360 361 for_each_node_by_type(np, "cpu") { 362 num_cpus += 1; 363 364 /* 365 * We're assuming *all* of the CPUs have the same 366 * d-cache and i-cache sizes... -Peter 367 */ 368 if (num_cpus == 1) { 369 const __be32 *sizep, *lsizep; 370 u32 size, lsize; 371 372 size = 0; 373 lsize = cur_cpu_spec->dcache_bsize; 374 sizep = of_get_property(np, "d-cache-size", NULL); 375 if (sizep != NULL) 376 size = be32_to_cpu(*sizep); 377 lsizep = of_get_property(np, "d-cache-block-size", 378 NULL); 379 /* fallback if block size missing */ 380 if (lsizep == NULL) 381 lsizep = of_get_property(np, 382 "d-cache-line-size", 383 NULL); 384 if (lsizep != NULL) 385 lsize = be32_to_cpu(*lsizep); 386 if (sizep == NULL || lsizep == NULL) 387 DBG("Argh, can't find dcache properties ! " 388 "sizep: %p, lsizep: %p\n", sizep, lsizep); 389 390 ppc64_caches.dsize = size; 391 ppc64_caches.dline_size = lsize; 392 ppc64_caches.log_dline_size = __ilog2(lsize); 393 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 394 395 size = 0; 396 lsize = cur_cpu_spec->icache_bsize; 397 sizep = of_get_property(np, "i-cache-size", NULL); 398 if (sizep != NULL) 399 size = be32_to_cpu(*sizep); 400 lsizep = of_get_property(np, "i-cache-block-size", 401 NULL); 402 if (lsizep == NULL) 403 lsizep = of_get_property(np, 404 "i-cache-line-size", 405 NULL); 406 if (lsizep != NULL) 407 lsize = be32_to_cpu(*lsizep); 408 if (sizep == NULL || lsizep == NULL) 409 DBG("Argh, can't find icache properties ! " 410 "sizep: %p, lsizep: %p\n", sizep, lsizep); 411 412 ppc64_caches.isize = size; 413 ppc64_caches.iline_size = lsize; 414 ppc64_caches.log_iline_size = __ilog2(lsize); 415 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 416 } 417 } 418 419 DBG(" <- initialize_cache_info()\n"); 420} 421 422 423/* 424 * Do some initial setup of the system. The parameters are those which 425 * were passed in from the bootloader. 426 */ 427void __init setup_system(void) 428{ 429 DBG(" -> setup_system()\n"); 430 431 /* Apply the CPUs-specific and firmware specific fixups to kernel 432 * text (nop out sections not relevant to this CPU or this firmware) 433 */ 434 do_feature_fixups(cur_cpu_spec->cpu_features, 435 &__start___ftr_fixup, &__stop___ftr_fixup); 436 do_feature_fixups(cur_cpu_spec->mmu_features, 437 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 438 do_feature_fixups(powerpc_firmware_features, 439 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 440 do_lwsync_fixups(cur_cpu_spec->cpu_features, 441 &__start___lwsync_fixup, &__stop___lwsync_fixup); 442 do_final_fixups(); 443 444 /* 445 * Unflatten the device-tree passed by prom_init or kexec 446 */ 447 unflatten_device_tree(); 448 449 /* 450 * Fill the ppc64_caches & systemcfg structures with informations 451 * retrieved from the device-tree. 452 */ 453 initialize_cache_info(); 454 455#ifdef CONFIG_PPC_RTAS 456 /* 457 * Initialize RTAS if available 458 */ 459 rtas_initialize(); 460#endif /* CONFIG_PPC_RTAS */ 461 462 /* 463 * Check if we have an initrd provided via the device-tree 464 */ 465 check_for_initrd(); 466 467 /* 468 * Do some platform specific early initializations, that includes 469 * setting up the hash table pointers. It also sets up some interrupt-mapping 470 * related options that will be used by finish_device_tree() 471 */ 472 if (ppc_md.init_early) 473 ppc_md.init_early(); 474 475 /* 476 * We can discover serial ports now since the above did setup the 477 * hash table management for us, thus ioremap works. We do that early 478 * so that further code can be debugged 479 */ 480 find_legacy_serial_ports(); 481 482 /* 483 * Register early console 484 */ 485 register_early_udbg_console(); 486 487 /* 488 * Initialize xmon 489 */ 490 xmon_setup(); 491 492 smp_setup_cpu_maps(); 493 check_smt_enabled(); 494 setup_tlb_core_data(); 495 496#ifdef CONFIG_SMP 497 /* Release secondary cpus out of their spinloops at 0x60 now that 498 * we can map physical -> logical CPU ids 499 */ 500 smp_release_cpus(); 501#endif 502 503 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 504 505 printk("-----------------------------------------------------\n"); 506 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 507 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); 508 if (ppc64_caches.dline_size != 0x80) 509 printk("ppc64_caches.dcache_line_size = 0x%x\n", 510 ppc64_caches.dline_size); 511 if (ppc64_caches.iline_size != 0x80) 512 printk("ppc64_caches.icache_line_size = 0x%x\n", 513 ppc64_caches.iline_size); 514#ifdef CONFIG_PPC_STD_MMU_64 515 if (htab_address) 516 printk("htab_address = 0x%p\n", htab_address); 517 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 518#endif /* CONFIG_PPC_STD_MMU_64 */ 519 if (PHYSICAL_START > 0) 520 printk("physical_start = 0x%llx\n", 521 (unsigned long long)PHYSICAL_START); 522 printk("-----------------------------------------------------\n"); 523 524 DBG(" <- setup_system()\n"); 525} 526 527/* This returns the limit below which memory accesses to the linear 528 * mapping are guarnateed not to cause a TLB or SLB miss. This is 529 * used to allocate interrupt or emergency stacks for which our 530 * exception entry path doesn't deal with being interrupted. 531 */ 532static u64 safe_stack_limit(void) 533{ 534#ifdef CONFIG_PPC_BOOK3E 535 /* Freescale BookE bolts the entire linear mapping */ 536 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 537 return linear_map_top; 538 /* Other BookE, we assume the first GB is bolted */ 539 return 1ul << 30; 540#else 541 /* BookS, the first segment is bolted */ 542 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 543 return 1UL << SID_SHIFT_1T; 544 return 1UL << SID_SHIFT; 545#endif 546} 547 548static void __init irqstack_early_init(void) 549{ 550 u64 limit = safe_stack_limit(); 551 unsigned int i; 552 553 /* 554 * Interrupt stacks must be in the first segment since we 555 * cannot afford to take SLB misses on them. 556 */ 557 for_each_possible_cpu(i) { 558 softirq_ctx[i] = (struct thread_info *) 559 __va(memblock_alloc_base(THREAD_SIZE, 560 THREAD_SIZE, limit)); 561 hardirq_ctx[i] = (struct thread_info *) 562 __va(memblock_alloc_base(THREAD_SIZE, 563 THREAD_SIZE, limit)); 564 } 565} 566 567#ifdef CONFIG_PPC_BOOK3E 568static void __init exc_lvl_early_init(void) 569{ 570 unsigned int i; 571 unsigned long sp; 572 573 for_each_possible_cpu(i) { 574 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 575 critirq_ctx[i] = (struct thread_info *)__va(sp); 576 paca[i].crit_kstack = __va(sp + THREAD_SIZE); 577 578 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 579 dbgirq_ctx[i] = (struct thread_info *)__va(sp); 580 paca[i].dbg_kstack = __va(sp + THREAD_SIZE); 581 582 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); 583 mcheckirq_ctx[i] = (struct thread_info *)__va(sp); 584 paca[i].mc_kstack = __va(sp + THREAD_SIZE); 585 } 586 587 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 588 patch_exception(0x040, exc_debug_debug_book3e); 589} 590#else 591#define exc_lvl_early_init() 592#endif 593 594/* 595 * Stack space used when we detect a bad kernel stack pointer, and 596 * early in SMP boots before relocation is enabled. Exclusive emergency 597 * stack for machine checks. 598 */ 599static void __init emergency_stack_init(void) 600{ 601 u64 limit; 602 unsigned int i; 603 604 /* 605 * Emergency stacks must be under 256MB, we cannot afford to take 606 * SLB misses on them. The ABI also requires them to be 128-byte 607 * aligned. 608 * 609 * Since we use these as temporary stacks during secondary CPU 610 * bringup, we need to get at them in real mode. This means they 611 * must also be within the RMO region. 612 */ 613 limit = min(safe_stack_limit(), ppc64_rma_size); 614 615 for_each_possible_cpu(i) { 616 unsigned long sp; 617 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 618 sp += THREAD_SIZE; 619 paca[i].emergency_sp = __va(sp); 620 621#ifdef CONFIG_PPC_BOOK3S_64 622 /* emergency stack for machine check exception handling. */ 623 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 624 sp += THREAD_SIZE; 625 paca[i].mc_emergency_sp = __va(sp); 626#endif 627 } 628} 629 630/* 631 * Called into from start_kernel this initializes bootmem, which is used 632 * to manage page allocation until mem_init is called. 633 */ 634void __init setup_arch(char **cmdline_p) 635{ 636 ppc64_boot_msg(0x12, "Setup Arch"); 637 638 *cmdline_p = cmd_line; 639 640 /* 641 * Set cache line size based on type of cpu as a default. 642 * Systems with OF can look in the properties on the cpu node(s) 643 * for a possibly more accurate value. 644 */ 645 dcache_bsize = ppc64_caches.dline_size; 646 icache_bsize = ppc64_caches.iline_size; 647 648 if (ppc_md.panic) 649 setup_panic(); 650 651 init_mm.start_code = (unsigned long)_stext; 652 init_mm.end_code = (unsigned long) _etext; 653 init_mm.end_data = (unsigned long) _edata; 654 init_mm.brk = klimit; 655#ifdef CONFIG_PPC_64K_PAGES 656 init_mm.context.pte_frag = NULL; 657#endif 658 irqstack_early_init(); 659 exc_lvl_early_init(); 660 emergency_stack_init(); 661 662#ifdef CONFIG_PPC_STD_MMU_64 663 stabs_alloc(); 664#endif 665 /* set up the bootmem stuff with available memory */ 666 do_init_bootmem(); 667 sparse_init(); 668 669#ifdef CONFIG_DUMMY_CONSOLE 670 conswitchp = &dummy_con; 671#endif 672 673 if (ppc_md.setup_arch) 674 ppc_md.setup_arch(); 675 676 paging_init(); 677 678 /* Initialize the MMU context management stuff */ 679 mmu_context_init(); 680 681 /* Interrupt code needs to be 64K-aligned */ 682 if ((unsigned long)_stext & 0xffff) 683 panic("Kernelbase not 64K-aligned (0x%lx)!\n", 684 (unsigned long)_stext); 685 686 ppc64_boot_msg(0x15, "Setup Done"); 687} 688 689 690/* ToDo: do something useful if ppc_md is not yet setup. */ 691#define PPC64_LINUX_FUNCTION 0x0f000000 692#define PPC64_IPL_MESSAGE 0xc0000000 693#define PPC64_TERM_MESSAGE 0xb0000000 694 695static void ppc64_do_msg(unsigned int src, const char *msg) 696{ 697 if (ppc_md.progress) { 698 char buf[128]; 699 700 sprintf(buf, "%08X\n", src); 701 ppc_md.progress(buf, 0); 702 snprintf(buf, 128, "%s", msg); 703 ppc_md.progress(buf, 0); 704 } 705} 706 707/* Print a boot progress message. */ 708void ppc64_boot_msg(unsigned int src, const char *msg) 709{ 710 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); 711 printk("[boot]%04x %s\n", src, msg); 712} 713 714#ifdef CONFIG_SMP 715#define PCPU_DYN_SIZE () 716 717static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 718{ 719 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 720 __pa(MAX_DMA_ADDRESS)); 721} 722 723static void __init pcpu_fc_free(void *ptr, size_t size) 724{ 725 free_bootmem(__pa(ptr), size); 726} 727 728static int pcpu_cpu_distance(unsigned int from, unsigned int to) 729{ 730 if (cpu_to_node(from) == cpu_to_node(to)) 731 return LOCAL_DISTANCE; 732 else 733 return REMOTE_DISTANCE; 734} 735 736unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 737EXPORT_SYMBOL(__per_cpu_offset); 738 739void __init setup_per_cpu_areas(void) 740{ 741 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 742 size_t atom_size; 743 unsigned long delta; 744 unsigned int cpu; 745 int rc; 746 747 /* 748 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 749 * to group units. For larger mappings, use 1M atom which 750 * should be large enough to contain a number of units. 751 */ 752 if (mmu_linear_psize == MMU_PAGE_4K) 753 atom_size = PAGE_SIZE; 754 else 755 atom_size = 1 << 20; 756 757 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 758 pcpu_fc_alloc, pcpu_fc_free); 759 if (rc < 0) 760 panic("cannot initialize percpu area (err=%d)", rc); 761 762 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 763 for_each_possible_cpu(cpu) { 764 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 765 paca[cpu].data_offset = __per_cpu_offset[cpu]; 766 } 767} 768#endif 769 770 771#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 772struct ppc_pci_io ppc_pci_io; 773EXPORT_SYMBOL(ppc_pci_io); 774#endif 775