setup_64.c revision d36b4c4f3cc6caae6d4a12d9f995513e4c3acdd5
1/* 2 * 3 * Common boot and setup code. 4 * 5 * Copyright (C) 2001 PPC64 Team, IBM Corp 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13#undef DEBUG 14 15#include <linux/module.h> 16#include <linux/string.h> 17#include <linux/sched.h> 18#include <linux/init.h> 19#include <linux/kernel.h> 20#include <linux/reboot.h> 21#include <linux/delay.h> 22#include <linux/initrd.h> 23#include <linux/seq_file.h> 24#include <linux/ioport.h> 25#include <linux/console.h> 26#include <linux/utsname.h> 27#include <linux/tty.h> 28#include <linux/root_dev.h> 29#include <linux/notifier.h> 30#include <linux/cpu.h> 31#include <linux/unistd.h> 32#include <linux/serial.h> 33#include <linux/serial_8250.h> 34#include <linux/bootmem.h> 35#include <linux/pci.h> 36#include <linux/lockdep.h> 37#include <linux/memblock.h> 38#include <asm/io.h> 39#include <asm/kdump.h> 40#include <asm/prom.h> 41#include <asm/processor.h> 42#include <asm/pgtable.h> 43#include <asm/smp.h> 44#include <asm/elf.h> 45#include <asm/machdep.h> 46#include <asm/paca.h> 47#include <asm/time.h> 48#include <asm/cputable.h> 49#include <asm/sections.h> 50#include <asm/btext.h> 51#include <asm/nvram.h> 52#include <asm/setup.h> 53#include <asm/system.h> 54#include <asm/rtas.h> 55#include <asm/iommu.h> 56#include <asm/serial.h> 57#include <asm/cache.h> 58#include <asm/page.h> 59#include <asm/mmu.h> 60#include <asm/firmware.h> 61#include <asm/xmon.h> 62#include <asm/udbg.h> 63#include <asm/kexec.h> 64#include <asm/mmu_context.h> 65#include <asm/code-patching.h> 66 67#include "setup.h" 68 69#ifdef DEBUG 70#define DBG(fmt...) udbg_printf(fmt) 71#else 72#define DBG(fmt...) 73#endif 74 75int boot_cpuid = 0; 76int __initdata boot_cpu_count; 77u64 ppc64_pft_size; 78 79/* Pick defaults since we might want to patch instructions 80 * before we've read this from the device tree. 81 */ 82struct ppc64_caches ppc64_caches = { 83 .dline_size = 0x40, 84 .log_dline_size = 6, 85 .iline_size = 0x40, 86 .log_iline_size = 6 87}; 88EXPORT_SYMBOL_GPL(ppc64_caches); 89 90/* 91 * These are used in binfmt_elf.c to put aux entries on the stack 92 * for each elf executable being started. 93 */ 94int dcache_bsize; 95int icache_bsize; 96int ucache_bsize; 97 98#ifdef CONFIG_SMP 99 100static char *smt_enabled_cmdline; 101 102/* Look for ibm,smt-enabled OF option */ 103static void check_smt_enabled(void) 104{ 105 struct device_node *dn; 106 const char *smt_option; 107 108 /* Default to enabling all threads */ 109 smt_enabled_at_boot = threads_per_core; 110 111 /* Allow the command line to overrule the OF option */ 112 if (smt_enabled_cmdline) { 113 if (!strcmp(smt_enabled_cmdline, "on")) 114 smt_enabled_at_boot = threads_per_core; 115 else if (!strcmp(smt_enabled_cmdline, "off")) 116 smt_enabled_at_boot = 0; 117 else { 118 long smt; 119 int rc; 120 121 rc = strict_strtol(smt_enabled_cmdline, 10, &smt); 122 if (!rc) 123 smt_enabled_at_boot = 124 min(threads_per_core, (int)smt); 125 } 126 } else { 127 dn = of_find_node_by_path("/options"); 128 if (dn) { 129 smt_option = of_get_property(dn, "ibm,smt-enabled", 130 NULL); 131 132 if (smt_option) { 133 if (!strcmp(smt_option, "on")) 134 smt_enabled_at_boot = threads_per_core; 135 else if (!strcmp(smt_option, "off")) 136 smt_enabled_at_boot = 0; 137 } 138 139 of_node_put(dn); 140 } 141 } 142} 143 144/* Look for smt-enabled= cmdline option */ 145static int __init early_smt_enabled(char *p) 146{ 147 smt_enabled_cmdline = p; 148 return 0; 149} 150early_param("smt-enabled", early_smt_enabled); 151 152#else 153#define check_smt_enabled() 154#endif /* CONFIG_SMP */ 155 156/* 157 * Early initialization entry point. This is called by head.S 158 * with MMU translation disabled. We rely on the "feature" of 159 * the CPU that ignores the top 2 bits of the address in real 160 * mode so we can access kernel globals normally provided we 161 * only toy with things in the RMO region. From here, we do 162 * some early parsing of the device-tree to setup out MEMBLOCK 163 * data structures, and allocate & initialize the hash table 164 * and segment tables so we can start running with translation 165 * enabled. 166 * 167 * It is this function which will call the probe() callback of 168 * the various platform types and copy the matching one to the 169 * global ppc_md structure. Your platform can eventually do 170 * some very early initializations from the probe() routine, but 171 * this is not recommended, be very careful as, for example, the 172 * device-tree is not accessible via normal means at this point. 173 */ 174 175void __init early_setup(unsigned long dt_ptr) 176{ 177 /* -------- printk is _NOT_ safe to use here ! ------- */ 178 179 /* Identify CPU type */ 180 identify_cpu(0, mfspr(SPRN_PVR)); 181 182 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ 183 initialise_paca(&boot_paca, 0); 184 setup_paca(&boot_paca); 185 186 /* Initialize lockdep early or else spinlocks will blow */ 187 lockdep_init(); 188 189 /* -------- printk is now safe to use ------- */ 190 191 /* Enable early debugging if any specified (see udbg.h) */ 192 udbg_early_init(); 193 194 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); 195 196 /* 197 * Do early initialization using the flattened device 198 * tree, such as retrieving the physical memory map or 199 * calculating/retrieving the hash table size. 200 */ 201 early_init_devtree(__va(dt_ptr)); 202 203 /* Now we know the logical id of our boot cpu, setup the paca. */ 204 setup_paca(&paca[boot_cpuid]); 205 206 /* Fix up paca fields required for the boot cpu */ 207 get_paca()->cpu_start = 1; 208 209 /* Probe the machine type */ 210 probe_machine(); 211 212 setup_kdump_trampoline(); 213 214 DBG("Found, Initializing memory management...\n"); 215 216 /* Initialize the hash table or TLB handling */ 217 early_init_mmu(); 218 219 DBG(" <- early_setup()\n"); 220} 221 222#ifdef CONFIG_SMP 223void early_setup_secondary(void) 224{ 225 /* Mark interrupts enabled in PACA */ 226 get_paca()->soft_enabled = 0; 227 228 /* Initialize the hash table or TLB handling */ 229 early_init_mmu_secondary(); 230} 231 232#endif /* CONFIG_SMP */ 233 234#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) 235void smp_release_cpus(void) 236{ 237 unsigned long *ptr; 238 int i; 239 240 DBG(" -> smp_release_cpus()\n"); 241 242 /* All secondary cpus are spinning on a common spinloop, release them 243 * all now so they can start to spin on their individual paca 244 * spinloops. For non SMP kernels, the secondary cpus never get out 245 * of the common spinloop. 246 */ 247 248 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop 249 - PHYSICAL_START); 250 *ptr = __pa(generic_secondary_smp_init); 251 252 /* And wait a bit for them to catch up */ 253 for (i = 0; i < 100000; i++) { 254 mb(); 255 HMT_low(); 256 if (boot_cpu_count == 0) 257 break; 258 udelay(1); 259 } 260 DBG("boot_cpu_count = %d\n", boot_cpu_count); 261 262 DBG(" <- smp_release_cpus()\n"); 263} 264#endif /* CONFIG_SMP || CONFIG_KEXEC */ 265 266/* 267 * Initialize some remaining members of the ppc64_caches and systemcfg 268 * structures 269 * (at least until we get rid of them completely). This is mostly some 270 * cache informations about the CPU that will be used by cache flush 271 * routines and/or provided to userland 272 */ 273static void __init initialize_cache_info(void) 274{ 275 struct device_node *np; 276 unsigned long num_cpus = 0; 277 278 DBG(" -> initialize_cache_info()\n"); 279 280 for (np = NULL; (np = of_find_node_by_type(np, "cpu"));) { 281 num_cpus += 1; 282 283 /* We're assuming *all* of the CPUs have the same 284 * d-cache and i-cache sizes... -Peter 285 */ 286 287 if ( num_cpus == 1 ) { 288 const u32 *sizep, *lsizep; 289 u32 size, lsize; 290 291 size = 0; 292 lsize = cur_cpu_spec->dcache_bsize; 293 sizep = of_get_property(np, "d-cache-size", NULL); 294 if (sizep != NULL) 295 size = *sizep; 296 lsizep = of_get_property(np, "d-cache-block-size", NULL); 297 /* fallback if block size missing */ 298 if (lsizep == NULL) 299 lsizep = of_get_property(np, "d-cache-line-size", NULL); 300 if (lsizep != NULL) 301 lsize = *lsizep; 302 if (sizep == 0 || lsizep == 0) 303 DBG("Argh, can't find dcache properties ! " 304 "sizep: %p, lsizep: %p\n", sizep, lsizep); 305 306 ppc64_caches.dsize = size; 307 ppc64_caches.dline_size = lsize; 308 ppc64_caches.log_dline_size = __ilog2(lsize); 309 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; 310 311 size = 0; 312 lsize = cur_cpu_spec->icache_bsize; 313 sizep = of_get_property(np, "i-cache-size", NULL); 314 if (sizep != NULL) 315 size = *sizep; 316 lsizep = of_get_property(np, "i-cache-block-size", NULL); 317 if (lsizep == NULL) 318 lsizep = of_get_property(np, "i-cache-line-size", NULL); 319 if (lsizep != NULL) 320 lsize = *lsizep; 321 if (sizep == 0 || lsizep == 0) 322 DBG("Argh, can't find icache properties ! " 323 "sizep: %p, lsizep: %p\n", sizep, lsizep); 324 325 ppc64_caches.isize = size; 326 ppc64_caches.iline_size = lsize; 327 ppc64_caches.log_iline_size = __ilog2(lsize); 328 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; 329 } 330 } 331 332 DBG(" <- initialize_cache_info()\n"); 333} 334 335 336/* 337 * Do some initial setup of the system. The parameters are those which 338 * were passed in from the bootloader. 339 */ 340void __init setup_system(void) 341{ 342 DBG(" -> setup_system()\n"); 343 344 /* Apply the CPUs-specific and firmware specific fixups to kernel 345 * text (nop out sections not relevant to this CPU or this firmware) 346 */ 347 do_feature_fixups(cur_cpu_spec->cpu_features, 348 &__start___ftr_fixup, &__stop___ftr_fixup); 349 do_feature_fixups(cur_cpu_spec->mmu_features, 350 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); 351 do_feature_fixups(powerpc_firmware_features, 352 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); 353 do_lwsync_fixups(cur_cpu_spec->cpu_features, 354 &__start___lwsync_fixup, &__stop___lwsync_fixup); 355 356 /* 357 * Unflatten the device-tree passed by prom_init or kexec 358 */ 359 unflatten_device_tree(); 360 361 /* 362 * Fill the ppc64_caches & systemcfg structures with informations 363 * retrieved from the device-tree. 364 */ 365 initialize_cache_info(); 366 367#ifdef CONFIG_PPC_RTAS 368 /* 369 * Initialize RTAS if available 370 */ 371 rtas_initialize(); 372#endif /* CONFIG_PPC_RTAS */ 373 374 /* 375 * Check if we have an initrd provided via the device-tree 376 */ 377 check_for_initrd(); 378 379 /* 380 * Do some platform specific early initializations, that includes 381 * setting up the hash table pointers. It also sets up some interrupt-mapping 382 * related options that will be used by finish_device_tree() 383 */ 384 if (ppc_md.init_early) 385 ppc_md.init_early(); 386 387 /* 388 * We can discover serial ports now since the above did setup the 389 * hash table management for us, thus ioremap works. We do that early 390 * so that further code can be debugged 391 */ 392 find_legacy_serial_ports(); 393 394 /* 395 * Register early console 396 */ 397 register_early_udbg_console(); 398 399 /* 400 * Initialize xmon 401 */ 402 xmon_setup(); 403 404 smp_setup_cpu_maps(); 405 check_smt_enabled(); 406 407#ifdef CONFIG_SMP 408 /* Release secondary cpus out of their spinloops at 0x60 now that 409 * we can map physical -> logical CPU ids 410 */ 411 smp_release_cpus(); 412#endif 413 414 printk("Starting Linux PPC64 %s\n", init_utsname()->version); 415 416 printk("-----------------------------------------------------\n"); 417 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); 418 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); 419 if (ppc64_caches.dline_size != 0x80) 420 printk("ppc64_caches.dcache_line_size = 0x%x\n", 421 ppc64_caches.dline_size); 422 if (ppc64_caches.iline_size != 0x80) 423 printk("ppc64_caches.icache_line_size = 0x%x\n", 424 ppc64_caches.iline_size); 425#ifdef CONFIG_PPC_STD_MMU_64 426 if (htab_address) 427 printk("htab_address = 0x%p\n", htab_address); 428 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); 429#endif /* CONFIG_PPC_STD_MMU_64 */ 430 if (PHYSICAL_START > 0) 431 printk("physical_start = 0x%llx\n", 432 (unsigned long long)PHYSICAL_START); 433 printk("-----------------------------------------------------\n"); 434 435 DBG(" <- setup_system()\n"); 436} 437 438/* This returns the limit below which memory accesses to the linear 439 * mapping are guarnateed not to cause a TLB or SLB miss. This is 440 * used to allocate interrupt or emergency stacks for which our 441 * exception entry path doesn't deal with being interrupted. 442 */ 443static u64 safe_stack_limit(void) 444{ 445#ifdef CONFIG_PPC_BOOK3E 446 /* Freescale BookE bolts the entire linear mapping */ 447 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) 448 return linear_map_top; 449 /* Other BookE, we assume the first GB is bolted */ 450 return 1ul << 30; 451#else 452 /* BookS, the first segment is bolted */ 453 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) 454 return 1UL << SID_SHIFT_1T; 455 return 1UL << SID_SHIFT; 456#endif 457} 458 459static void __init irqstack_early_init(void) 460{ 461 u64 limit = safe_stack_limit(); 462 unsigned int i; 463 464 /* 465 * Interrupt stacks must be in the first segment since we 466 * cannot afford to take SLB misses on them. 467 */ 468 for_each_possible_cpu(i) { 469 softirq_ctx[i] = (struct thread_info *) 470 __va(memblock_alloc_base(THREAD_SIZE, 471 THREAD_SIZE, limit)); 472 hardirq_ctx[i] = (struct thread_info *) 473 __va(memblock_alloc_base(THREAD_SIZE, 474 THREAD_SIZE, limit)); 475 } 476} 477 478#ifdef CONFIG_PPC_BOOK3E 479static void __init exc_lvl_early_init(void) 480{ 481 extern unsigned int interrupt_base_book3e; 482 extern unsigned int exc_debug_debug_book3e; 483 484 unsigned int i; 485 486 for_each_possible_cpu(i) { 487 critirq_ctx[i] = (struct thread_info *) 488 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 489 dbgirq_ctx[i] = (struct thread_info *) 490 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 491 mcheckirq_ctx[i] = (struct thread_info *) 492 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 493 } 494 495 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) 496 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1, 497 (unsigned long)&exc_debug_debug_book3e, 0); 498} 499#else 500#define exc_lvl_early_init() 501#endif 502 503/* 504 * Stack space used when we detect a bad kernel stack pointer, and 505 * early in SMP boots before relocation is enabled. 506 */ 507static void __init emergency_stack_init(void) 508{ 509 u64 limit; 510 unsigned int i; 511 512 /* 513 * Emergency stacks must be under 256MB, we cannot afford to take 514 * SLB misses on them. The ABI also requires them to be 128-byte 515 * aligned. 516 * 517 * Since we use these as temporary stacks during secondary CPU 518 * bringup, we need to get at them in real mode. This means they 519 * must also be within the RMO region. 520 */ 521 limit = min(safe_stack_limit(), ppc64_rma_size); 522 523 for_each_possible_cpu(i) { 524 unsigned long sp; 525 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); 526 sp += THREAD_SIZE; 527 paca[i].emergency_sp = __va(sp); 528 } 529} 530 531/* 532 * Called into from start_kernel this initializes bootmem, which is used 533 * to manage page allocation until mem_init is called. 534 */ 535void __init setup_arch(char **cmdline_p) 536{ 537 ppc64_boot_msg(0x12, "Setup Arch"); 538 539 *cmdline_p = cmd_line; 540 541 /* 542 * Set cache line size based on type of cpu as a default. 543 * Systems with OF can look in the properties on the cpu node(s) 544 * for a possibly more accurate value. 545 */ 546 dcache_bsize = ppc64_caches.dline_size; 547 icache_bsize = ppc64_caches.iline_size; 548 549 /* reboot on panic */ 550 panic_timeout = 180; 551 552 if (ppc_md.panic) 553 setup_panic(); 554 555 init_mm.start_code = (unsigned long)_stext; 556 init_mm.end_code = (unsigned long) _etext; 557 init_mm.end_data = (unsigned long) _edata; 558 init_mm.brk = klimit; 559 560 irqstack_early_init(); 561 exc_lvl_early_init(); 562 emergency_stack_init(); 563 564#ifdef CONFIG_PPC_STD_MMU_64 565 stabs_alloc(); 566#endif 567 /* set up the bootmem stuff with available memory */ 568 do_init_bootmem(); 569 sparse_init(); 570 571#ifdef CONFIG_DUMMY_CONSOLE 572 conswitchp = &dummy_con; 573#endif 574 575 if (ppc_md.setup_arch) 576 ppc_md.setup_arch(); 577 578 paging_init(); 579 580 /* Initialize the MMU context management stuff */ 581 mmu_context_init(); 582 583 ppc64_boot_msg(0x15, "Setup Done"); 584} 585 586 587/* ToDo: do something useful if ppc_md is not yet setup. */ 588#define PPC64_LINUX_FUNCTION 0x0f000000 589#define PPC64_IPL_MESSAGE 0xc0000000 590#define PPC64_TERM_MESSAGE 0xb0000000 591 592static void ppc64_do_msg(unsigned int src, const char *msg) 593{ 594 if (ppc_md.progress) { 595 char buf[128]; 596 597 sprintf(buf, "%08X\n", src); 598 ppc_md.progress(buf, 0); 599 snprintf(buf, 128, "%s", msg); 600 ppc_md.progress(buf, 0); 601 } 602} 603 604/* Print a boot progress message. */ 605void ppc64_boot_msg(unsigned int src, const char *msg) 606{ 607 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); 608 printk("[boot]%04x %s\n", src, msg); 609} 610 611#ifdef CONFIG_SMP 612#define PCPU_DYN_SIZE () 613 614static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) 615{ 616 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, 617 __pa(MAX_DMA_ADDRESS)); 618} 619 620static void __init pcpu_fc_free(void *ptr, size_t size) 621{ 622 free_bootmem(__pa(ptr), size); 623} 624 625static int pcpu_cpu_distance(unsigned int from, unsigned int to) 626{ 627 if (cpu_to_node(from) == cpu_to_node(to)) 628 return LOCAL_DISTANCE; 629 else 630 return REMOTE_DISTANCE; 631} 632 633unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; 634EXPORT_SYMBOL(__per_cpu_offset); 635 636void __init setup_per_cpu_areas(void) 637{ 638 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; 639 size_t atom_size; 640 unsigned long delta; 641 unsigned int cpu; 642 int rc; 643 644 /* 645 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need 646 * to group units. For larger mappings, use 1M atom which 647 * should be large enough to contain a number of units. 648 */ 649 if (mmu_linear_psize == MMU_PAGE_4K) 650 atom_size = PAGE_SIZE; 651 else 652 atom_size = 1 << 20; 653 654 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, 655 pcpu_fc_alloc, pcpu_fc_free); 656 if (rc < 0) 657 panic("cannot initialize percpu area (err=%d)", rc); 658 659 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; 660 for_each_possible_cpu(cpu) { 661 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; 662 paca[cpu].data_offset = __per_cpu_offset[cpu]; 663 } 664} 665#endif 666 667 668#ifdef CONFIG_PPC_INDIRECT_IO 669struct ppc_pci_io ppc_pci_io; 670EXPORT_SYMBOL(ppc_pci_io); 671#endif /* CONFIG_PPC_INDIRECT_IO */ 672 673