iommu.c revision 4f3dd8a06239c0a19d772a27c2f618dc2faadf4a
1/* 2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 3 * 4 * Rewrite, cleanup: 5 * 6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net> 8 * 9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 27#include <linux/init.h> 28#include <linux/types.h> 29#include <linux/slab.h> 30#include <linux/mm.h> 31#include <linux/spinlock.h> 32#include <linux/string.h> 33#include <linux/pci.h> 34#include <linux/dma-mapping.h> 35#include <asm/io.h> 36#include <asm/prom.h> 37#include <asm/rtas.h> 38#include <asm/iommu.h> 39#include <asm/pci-bridge.h> 40#include <asm/machdep.h> 41#include <asm/abs_addr.h> 42#include <asm/pSeries_reconfig.h> 43#include <asm/firmware.h> 44#include <asm/tce.h> 45#include <asm/ppc-pci.h> 46#include <asm/udbg.h> 47 48#include "plpar_wrappers.h" 49 50 51static void tce_build_pSeries(struct iommu_table *tbl, long index, 52 long npages, unsigned long uaddr, 53 enum dma_data_direction direction, 54 struct dma_attrs *attrs) 55{ 56 u64 proto_tce; 57 u64 *tcep; 58 u64 rpn; 59 60 proto_tce = TCE_PCI_READ; // Read allowed 61 62 if (direction != DMA_TO_DEVICE) 63 proto_tce |= TCE_PCI_WRITE; 64 65 tcep = ((u64 *)tbl->it_base) + index; 66 67 while (npages--) { 68 /* can't move this out since we might cross LMB boundary */ 69 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 70 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 71 72 uaddr += TCE_PAGE_SIZE; 73 tcep++; 74 } 75} 76 77 78static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) 79{ 80 u64 *tcep; 81 82 tcep = ((u64 *)tbl->it_base) + index; 83 84 while (npages--) 85 *(tcep++) = 0; 86} 87 88static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) 89{ 90 u64 *tcep; 91 92 tcep = ((u64 *)tbl->it_base) + index; 93 94 return *tcep; 95} 96 97static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, 98 long npages, unsigned long uaddr, 99 enum dma_data_direction direction, 100 struct dma_attrs *attrs) 101{ 102 u64 rc; 103 u64 proto_tce, tce; 104 u64 rpn; 105 106 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 107 proto_tce = TCE_PCI_READ; 108 if (direction != DMA_TO_DEVICE) 109 proto_tce |= TCE_PCI_WRITE; 110 111 while (npages--) { 112 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 113 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); 114 115 if (rc && printk_ratelimit()) { 116 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 117 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 118 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 119 printk("\ttce val = 0x%lx\n", tce ); 120 show_stack(current, (unsigned long *)__get_SP()); 121 } 122 123 tcenum++; 124 rpn++; 125 } 126} 127 128static DEFINE_PER_CPU(u64 *, tce_page) = NULL; 129 130static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 131 long npages, unsigned long uaddr, 132 enum dma_data_direction direction, 133 struct dma_attrs *attrs) 134{ 135 u64 rc; 136 u64 proto_tce; 137 u64 *tcep; 138 u64 rpn; 139 long l, limit; 140 141 if (npages == 1) { 142 tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, 143 direction, attrs); 144 return; 145 } 146 147 tcep = __get_cpu_var(tce_page); 148 149 /* This is safe to do since interrupts are off when we're called 150 * from iommu_alloc{,_sg}() 151 */ 152 if (!tcep) { 153 tcep = (u64 *)__get_free_page(GFP_ATOMIC); 154 /* If allocation fails, fall back to the loop implementation */ 155 if (!tcep) { 156 tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, 157 direction, attrs); 158 return; 159 } 160 __get_cpu_var(tce_page) = tcep; 161 } 162 163 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 164 proto_tce = TCE_PCI_READ; 165 if (direction != DMA_TO_DEVICE) 166 proto_tce |= TCE_PCI_WRITE; 167 168 /* We can map max one pageful of TCEs at a time */ 169 do { 170 /* 171 * Set up the page with TCE data, looping through and setting 172 * the values. 173 */ 174 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); 175 176 for (l = 0; l < limit; l++) { 177 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 178 rpn++; 179 } 180 181 rc = plpar_tce_put_indirect((u64)tbl->it_index, 182 (u64)tcenum << 12, 183 (u64)virt_to_abs(tcep), 184 limit); 185 186 npages -= limit; 187 tcenum += limit; 188 } while (npages > 0 && !rc); 189 190 if (rc && printk_ratelimit()) { 191 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 192 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 193 printk("\tnpages = 0x%lx\n", (u64)npages); 194 printk("\ttce[0] val = 0x%lx\n", tcep[0]); 195 show_stack(current, (unsigned long *)__get_SP()); 196 } 197} 198 199static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 200{ 201 u64 rc; 202 203 while (npages--) { 204 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); 205 206 if (rc && printk_ratelimit()) { 207 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 208 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 209 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 210 show_stack(current, (unsigned long *)__get_SP()); 211 } 212 213 tcenum++; 214 } 215} 216 217 218static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 219{ 220 u64 rc; 221 222 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); 223 224 if (rc && printk_ratelimit()) { 225 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); 226 printk("\trc = %ld\n", rc); 227 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 228 printk("\tnpages = 0x%lx\n", (u64)npages); 229 show_stack(current, (unsigned long *)__get_SP()); 230 } 231} 232 233static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) 234{ 235 u64 rc; 236 unsigned long tce_ret; 237 238 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); 239 240 if (rc && printk_ratelimit()) { 241 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n", 242 rc); 243 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 244 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 245 show_stack(current, (unsigned long *)__get_SP()); 246 } 247 248 return tce_ret; 249} 250 251#ifdef CONFIG_PCI 252static void iommu_table_setparms(struct pci_controller *phb, 253 struct device_node *dn, 254 struct iommu_table *tbl) 255{ 256 struct device_node *node; 257 const unsigned long *basep; 258 const u32 *sizep; 259 260 node = phb->dn; 261 262 basep = of_get_property(node, "linux,tce-base", NULL); 263 sizep = of_get_property(node, "linux,tce-size", NULL); 264 if (basep == NULL || sizep == NULL) { 265 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " 266 "missing tce entries !\n", dn->full_name); 267 return; 268 } 269 270 tbl->it_base = (unsigned long)__va(*basep); 271 272#ifndef CONFIG_CRASH_DUMP 273 memset((void *)tbl->it_base, 0, *sizep); 274#endif 275 276 tbl->it_busno = phb->bus->number; 277 278 /* Units of tce entries */ 279 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; 280 281 /* Test if we are going over 2GB of DMA space */ 282 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { 283 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 284 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 285 } 286 287 phb->dma_window_base_cur += phb->dma_window_size; 288 289 /* Set the tce table size - measured in entries */ 290 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; 291 292 tbl->it_index = 0; 293 tbl->it_blocksize = 16; 294 tbl->it_type = TCE_PCI; 295} 296 297/* 298 * iommu_table_setparms_lpar 299 * 300 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. 301 */ 302static void iommu_table_setparms_lpar(struct pci_controller *phb, 303 struct device_node *dn, 304 struct iommu_table *tbl, 305 const void *dma_window, 306 int bussubno) 307{ 308 unsigned long offset, size; 309 310 tbl->it_busno = bussubno; 311 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); 312 313 tbl->it_base = 0; 314 tbl->it_blocksize = 16; 315 tbl->it_type = TCE_PCI; 316 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; 317 tbl->it_size = size >> IOMMU_PAGE_SHIFT; 318} 319 320static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) 321{ 322 struct device_node *dn; 323 struct iommu_table *tbl; 324 struct device_node *isa_dn, *isa_dn_orig; 325 struct device_node *tmp; 326 struct pci_dn *pci; 327 int children; 328 329 dn = pci_bus_to_OF_node(bus); 330 331 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); 332 333 if (bus->self) { 334 /* This is not a root bus, any setup will be done for the 335 * device-side of the bridge in iommu_dev_setup_pSeries(). 336 */ 337 return; 338 } 339 pci = PCI_DN(dn); 340 341 /* Check if the ISA bus on the system is under 342 * this PHB. 343 */ 344 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); 345 346 while (isa_dn && isa_dn != dn) 347 isa_dn = isa_dn->parent; 348 349 if (isa_dn_orig) 350 of_node_put(isa_dn_orig); 351 352 /* Count number of direct PCI children of the PHB. */ 353 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) 354 children++; 355 356 pr_debug("Children: %d\n", children); 357 358 /* Calculate amount of DMA window per slot. Each window must be 359 * a power of two (due to pci_alloc_consistent requirements). 360 * 361 * Keep 256MB aside for PHBs with ISA. 362 */ 363 364 if (!isa_dn) { 365 /* No ISA/IDE - just set window size and return */ 366 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ 367 368 while (pci->phb->dma_window_size * children > 0x80000000ul) 369 pci->phb->dma_window_size >>= 1; 370 pr_debug("No ISA/IDE, window size is 0x%lx\n", 371 pci->phb->dma_window_size); 372 pci->phb->dma_window_base_cur = 0; 373 374 return; 375 } 376 377 /* If we have ISA, then we probably have an IDE 378 * controller too. Allocate a 128MB table but 379 * skip the first 128MB to avoid stepping on ISA 380 * space. 381 */ 382 pci->phb->dma_window_size = 0x8000000ul; 383 pci->phb->dma_window_base_cur = 0x8000000ul; 384 385 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 386 pci->phb->node); 387 388 iommu_table_setparms(pci->phb, dn, tbl); 389 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 390 391 /* Divide the rest (1.75GB) among the children */ 392 pci->phb->dma_window_size = 0x80000000ul; 393 while (pci->phb->dma_window_size * children > 0x70000000ul) 394 pci->phb->dma_window_size >>= 1; 395 396 pr_debug("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); 397} 398 399 400static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) 401{ 402 struct iommu_table *tbl; 403 struct device_node *dn, *pdn; 404 struct pci_dn *ppci; 405 const void *dma_window = NULL; 406 407 dn = pci_bus_to_OF_node(bus); 408 409 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", 410 dn->full_name); 411 412 /* Find nearest ibm,dma-window, walking up the device tree */ 413 for (pdn = dn; pdn != NULL; pdn = pdn->parent) { 414 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 415 if (dma_window != NULL) 416 break; 417 } 418 419 if (dma_window == NULL) { 420 pr_debug(" no ibm,dma-window property !\n"); 421 return; 422 } 423 424 ppci = PCI_DN(pdn); 425 426 pr_debug(" parent is %s, iommu_table: 0x%p\n", 427 pdn->full_name, ppci->iommu_table); 428 429 if (!ppci->iommu_table) { 430 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 431 ppci->phb->node); 432 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window, 433 bus->number); 434 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); 435 pr_debug(" created table: %p\n", ppci->iommu_table); 436 } 437 438 if (pdn != dn) 439 PCI_DN(dn)->iommu_table = ppci->iommu_table; 440} 441 442 443static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) 444{ 445 struct device_node *dn; 446 struct iommu_table *tbl; 447 448 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); 449 450 dn = dev->dev.archdata.of_node; 451 452 /* If we're the direct child of a root bus, then we need to allocate 453 * an iommu table ourselves. The bus setup code should have setup 454 * the window sizes already. 455 */ 456 if (!dev->bus->self) { 457 struct pci_controller *phb = PCI_DN(dn)->phb; 458 459 pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); 460 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 461 phb->node); 462 iommu_table_setparms(phb, dn, tbl); 463 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); 464 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; 465 return; 466 } 467 468 /* If this device is further down the bus tree, search upwards until 469 * an already allocated iommu table is found and use that. 470 */ 471 472 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) 473 dn = dn->parent; 474 475 if (dn && PCI_DN(dn)) 476 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; 477 else 478 printk(KERN_WARNING "iommu: Device %s has no iommu table\n", 479 pci_name(dev)); 480} 481 482static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) 483{ 484 struct device_node *pdn, *dn; 485 struct iommu_table *tbl; 486 const void *dma_window = NULL; 487 struct pci_dn *pci; 488 489 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); 490 491 /* dev setup for LPAR is a little tricky, since the device tree might 492 * contain the dma-window properties per-device and not neccesarily 493 * for the bus. So we need to search upwards in the tree until we 494 * either hit a dma-window property, OR find a parent with a table 495 * already allocated. 496 */ 497 dn = pci_device_to_OF_node(dev); 498 pr_debug(" node is %s\n", dn->full_name); 499 500 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; 501 pdn = pdn->parent) { 502 dma_window = of_get_property(pdn, "ibm,dma-window", NULL); 503 if (dma_window) 504 break; 505 } 506 507 if (!pdn || !PCI_DN(pdn)) { 508 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " 509 "no DMA window found for pci dev=%s dn=%s\n", 510 pci_name(dev), dn? dn->full_name : "<null>"); 511 return; 512 } 513 pr_debug(" parent is %s\n", pdn->full_name); 514 515 /* Check for parent == NULL so we don't try to setup the empty EADS 516 * slots on POWER4 machines. 517 */ 518 if (dma_window == NULL || pdn->parent == NULL) { 519 pr_debug(" no dma window for device, linking to parent\n"); 520 dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; 521 return; 522 } 523 524 pci = PCI_DN(pdn); 525 if (!pci->iommu_table) { 526 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 527 pci->phb->node); 528 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window, 529 pci->phb->bus->number); 530 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 531 pr_debug(" created table: %p\n", pci->iommu_table); 532 } else { 533 pr_debug(" found DMA window, table: %p\n", pci->iommu_table); 534 } 535 536 dev->dev.archdata.dma_data = pci->iommu_table; 537} 538#else /* CONFIG_PCI */ 539#define pci_dma_bus_setup_pSeries NULL 540#define pci_dma_dev_setup_pSeries NULL 541#define pci_dma_bus_setup_pSeriesLP NULL 542#define pci_dma_dev_setup_pSeriesLP NULL 543#endif /* !CONFIG_PCI */ 544 545static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) 546{ 547 int err = NOTIFY_OK; 548 struct device_node *np = node; 549 struct pci_dn *pci = PCI_DN(np); 550 551 switch (action) { 552 case PSERIES_RECONFIG_REMOVE: 553 if (pci && pci->iommu_table && 554 of_get_property(np, "ibm,dma-window", NULL)) 555 iommu_free_table(pci->iommu_table, np->full_name); 556 break; 557 default: 558 err = NOTIFY_DONE; 559 break; 560 } 561 return err; 562} 563 564static struct notifier_block iommu_reconfig_nb = { 565 .notifier_call = iommu_reconfig_notifier, 566}; 567 568/* These are called very early. */ 569void iommu_init_early_pSeries(void) 570{ 571 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) { 572 /* Direct I/O, IOMMU off */ 573 ppc_md.pci_dma_dev_setup = NULL; 574 ppc_md.pci_dma_bus_setup = NULL; 575 set_pci_dma_ops(&dma_direct_ops); 576 return; 577 } 578 579 if (firmware_has_feature(FW_FEATURE_LPAR)) { 580 if (firmware_has_feature(FW_FEATURE_MULTITCE)) { 581 ppc_md.tce_build = tce_buildmulti_pSeriesLP; 582 ppc_md.tce_free = tce_freemulti_pSeriesLP; 583 } else { 584 ppc_md.tce_build = tce_build_pSeriesLP; 585 ppc_md.tce_free = tce_free_pSeriesLP; 586 } 587 ppc_md.tce_get = tce_get_pSeriesLP; 588 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; 589 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; 590 } else { 591 ppc_md.tce_build = tce_build_pSeries; 592 ppc_md.tce_free = tce_free_pSeries; 593 ppc_md.tce_get = tce_get_pseries; 594 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; 595 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; 596 } 597 598 599 pSeries_reconfig_notifier_register(&iommu_reconfig_nb); 600 601 set_pci_dma_ops(&dma_iommu_ops); 602} 603 604