iommu.c revision 77319254f109963213f33cbb15e0103f2e81a64a
1/* 2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 3 * 4 * Rewrite, cleanup: 5 * 6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net> 8 * 9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 27#include <linux/init.h> 28#include <linux/types.h> 29#include <linux/slab.h> 30#include <linux/mm.h> 31#include <linux/spinlock.h> 32#include <linux/string.h> 33#include <linux/pci.h> 34#include <linux/dma-mapping.h> 35#include <asm/io.h> 36#include <asm/prom.h> 37#include <asm/rtas.h> 38#include <asm/iommu.h> 39#include <asm/pci-bridge.h> 40#include <asm/machdep.h> 41#include <asm/abs_addr.h> 42#include <asm/pSeries_reconfig.h> 43#include <asm/firmware.h> 44#include <asm/tce.h> 45#include <asm/ppc-pci.h> 46#include <asm/udbg.h> 47 48#include "plpar_wrappers.h" 49 50#define DBG(fmt...) 51 52static void tce_build_pSeries(struct iommu_table *tbl, long index, 53 long npages, unsigned long uaddr, 54 enum dma_data_direction direction) 55{ 56 u64 proto_tce; 57 u64 *tcep; 58 u64 rpn; 59 60 proto_tce = TCE_PCI_READ; // Read allowed 61 62 if (direction != DMA_TO_DEVICE) 63 proto_tce |= TCE_PCI_WRITE; 64 65 tcep = ((u64 *)tbl->it_base) + index; 66 67 while (npages--) { 68 /* can't move this out since we might cross LMB boundary */ 69 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 70 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 71 72 uaddr += TCE_PAGE_SIZE; 73 tcep++; 74 } 75} 76 77 78static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) 79{ 80 u64 *tcep; 81 82 tcep = ((u64 *)tbl->it_base) + index; 83 84 while (npages--) 85 *(tcep++) = 0; 86} 87 88static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) 89{ 90 u64 *tcep; 91 92 tcep = ((u64 *)tbl->it_base) + index; 93 94 return *tcep; 95} 96 97static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum, 98 long npages, unsigned long uaddr, 99 enum dma_data_direction direction) 100{ 101 u64 rc; 102 u64 proto_tce, tce; 103 u64 rpn; 104 105 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 106 proto_tce = TCE_PCI_READ; 107 if (direction != DMA_TO_DEVICE) 108 proto_tce |= TCE_PCI_WRITE; 109 110 while (npages--) { 111 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 112 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce); 113 114 if (rc && printk_ratelimit()) { 115 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 116 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 117 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 118 printk("\ttce val = 0x%lx\n", tce ); 119 show_stack(current, (unsigned long *)__get_SP()); 120 } 121 122 tcenum++; 123 rpn++; 124 } 125} 126 127static DEFINE_PER_CPU(u64 *, tce_page) = NULL; 128 129static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 130 long npages, unsigned long uaddr, 131 enum dma_data_direction direction) 132{ 133 u64 rc; 134 u64 proto_tce; 135 u64 *tcep; 136 u64 rpn; 137 long l, limit; 138 139 if (npages == 1) 140 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr, 141 direction); 142 143 tcep = __get_cpu_var(tce_page); 144 145 /* This is safe to do since interrupts are off when we're called 146 * from iommu_alloc{,_sg}() 147 */ 148 if (!tcep) { 149 tcep = (u64 *)__get_free_page(GFP_ATOMIC); 150 /* If allocation fails, fall back to the loop implementation */ 151 if (!tcep) 152 return tce_build_pSeriesLP(tbl, tcenum, npages, 153 uaddr, direction); 154 __get_cpu_var(tce_page) = tcep; 155 } 156 157 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT; 158 proto_tce = TCE_PCI_READ; 159 if (direction != DMA_TO_DEVICE) 160 proto_tce |= TCE_PCI_WRITE; 161 162 /* We can map max one pageful of TCEs at a time */ 163 do { 164 /* 165 * Set up the page with TCE data, looping through and setting 166 * the values. 167 */ 168 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE); 169 170 for (l = 0; l < limit; l++) { 171 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT; 172 rpn++; 173 } 174 175 rc = plpar_tce_put_indirect((u64)tbl->it_index, 176 (u64)tcenum << 12, 177 (u64)virt_to_abs(tcep), 178 limit); 179 180 npages -= limit; 181 tcenum += limit; 182 } while (npages > 0 && !rc); 183 184 if (rc && printk_ratelimit()) { 185 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 186 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 187 printk("\tnpages = 0x%lx\n", (u64)npages); 188 printk("\ttce[0] val = 0x%lx\n", tcep[0]); 189 show_stack(current, (unsigned long *)__get_SP()); 190 } 191} 192 193static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 194{ 195 u64 rc; 196 197 while (npages--) { 198 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0); 199 200 if (rc && printk_ratelimit()) { 201 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc); 202 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 203 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 204 show_stack(current, (unsigned long *)__get_SP()); 205 } 206 207 tcenum++; 208 } 209} 210 211 212static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 213{ 214 u64 rc; 215 216 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages); 217 218 if (rc && printk_ratelimit()) { 219 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); 220 printk("\trc = %ld\n", rc); 221 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 222 printk("\tnpages = 0x%lx\n", (u64)npages); 223 show_stack(current, (unsigned long *)__get_SP()); 224 } 225} 226 227static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) 228{ 229 u64 rc; 230 unsigned long tce_ret; 231 232 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret); 233 234 if (rc && printk_ratelimit()) { 235 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n", 236 rc); 237 printk("\tindex = 0x%lx\n", (u64)tbl->it_index); 238 printk("\ttcenum = 0x%lx\n", (u64)tcenum); 239 show_stack(current, (unsigned long *)__get_SP()); 240 } 241 242 return tce_ret; 243} 244 245static void iommu_table_setparms(struct pci_controller *phb, 246 struct device_node *dn, 247 struct iommu_table *tbl) 248{ 249 struct device_node *node; 250 const unsigned long *basep; 251 const u32 *sizep; 252 253 node = (struct device_node *)phb->arch_data; 254 255 basep = get_property(node, "linux,tce-base", NULL); 256 sizep = get_property(node, "linux,tce-size", NULL); 257 if (basep == NULL || sizep == NULL) { 258 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has " 259 "missing tce entries !\n", dn->full_name); 260 return; 261 } 262 263 tbl->it_base = (unsigned long)__va(*basep); 264 265#ifndef CONFIG_CRASH_DUMP 266 memset((void *)tbl->it_base, 0, *sizep); 267#endif 268 269 tbl->it_busno = phb->bus->number; 270 271 /* Units of tce entries */ 272 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT; 273 274 /* Test if we are going over 2GB of DMA space */ 275 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) { 276 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 277 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 278 } 279 280 phb->dma_window_base_cur += phb->dma_window_size; 281 282 /* Set the tce table size - measured in entries */ 283 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT; 284 285 tbl->it_index = 0; 286 tbl->it_blocksize = 16; 287 tbl->it_type = TCE_PCI; 288} 289 290/* 291 * iommu_table_setparms_lpar 292 * 293 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus. 294 */ 295static void iommu_table_setparms_lpar(struct pci_controller *phb, 296 struct device_node *dn, 297 struct iommu_table *tbl, 298 const void *dma_window) 299{ 300 unsigned long offset, size; 301 302 tbl->it_busno = PCI_DN(dn)->bussubno; 303 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size); 304 305 tbl->it_base = 0; 306 tbl->it_blocksize = 16; 307 tbl->it_type = TCE_PCI; 308 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT; 309 tbl->it_size = size >> IOMMU_PAGE_SHIFT; 310} 311 312static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) 313{ 314 struct device_node *dn; 315 struct iommu_table *tbl; 316 struct device_node *isa_dn, *isa_dn_orig; 317 struct device_node *tmp; 318 struct pci_dn *pci; 319 int children; 320 321 dn = pci_bus_to_OF_node(bus); 322 323 DBG("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name); 324 325 if (bus->self) { 326 /* This is not a root bus, any setup will be done for the 327 * device-side of the bridge in iommu_dev_setup_pSeries(). 328 */ 329 return; 330 } 331 pci = PCI_DN(dn); 332 333 /* Check if the ISA bus on the system is under 334 * this PHB. 335 */ 336 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); 337 338 while (isa_dn && isa_dn != dn) 339 isa_dn = isa_dn->parent; 340 341 if (isa_dn_orig) 342 of_node_put(isa_dn_orig); 343 344 /* Count number of direct PCI children of the PHB. */ 345 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) 346 children++; 347 348 DBG("Children: %d\n", children); 349 350 /* Calculate amount of DMA window per slot. Each window must be 351 * a power of two (due to pci_alloc_consistent requirements). 352 * 353 * Keep 256MB aside for PHBs with ISA. 354 */ 355 356 if (!isa_dn) { 357 /* No ISA/IDE - just set window size and return */ 358 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ 359 360 while (pci->phb->dma_window_size * children > 0x80000000ul) 361 pci->phb->dma_window_size >>= 1; 362 DBG("No ISA/IDE, window size is 0x%lx\n", 363 pci->phb->dma_window_size); 364 pci->phb->dma_window_base_cur = 0; 365 366 return; 367 } 368 369 /* If we have ISA, then we probably have an IDE 370 * controller too. Allocate a 128MB table but 371 * skip the first 128MB to avoid stepping on ISA 372 * space. 373 */ 374 pci->phb->dma_window_size = 0x8000000ul; 375 pci->phb->dma_window_base_cur = 0x8000000ul; 376 377 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 378 pci->phb->node); 379 380 iommu_table_setparms(pci->phb, dn, tbl); 381 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 382 383 /* Divide the rest (1.75GB) among the children */ 384 pci->phb->dma_window_size = 0x80000000ul; 385 while (pci->phb->dma_window_size * children > 0x70000000ul) 386 pci->phb->dma_window_size >>= 1; 387 388 DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size); 389 390} 391 392 393static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) 394{ 395 struct iommu_table *tbl; 396 struct device_node *dn, *pdn; 397 struct pci_dn *ppci; 398 const void *dma_window = NULL; 399 400 dn = pci_bus_to_OF_node(bus); 401 402 DBG("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", dn->full_name); 403 404 /* Find nearest ibm,dma-window, walking up the device tree */ 405 for (pdn = dn; pdn != NULL; pdn = pdn->parent) { 406 dma_window = get_property(pdn, "ibm,dma-window", NULL); 407 if (dma_window != NULL) 408 break; 409 } 410 411 if (dma_window == NULL) { 412 DBG(" no ibm,dma-window property !\n"); 413 return; 414 } 415 416 ppci = PCI_DN(pdn); 417 418 DBG(" parent is %s, iommu_table: 0x%p\n", 419 pdn->full_name, ppci->iommu_table); 420 421 if (!ppci->iommu_table) { 422 /* Bussubno hasn't been copied yet. 423 * Do it now because iommu_table_setparms_lpar needs it. 424 */ 425 426 ppci->bussubno = bus->number; 427 428 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 429 ppci->phb->node); 430 431 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window); 432 433 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node); 434 DBG(" created table: %p\n", ppci->iommu_table); 435 } 436 437 if (pdn != dn) 438 PCI_DN(dn)->iommu_table = ppci->iommu_table; 439} 440 441 442static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) 443{ 444 struct device_node *dn; 445 struct iommu_table *tbl; 446 447 DBG("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); 448 449 dn = dev->dev.archdata.of_node; 450 451 /* If we're the direct child of a root bus, then we need to allocate 452 * an iommu table ourselves. The bus setup code should have setup 453 * the window sizes already. 454 */ 455 if (!dev->bus->self) { 456 struct pci_controller *phb = PCI_DN(dn)->phb; 457 458 DBG(" --> first child, no bridge. Allocating iommu table.\n"); 459 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 460 phb->node); 461 iommu_table_setparms(phb, dn, tbl); 462 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node); 463 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; 464 return; 465 } 466 467 /* If this device is further down the bus tree, search upwards until 468 * an already allocated iommu table is found and use that. 469 */ 470 471 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL) 472 dn = dn->parent; 473 474 if (dn && PCI_DN(dn)) 475 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table; 476 else 477 printk(KERN_WARNING "iommu: Device %s has no iommu table\n", 478 pci_name(dev)); 479} 480 481static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) 482{ 483 int err = NOTIFY_OK; 484 struct device_node *np = node; 485 struct pci_dn *pci = PCI_DN(np); 486 487 switch (action) { 488 case PSERIES_RECONFIG_REMOVE: 489 if (pci && pci->iommu_table && 490 get_property(np, "ibm,dma-window", NULL)) 491 iommu_free_table(np); 492 break; 493 default: 494 err = NOTIFY_DONE; 495 break; 496 } 497 return err; 498} 499 500static struct notifier_block iommu_reconfig_nb = { 501 .notifier_call = iommu_reconfig_notifier, 502}; 503 504static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) 505{ 506 struct device_node *pdn, *dn; 507 struct iommu_table *tbl; 508 const void *dma_window = NULL; 509 struct pci_dn *pci; 510 511 DBG("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); 512 513 /* dev setup for LPAR is a little tricky, since the device tree might 514 * contain the dma-window properties per-device and not neccesarily 515 * for the bus. So we need to search upwards in the tree until we 516 * either hit a dma-window property, OR find a parent with a table 517 * already allocated. 518 */ 519 dn = pci_device_to_OF_node(dev); 520 DBG(" node is %s\n", dn->full_name); 521 522 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; 523 pdn = pdn->parent) { 524 dma_window = get_property(pdn, "ibm,dma-window", NULL); 525 if (dma_window) 526 break; 527 } 528 529 DBG(" parent is %s\n", pdn->full_name); 530 531 /* Check for parent == NULL so we don't try to setup the empty EADS 532 * slots on POWER4 machines. 533 */ 534 if (dma_window == NULL || pdn->parent == NULL) { 535 DBG(" no dma window for device, linking to parent\n"); 536 dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table; 537 return; 538 } 539 DBG(" found DMA window, table: %p\n", pci->iommu_table); 540 541 pci = PCI_DN(pdn); 542 if (!pci->iommu_table) { 543 /* iommu_table_setparms_lpar needs bussubno. */ 544 pci->bussubno = pci->phb->bus->number; 545 546 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL, 547 pci->phb->node); 548 549 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window); 550 551 pci->iommu_table = iommu_init_table(tbl, pci->phb->node); 552 DBG(" created table: %p\n", pci->iommu_table); 553 } 554 555 dev->dev.archdata.dma_data = pci->iommu_table; 556} 557 558/* These are called very early. */ 559void iommu_init_early_pSeries(void) 560{ 561 if (of_chosen && get_property(of_chosen, "linux,iommu-off", NULL)) { 562 /* Direct I/O, IOMMU off */ 563 ppc_md.pci_dma_dev_setup = NULL; 564 ppc_md.pci_dma_bus_setup = NULL; 565 pci_dma_ops = &dma_direct_ops; 566 return; 567 } 568 569 if (firmware_has_feature(FW_FEATURE_LPAR)) { 570 if (firmware_has_feature(FW_FEATURE_MULTITCE)) { 571 ppc_md.tce_build = tce_buildmulti_pSeriesLP; 572 ppc_md.tce_free = tce_freemulti_pSeriesLP; 573 } else { 574 ppc_md.tce_build = tce_build_pSeriesLP; 575 ppc_md.tce_free = tce_free_pSeriesLP; 576 } 577 ppc_md.tce_get = tce_get_pSeriesLP; 578 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; 579 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; 580 } else { 581 ppc_md.tce_build = tce_build_pSeries; 582 ppc_md.tce_free = tce_free_pSeries; 583 ppc_md.tce_get = tce_get_pseries; 584 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries; 585 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries; 586 } 587 588 589 pSeries_reconfig_notifier_register(&iommu_reconfig_nb); 590 591 pci_dma_ops = &dma_iommu_ops; 592} 593 594