fsl_pci.c revision 9ac4dd301eebb3cd8de801e02bfc91f296e56f63
1/* 2 * MPC85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007 Freescale Semiconductor, Inc 5 * 6 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 7 * Recode: ZHANG WEI <wei.zhang@freescale.com> 8 * Rewrite the routing for Frescale PCI and PCI Express 9 * Roy Zang <tie-fei.zang@freescale.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16#include <linux/kernel.h> 17#include <linux/pci.h> 18#include <linux/delay.h> 19#include <linux/string.h> 20#include <linux/init.h> 21#include <linux/bootmem.h> 22 23#include <asm/io.h> 24#include <asm/prom.h> 25#include <asm/pci-bridge.h> 26#include <asm/machdep.h> 27#include <sysdev/fsl_soc.h> 28#include <sysdev/fsl_pci.h> 29 30/* atmu setup for fsl pci/pcie controller */ 31void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) 32{ 33 struct ccsr_pci __iomem *pci; 34 int i; 35 36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start, 37 rsrc->end - rsrc->start + 1); 38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 39 40 /* Disable all windows (except powar0 since its ignored) */ 41 for(i = 1; i < 5; i++) 42 out_be32(&pci->pow[i].powar, 0); 43 for(i = 0; i < 3; i++) 44 out_be32(&pci->piw[i].piwar, 0); 45 46 /* Setup outbound MEM window */ 47 for(i = 0; i < 3; i++) 48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){ 49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n", 50 hose->mem_resources[i].start, 51 hose->mem_resources[i].end 52 - hose->mem_resources[i].start + 1); 53 out_be32(&pci->pow[i+1].potar, 54 (hose->mem_resources[i].start >> 12) 55 & 0x000fffff); 56 out_be32(&pci->pow[i+1].potear, 0); 57 out_be32(&pci->pow[i+1].powbar, 58 (hose->mem_resources[i].start >> 12) 59 & 0x000fffff); 60 /* Enable, Mem R/W */ 61 out_be32(&pci->pow[i+1].powar, 0x80044000 62 | (__ilog2(hose->mem_resources[i].end 63 - hose->mem_resources[i].start + 1) - 1)); 64 } 65 66 /* Setup outbound IO window */ 67 if (hose->io_resource.flags & IORESOURCE_IO){ 68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", 69 hose->io_resource.start, 70 hose->io_resource.end - hose->io_resource.start + 1, 71 hose->io_base_phys); 72 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12) 73 & 0x000fffff); 74 out_be32(&pci->pow[i+1].potear, 0); 75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12) 76 & 0x000fffff); 77 /* Enable, IO R/W */ 78 out_be32(&pci->pow[i+1].powar, 0x80088000 79 | (__ilog2(hose->io_resource.end 80 - hose->io_resource.start + 1) - 1)); 81 } 82 83 /* Setup 2G inbound Memory Window @ 1 */ 84 out_be32(&pci->piw[2].pitar, 0x00000000); 85 out_be32(&pci->piw[2].piwbar,0x00000000); 86 out_be32(&pci->piw[2].piwar, PIWAR_2G); 87} 88 89void __init setup_pci_cmd(struct pci_controller *hose) 90{ 91 u16 cmd; 92 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 93 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 94 | PCI_COMMAND_IO; 95 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 96 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 97} 98 99static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev) 100{ 101 struct resource *res; 102 int i, res_idx = PCI_BRIDGE_RESOURCES; 103 struct pci_controller *hose; 104 105 /* 106 * Make the bridge be transparent. 107 */ 108 dev->transparent = 1; 109 110 hose = pci_bus_to_host(dev->bus); 111 if (!hose) { 112 printk(KERN_ERR "Can't find hose for bus %d\n", 113 dev->bus->number); 114 return; 115 } 116 117 if (hose->io_resource.flags) { 118 res = &dev->resource[res_idx++]; 119 res->start = hose->io_resource.start; 120 res->end = hose->io_resource.end; 121 res->flags = hose->io_resource.flags; 122 } 123 124 for (i = 0; i < 3; i++) { 125 res = &dev->resource[res_idx + i]; 126 res->start = hose->mem_resources[i].start; 127 res->end = hose->mem_resources[i].end; 128 res->flags = hose->mem_resources[i].flags; 129 } 130} 131 132int __init fsl_pcie_check_link(struct pci_controller *hose) 133{ 134 u16 val; 135 early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); 136 if (val < PCIE_LTSSM_L0) 137 return 1; 138 return 0; 139} 140 141int __init fsl_add_bridge(struct device_node *dev, int is_primary) 142{ 143 int len; 144 struct pci_controller *hose; 145 struct resource rsrc; 146 const int *bus_range; 147 148 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 149 150 /* Fetch host bridge registers address */ 151 if (of_address_to_resource(dev, 0, &rsrc)) { 152 printk(KERN_WARNING "Can't get pci register base!"); 153 return -ENOMEM; 154 } 155 156 /* Get bus range if any */ 157 bus_range = of_get_property(dev, "bus-range", &len); 158 if (bus_range == NULL || len < 2 * sizeof(int)) 159 printk(KERN_WARNING "Can't get bus-range for %s, assume" 160 " bus 0\n", dev->full_name); 161 162 pci_assign_all_buses = 1; 163 hose = pcibios_alloc_controller(dev); 164 if (!hose) 165 return -ENOMEM; 166 167 hose->first_busno = bus_range ? bus_range[0] : 0x0; 168 hose->last_busno = bus_range ? bus_range[1] : 0xff; 169 170 /* check PCI express bridge */ 171 if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || 172 of_device_is_compatible(dev, "fsl,mpc8641-pcie")) 173 hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG | 174 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 175 176 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); 177 setup_pci_cmd(hose); 178 179 /* check PCI express link status */ 180 if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") || 181 of_device_is_compatible(dev, "fsl,mpc8641-pcie")) 182 if (fsl_pcie_check_link(hose)) 183 return -ENXIO; 184 185 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx." 186 "Firmware bus number: %d->%d\n", 187 (unsigned long long)rsrc.start, hose->first_busno, 188 hose->last_busno); 189 190 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 191 hose, hose->cfg_addr, hose->cfg_data); 192 193 /* Interpret the "ranges" property */ 194 /* This also maps the I/O region and sets isa_io/mem_base */ 195 pci_process_bridge_OF_ranges(hose, dev, is_primary); 196 197 /* Setup PEX window registers */ 198 setup_pci_atmu(hose, &rsrc); 199 200 return 0; 201} 202 203DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); 204DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent); 205