19eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r/* 29eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * MPC85xx/86xx PCI Express structure define 39eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * 4f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha * Copyright 2007,2011 Freescale Semiconductor, Inc 59eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * 69eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * This program is free software; you can redistribute it and/or modify it 79eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * under the terms of the GNU General Public License as published by the 89eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * Free Software Foundation; either version 2 of the License, or (at your 99eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * option) any later version. 109eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * 119eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r */ 129eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 139eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r#ifdef __KERNEL__ 149ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#ifndef __POWERPC_FSL_PCI_H 159ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define __POWERPC_FSL_PCI_H 169eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 17c7417202569ff31c4ddc88811b30925263951da1Jia Hongtaostruct platform_device; 18c7417202569ff31c4ddc88811b30925263951da1Jia Hongtao 19695093e38c3ef63fcb43a2840ed865efa20671d5Varun Sethi 20695093e38c3ef63fcb43a2840ed865efa20671d5Varun Sethi/* FSL PCI controller BRR1 register */ 21695093e38c3ef63fcb43a2840ed865efa20671d5Varun Sethi#define PCI_FSL_BRR1 0xbf8 22695093e38c3ef63fcb43a2840ed865efa20671d5Varun Sethi#define PCI_FSL_BRR1_VER 0xffff 23695093e38c3ef63fcb43a2840ed865efa20671d5Varun Sethi 249ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ 259ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define PCIE_LTSSM_L0 0x16 /* L0 state */ 266cc1b4e931f8d8dccdcdb05b758a7d1178ad6b49Roy Zang#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ 27cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */ 2854c181935d2a2d46a1b2f00cbb25acc35e4f5ee2Kumar Gala#define PIWAR_EN 0x80000000 /* Enable */ 2954c181935d2a2d46a1b2f00cbb25acc35e4f5ee2Kumar Gala#define PIWAR_PF 0x20000000 /* prefetch */ 3054c181935d2a2d46a1b2f00cbb25acc35e4f5ee2Kumar Gala#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 3154c181935d2a2d46a1b2f00cbb25acc35e4f5ee2Kumar Gala#define PIWAR_READ_SNOOP 0x00050000 3254c181935d2a2d46a1b2f00cbb25acc35e4f5ee2Kumar Gala#define PIWAR_WRITE_SNOOP 0x00005000 33f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha#define PIWAR_SZ_MASK 0x0000003f 349eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 3548b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng#define PEX_PMCR_PTOMR 0x1 3648b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng#define PEX_PMCR_EXL2S 0x2 3748b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng 3848b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng#define PME_DISR_EN_PTOD 0x00008000 3948b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng#define PME_DISR_EN_ENL23D 0x00002000 4048b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng#define PME_DISR_EN_EXL23D 0x00001000 4148b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongsheng 429ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express outbound window reg */ 439ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rstruct pci_outbound_window_regs { 449ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 potar; /* 0x.0 - Outbound translation address register */ 459ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 potear; /* 0x.4 - Outbound translation extended address register */ 469ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 powbar; /* 0x.8 - Outbound window base address register */ 479ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res1[4]; 489ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 powar; /* 0x.10 - Outbound window attributes register */ 499ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res2[12]; 509eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r}; 519eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 529ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express inbound window reg */ 539ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rstruct pci_inbound_window_regs { 549ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pitar; /* 0x.0 - Inbound translation address register */ 559ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res1[4]; 569ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 piwbar; /* 0x.8 - Inbound window base address register */ 579ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 piwbear; /* 0x.c - Inbound window base extended address register */ 589ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 piwar; /* 0x.10 - Inbound window attributes register */ 599ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res2[12]; 609ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r}; 619ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 629ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express IO block registers for 85xx/86xx */ 639ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rstruct ccsr_pci { 649ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ 659ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ 669ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ 679ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ 689ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ 69f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */ 70f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */ 71f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha u8 res2[4]; 729ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ 739ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ 749ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ 759ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ 766cc1b4e931f8d8dccdcdb05b758a7d1178ad6b49Roy Zang u8 res3[3016]; 776cc1b4e931f8d8dccdcdb05b758a7d1178ad6b49Roy Zang __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */ 786cc1b4e931f8d8dccdcdb05b758a7d1178ad6b49Roy Zang __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */ 799ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 809ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express outbound window 0-4 819ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * Window 0 is the default window and is the only window enabled upon reset. 829ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * The default outbound register set is used when a transaction misses 839ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * in all of the other outbound windows. 849ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r */ 859ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r struct pci_outbound_window_regs pow[5]; 86f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha u8 res14[96]; 87f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */ 88f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha u8 res6[96]; 89f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha/* PCI/PCI Express inbound window 3-0 909ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * inbound window 1 supports only a 32-bit base address and does not 919ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * define an inbound window base extended address register. 929ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r */ 93f4154e160aa2a40dccc963110768b63ce004fed9Prabhakar Kushwaha struct pci_inbound_window_regs piw[4]; 949ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 959ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ 969ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res21[4]; 979ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ 989ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res22[4]; 999ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ 1009ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res23[12]; 1019ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ 1029ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res24[4]; 1039ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ 1049ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ 1059ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ 1069ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ 107cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG u8 res_e38[200]; 108cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */ 109cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG u8 res_f04[16]; 110cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/ 111cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG#define PEX_CSR0_LTSSM_MASK 0xFC 112cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG#define PEX_CSR0_LTSSM_SHIFT 2 113cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG#define PEX_CSR0_LTSSM_L0 0x11 114cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/ 115cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG u8 res_f1c[228]; 116cc6ea0dd28d450925dd43135647fcb73f171c748Roy ZANG 1179ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r}; 1189ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 11952c5affc545053d37c0b05224bbf70f5336caa20Varun Sethiextern int fsl_add_bridge(struct platform_device *pdev, int is_primary); 1206c0a11c118471f79795202348fbd0e6580341794Kumar Galaextern void fsl_pcibios_fixup_bus(struct pci_bus *bus); 12148b16180d0d91324e5d2423c6d53d97bbe3dcc14Wang Dongshengextern void fsl_pcibios_fixup_phb(struct pci_controller *phb); 12276fe1ffce94067fc82d1d958f826eb9f1df53910John Rigbyextern int mpc83xx_add_bridge(struct device_node *dev); 123b8f44ec2c05f9cfe1647173ac60c0cccb1118c91Kumar Galau64 fsl_pci_immrbar_base(struct pci_controller *hose); 1249ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 12507e4f8014f4d3404de7cdeaba3fe307cc6eecb79Scott Woodextern struct device_node *fsl_pci_primary; 12607e4f8014f4d3404de7cdeaba3fe307cc6eecb79Scott Wood 127905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao#ifdef CONFIG_PCI 128905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtaovoid fsl_pci_assign_primary(void); 12907e4f8014f4d3404de7cdeaba3fe307cc6eecb79Scott Wood#else 130905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtaostatic inline void fsl_pci_assign_primary(void) {} 131905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao#endif 132905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao 133905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao#ifdef CONFIG_EDAC_MPC85XX 134905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtaoint mpc85xx_pci_err_probe(struct platform_device *op); 135905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao#else 136905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtaostatic inline int mpc85xx_pci_err_probe(struct platform_device *op) 137905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao{ 138905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao return -ENOTSUPP; 139905e75c46dba5f3061049277e4eb7110beedba43Jia Hongtao} 14007e4f8014f4d3404de7cdeaba3fe307cc6eecb79Scott Wood#endif 14107e4f8014f4d3404de7cdeaba3fe307cc6eecb79Scott Wood 1424e0e3435b50285eafe5898124ce02f7577f6803aHongtao Jia#ifdef CONFIG_FSL_PCI 1434e0e3435b50285eafe5898124ce02f7577f6803aHongtao Jiaextern int fsl_pci_mcheck_exception(struct pt_regs *); 1444e0e3435b50285eafe5898124ce02f7577f6803aHongtao Jia#else 1454e0e3435b50285eafe5898124ce02f7577f6803aHongtao Jiastatic inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; } 1464e0e3435b50285eafe5898124ce02f7577f6803aHongtao Jia#endif 1474e0e3435b50285eafe5898124ce02f7577f6803aHongtao Jia 1489ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#endif /* __POWERPC_FSL_PCI_H */ 1499eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r#endif /* __KERNEL__ */ 150