fsl_pci.h revision 6c0a11c118471f79795202348fbd0e6580341794
19eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r/* 29eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * MPC85xx/86xx PCI Express structure define 39eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * 49eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * Copyright 2007 Freescale Semiconductor, Inc 59eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * 69eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * This program is free software; you can redistribute it and/or modify it 79eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * under the terms of the GNU General Public License as published by the 89eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * Free Software Foundation; either version 2 of the License, or (at your 99eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * option) any later version. 109eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r * 119eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r */ 129eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 139eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r#ifdef __KERNEL__ 149ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#ifndef __POWERPC_FSL_PCI_H 159ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define __POWERPC_FSL_PCI_H 169eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 179ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ 189ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define PCIE_LTSSM_L0 0x16 /* L0 state */ 199ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ 209eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 219ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express outbound window reg */ 229ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rstruct pci_outbound_window_regs { 239ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 potar; /* 0x.0 - Outbound translation address register */ 249ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 potear; /* 0x.4 - Outbound translation extended address register */ 259ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 powbar; /* 0x.8 - Outbound window base address register */ 269ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res1[4]; 279ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 powar; /* 0x.10 - Outbound window attributes register */ 289ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res2[12]; 299eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r}; 309eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r 319ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express inbound window reg */ 329ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rstruct pci_inbound_window_regs { 339ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pitar; /* 0x.0 - Inbound translation address register */ 349ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res1[4]; 359ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 piwbar; /* 0x.8 - Inbound window base address register */ 369ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 piwbear; /* 0x.c - Inbound window base extended address register */ 379ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 piwar; /* 0x.10 - Inbound window attributes register */ 389ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res2[12]; 399ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r}; 409ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 419ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express IO block registers for 85xx/86xx */ 429ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rstruct ccsr_pci { 439ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ 449ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */ 459ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ 469ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ 479ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ 489ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res2[12]; 499ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ 509ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ 519ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ 529ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */ 539ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res3[3024]; 549ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 559ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express outbound window 0-4 569ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * Window 0 is the default window and is the only window enabled upon reset. 579ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * The default outbound register set is used when a transaction misses 589ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * in all of the other outbound windows. 599ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r */ 609ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r struct pci_outbound_window_regs pow[5]; 619ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 629ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res14[256]; 639ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 649ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r/* PCI/PCI Express inbound window 3-1 659ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * inbound window 1 supports only a 32-bit base address and does not 669ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r * define an inbound window base extended address register. 679ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r */ 689ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r struct pci_inbound_window_regs piw[3]; 699ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 709ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ 719ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res21[4]; 729ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ 739ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res22[4]; 749ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ 759ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res23[12]; 769ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ 779ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r u8 res24[4]; 789ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ 799ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ 809ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ 819ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ 829ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r}; 839ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 849ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-rextern int fsl_add_bridge(struct device_node *dev, int is_primary); 856c0a11c118471f79795202348fbd0e6580341794Kumar Galaextern void fsl_pcibios_fixup_bus(struct pci_bus *bus); 869ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r 879ac4dd301eebb3cd8de801e02bfc91f296e56f63Zang Roy-r#endif /* __POWERPC_FSL_PCI_H */ 889eb90a0c3b333e27db74412833a36da3f27da6a3Zang Roy-r#endif /* __KERNEL__ */ 89