1d1839136098e281ece46520200599ef94edca612Paul Mundt/* 2d1839136098e281ece46520200599ef94edca612Paul Mundt * arch/sh/kernel/cpu/sh5/probe.c 3d1839136098e281ece46520200599ef94edca612Paul Mundt * 4d1839136098e281ece46520200599ef94edca612Paul Mundt * CPU Subtype Probing for SH-5. 5d1839136098e281ece46520200599ef94edca612Paul Mundt * 6d1839136098e281ece46520200599ef94edca612Paul Mundt * Copyright (C) 2000, 2001 Paolo Alberelli 7d1839136098e281ece46520200599ef94edca612Paul Mundt * Copyright (C) 2003 - 2007 Paul Mundt 8d1839136098e281ece46520200599ef94edca612Paul Mundt * 9d1839136098e281ece46520200599ef94edca612Paul Mundt * This file is subject to the terms and conditions of the GNU General Public 10d1839136098e281ece46520200599ef94edca612Paul Mundt * License. See the file "COPYING" in the main directory of this archive 11d1839136098e281ece46520200599ef94edca612Paul Mundt * for more details. 12d1839136098e281ece46520200599ef94edca612Paul Mundt */ 13d1839136098e281ece46520200599ef94edca612Paul Mundt#include <linux/init.h> 14d1839136098e281ece46520200599ef94edca612Paul Mundt#include <linux/io.h> 15d1839136098e281ece46520200599ef94edca612Paul Mundt#include <linux/string.h> 16d1839136098e281ece46520200599ef94edca612Paul Mundt#include <asm/processor.h> 17d1839136098e281ece46520200599ef94edca612Paul Mundt#include <asm/cache.h> 182a6b8148c050941dd61779cb0b49c5c3ea854ebfPaul Mundt#include <asm/tlb.h> 19d1839136098e281ece46520200599ef94edca612Paul Mundt 204603f53a1dc3c76dfba841d123db9fa6204934f5Paul Gortmakervoid cpu_probe(void) 21d1839136098e281ece46520200599ef94edca612Paul Mundt{ 22d1839136098e281ece46520200599ef94edca612Paul Mundt unsigned long long cir; 23d1839136098e281ece46520200599ef94edca612Paul Mundt 2438350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt /* 2538350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * Do peeks in real mode to avoid having to set up a mapping for 2638350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * the WPC registers. On SH5-101 cut2, such a mapping would be 2738350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * exposed to an address translation erratum which would make it 2838350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * hard to set up correctly. 2938350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt */ 30d1839136098e281ece46520200599ef94edca612Paul Mundt cir = peek_real_address_q(0x0d000008); 3138350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt if ((cir & 0xffff) == 0x5103) 32d1839136098e281ece46520200599ef94edca612Paul Mundt boot_cpu_data.type = CPU_SH5_103; 3338350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt else if (((cir >> 32) & 0xffff) == 0x51e2) 34d1839136098e281ece46520200599ef94edca612Paul Mundt /* CPU.VCR aliased at CIR address on SH5-101 */ 35d1839136098e281ece46520200599ef94edca612Paul Mundt boot_cpu_data.type = CPU_SH5_101; 36d1839136098e281ece46520200599ef94edca612Paul Mundt 37e82da214d2fe3dc2610df966100c4f36bc0fad91Paul Mundt boot_cpu_data.family = CPU_FAMILY_SH5; 38e82da214d2fe3dc2610df966100c4f36bc0fad91Paul Mundt 39d1839136098e281ece46520200599ef94edca612Paul Mundt /* 40d1839136098e281ece46520200599ef94edca612Paul Mundt * First, setup some sane values for the I-cache. 41d1839136098e281ece46520200599ef94edca612Paul Mundt */ 42d1839136098e281ece46520200599ef94edca612Paul Mundt boot_cpu_data.icache.ways = 4; 43d1839136098e281ece46520200599ef94edca612Paul Mundt boot_cpu_data.icache.sets = 256; 44d1839136098e281ece46520200599ef94edca612Paul Mundt boot_cpu_data.icache.linesz = L1_CACHE_BYTES; 4538350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.icache.way_incr = (1 << 13); 4638350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.icache.entry_shift = 5; 4738350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * 4838350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.icache.linesz; 4938350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.icache.entry_mask = 0x1fe0; 5038350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.icache.flags = 0; 51d1839136098e281ece46520200599ef94edca612Paul Mundt 52d1839136098e281ece46520200599ef94edca612Paul Mundt /* 5338350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * Next, setup some sane values for the D-cache. 5438350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * 5538350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * On the SH5, these are pretty consistent with the I-cache settings, 5638350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * so we just copy over the existing definitions.. these can be fixed 5738350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * up later, especially if we add runtime CPU probing. 5838350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * 5938350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * Though in the meantime it saves us from having to duplicate all of 6038350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * the above definitions.. 61d1839136098e281ece46520200599ef94edca612Paul Mundt */ 6238350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt boot_cpu_data.dcache = boot_cpu_data.icache; 63d1839136098e281ece46520200599ef94edca612Paul Mundt 64d1839136098e281ece46520200599ef94edca612Paul Mundt /* 6538350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt * Setup any cache-related flags here 66d1839136098e281ece46520200599ef94edca612Paul Mundt */ 6738350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt#if defined(CONFIG_CACHE_WRITETHROUGH) 6838350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags)); 6938350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt#elif defined(CONFIG_CACHE_WRITEBACK) 7038350e0a00f973dd9c6556beeff0f7eb5ef3f58bPaul Mundt set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags)); 71d1839136098e281ece46520200599ef94edca612Paul Mundt#endif 72d1839136098e281ece46520200599ef94edca612Paul Mundt 732a6b8148c050941dd61779cb0b49c5c3ea854ebfPaul Mundt /* Setup some I/D TLB defaults */ 742a6b8148c050941dd61779cb0b49c5c3ea854ebfPaul Mundt sh64_tlb_init(); 75d1839136098e281ece46520200599ef94edca612Paul Mundt} 76