traps_32.c revision 480c646c32f368dfa2a076f7a120a7795e786e62
1/* 2 * 'traps.c' handles hardware traps and faults after we have saved some 3 * state in 'entry.S'. 4 * 5 * SuperH version: Copyright (C) 1999 Niibe Yutaka 6 * Copyright (C) 2000 Philipp Rumpf 7 * Copyright (C) 2000 David Howells 8 * Copyright (C) 2002 - 2007 Paul Mundt 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14#include <linux/kernel.h> 15#include <linux/ptrace.h> 16#include <linux/hardirq.h> 17#include <linux/init.h> 18#include <linux/spinlock.h> 19#include <linux/module.h> 20#include <linux/kallsyms.h> 21#include <linux/io.h> 22#include <linux/bug.h> 23#include <linux/debug_locks.h> 24#include <linux/kdebug.h> 25#include <linux/kexec.h> 26#include <linux/limits.h> 27#include <linux/proc_fs.h> 28#include <asm/system.h> 29#include <asm/uaccess.h> 30#include <asm/fpu.h> 31#include <asm/kprobes.h> 32 33#ifdef CONFIG_CPU_SH2 34# define TRAP_RESERVED_INST 4 35# define TRAP_ILLEGAL_SLOT_INST 6 36# define TRAP_ADDRESS_ERROR 9 37# ifdef CONFIG_CPU_SH2A 38# define TRAP_UBC 12 39# define TRAP_FPU_ERROR 13 40# define TRAP_DIVZERO_ERROR 17 41# define TRAP_DIVOVF_ERROR 18 42# endif 43#else 44#define TRAP_RESERVED_INST 12 45#define TRAP_ILLEGAL_SLOT_INST 13 46#endif 47 48static unsigned long se_user; 49static unsigned long se_sys; 50static unsigned long se_half; 51static unsigned long se_word; 52static unsigned long se_dword; 53static unsigned long se_multi; 54/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not 55 valid! */ 56static int se_usermode = 3; 57/* 0: no warning 1: print a warning message */ 58static int se_kernmode_warn = 1; 59 60#ifdef CONFIG_PROC_FS 61static const char *se_usermode_action[] = { 62 "ignored", 63 "warn", 64 "fixup", 65 "fixup+warn", 66 "signal", 67 "signal+warn" 68}; 69 70static int 71proc_alignment_read(char *page, char **start, off_t off, int count, int *eof, 72 void *data) 73{ 74 char *p = page; 75 int len; 76 77 p += sprintf(p, "User:\t\t%lu\n", se_user); 78 p += sprintf(p, "System:\t\t%lu\n", se_sys); 79 p += sprintf(p, "Half:\t\t%lu\n", se_half); 80 p += sprintf(p, "Word:\t\t%lu\n", se_word); 81 p += sprintf(p, "DWord:\t\t%lu\n", se_dword); 82 p += sprintf(p, "Multi:\t\t%lu\n", se_multi); 83 p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode, 84 se_usermode_action[se_usermode]); 85 p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn, 86 se_kernmode_warn ? "+warn" : ""); 87 88 len = (p - page) - off; 89 if (len < 0) 90 len = 0; 91 92 *eof = (len <= count) ? 1 : 0; 93 *start = page + off; 94 95 return len; 96} 97 98static int proc_alignment_write(struct file *file, const char __user *buffer, 99 unsigned long count, void *data) 100{ 101 char mode; 102 103 if (count > 0) { 104 if (get_user(mode, buffer)) 105 return -EFAULT; 106 if (mode >= '0' && mode <= '5') 107 se_usermode = mode - '0'; 108 } 109 return count; 110} 111 112static int proc_alignment_kern_write(struct file *file, const char __user *buffer, 113 unsigned long count, void *data) 114{ 115 char mode; 116 117 if (count > 0) { 118 if (get_user(mode, buffer)) 119 return -EFAULT; 120 if (mode >= '0' && mode <= '1') 121 se_kernmode_warn = mode - '0'; 122 } 123 return count; 124} 125#endif 126 127static void dump_mem(const char *str, unsigned long bottom, unsigned long top) 128{ 129 unsigned long p; 130 int i; 131 132 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top); 133 134 for (p = bottom & ~31; p < top; ) { 135 printk("%04lx: ", p & 0xffff); 136 137 for (i = 0; i < 8; i++, p += 4) { 138 unsigned int val; 139 140 if (p < bottom || p >= top) 141 printk(" "); 142 else { 143 if (__get_user(val, (unsigned int __user *)p)) { 144 printk("\n"); 145 return; 146 } 147 printk("%08x ", val); 148 } 149 } 150 printk("\n"); 151 } 152} 153 154static DEFINE_SPINLOCK(die_lock); 155 156void die(const char * str, struct pt_regs * regs, long err) 157{ 158 static int die_counter; 159 160 oops_enter(); 161 162 console_verbose(); 163 spin_lock_irq(&die_lock); 164 bust_spinlocks(1); 165 166 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter); 167 168 print_modules(); 169 show_regs(regs); 170 171 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm, 172 task_pid_nr(current), task_stack_page(current) + 1); 173 174 if (!user_mode(regs) || in_interrupt()) 175 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE + 176 (unsigned long)task_stack_page(current)); 177 178 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV); 179 180 bust_spinlocks(0); 181 add_taint(TAINT_DIE); 182 spin_unlock_irq(&die_lock); 183 184 if (kexec_should_crash(current)) 185 crash_kexec(regs); 186 187 if (in_interrupt()) 188 panic("Fatal exception in interrupt"); 189 190 if (panic_on_oops) 191 panic("Fatal exception"); 192 193 oops_exit(); 194 do_exit(SIGSEGV); 195} 196 197static inline void die_if_kernel(const char *str, struct pt_regs *regs, 198 long err) 199{ 200 if (!user_mode(regs)) 201 die(str, regs, err); 202} 203 204/* 205 * try and fix up kernelspace address errors 206 * - userspace errors just cause EFAULT to be returned, resulting in SEGV 207 * - kernel/userspace interfaces cause a jump to an appropriate handler 208 * - other kernel errors are bad 209 */ 210static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err) 211{ 212 if (!user_mode(regs)) { 213 const struct exception_table_entry *fixup; 214 fixup = search_exception_tables(regs->pc); 215 if (fixup) { 216 regs->pc = fixup->fixup; 217 return; 218 } 219 220 die(str, regs, err); 221 } 222} 223 224static inline void sign_extend(unsigned int count, unsigned char *dst) 225{ 226#ifdef __LITTLE_ENDIAN__ 227 if ((count == 1) && dst[0] & 0x80) { 228 dst[1] = 0xff; 229 dst[2] = 0xff; 230 dst[3] = 0xff; 231 } 232 if ((count == 2) && dst[1] & 0x80) { 233 dst[2] = 0xff; 234 dst[3] = 0xff; 235 } 236#else 237 if ((count == 1) && dst[3] & 0x80) { 238 dst[2] = 0xff; 239 dst[1] = 0xff; 240 dst[0] = 0xff; 241 } 242 if ((count == 2) && dst[2] & 0x80) { 243 dst[1] = 0xff; 244 dst[0] = 0xff; 245 } 246#endif 247} 248 249static struct mem_access user_mem_access = { 250 copy_from_user, 251 copy_to_user, 252}; 253 254/* 255 * handle an instruction that does an unaligned memory access by emulating the 256 * desired behaviour 257 * - note that PC _may not_ point to the faulting instruction 258 * (if that instruction is in a branch delay slot) 259 * - return 0 if emulation okay, -EFAULT on existential error 260 */ 261static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, 262 struct mem_access *ma) 263{ 264 int ret, index, count; 265 unsigned long *rm, *rn; 266 unsigned char *src, *dst; 267 unsigned char __user *srcu, *dstu; 268 269 index = (instruction>>8)&15; /* 0x0F00 */ 270 rn = ®s->regs[index]; 271 272 index = (instruction>>4)&15; /* 0x00F0 */ 273 rm = ®s->regs[index]; 274 275 count = 1<<(instruction&3); 276 277 switch (count) { 278 case 1: se_half += 1; break; 279 case 2: se_word += 1; break; 280 case 4: se_dword += 1; break; 281 case 8: se_multi += 1; break; /* ??? */ 282 } 283 284 ret = -EFAULT; 285 switch (instruction>>12) { 286 case 0: /* mov.[bwl] to/from memory via r0+rn */ 287 if (instruction & 8) { 288 /* from memory */ 289 srcu = (unsigned char __user *)*rm; 290 srcu += regs->regs[0]; 291 dst = (unsigned char *)rn; 292 *(unsigned long *)dst = 0; 293 294#if !defined(__LITTLE_ENDIAN__) 295 dst += 4-count; 296#endif 297 if (ma->from(dst, srcu, count)) 298 goto fetch_fault; 299 300 sign_extend(count, dst); 301 } else { 302 /* to memory */ 303 src = (unsigned char *)rm; 304#if !defined(__LITTLE_ENDIAN__) 305 src += 4-count; 306#endif 307 dstu = (unsigned char __user *)*rn; 308 dstu += regs->regs[0]; 309 310 if (ma->to(dstu, src, count)) 311 goto fetch_fault; 312 } 313 ret = 0; 314 break; 315 316 case 1: /* mov.l Rm,@(disp,Rn) */ 317 src = (unsigned char*) rm; 318 dstu = (unsigned char __user *)*rn; 319 dstu += (instruction&0x000F)<<2; 320 321 if (ma->to(dstu, src, 4)) 322 goto fetch_fault; 323 ret = 0; 324 break; 325 326 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ 327 if (instruction & 4) 328 *rn -= count; 329 src = (unsigned char*) rm; 330 dstu = (unsigned char __user *)*rn; 331#if !defined(__LITTLE_ENDIAN__) 332 src += 4-count; 333#endif 334 if (ma->to(dstu, src, count)) 335 goto fetch_fault; 336 ret = 0; 337 break; 338 339 case 5: /* mov.l @(disp,Rm),Rn */ 340 srcu = (unsigned char __user *)*rm; 341 srcu += (instruction & 0x000F) << 2; 342 dst = (unsigned char *)rn; 343 *(unsigned long *)dst = 0; 344 345 if (ma->from(dst, srcu, 4)) 346 goto fetch_fault; 347 ret = 0; 348 break; 349 350 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 351 srcu = (unsigned char __user *)*rm; 352 if (instruction & 4) 353 *rm += count; 354 dst = (unsigned char*) rn; 355 *(unsigned long*)dst = 0; 356 357#if !defined(__LITTLE_ENDIAN__) 358 dst += 4-count; 359#endif 360 if (ma->from(dst, srcu, count)) 361 goto fetch_fault; 362 sign_extend(count, dst); 363 ret = 0; 364 break; 365 366 case 8: 367 switch ((instruction&0xFF00)>>8) { 368 case 0x81: /* mov.w R0,@(disp,Rn) */ 369 src = (unsigned char *) ®s->regs[0]; 370#if !defined(__LITTLE_ENDIAN__) 371 src += 2; 372#endif 373 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ 374 dstu += (instruction & 0x000F) << 1; 375 376 if (ma->to(dstu, src, 2)) 377 goto fetch_fault; 378 ret = 0; 379 break; 380 381 case 0x85: /* mov.w @(disp,Rm),R0 */ 382 srcu = (unsigned char __user *)*rm; 383 srcu += (instruction & 0x000F) << 1; 384 dst = (unsigned char *) ®s->regs[0]; 385 *(unsigned long *)dst = 0; 386 387#if !defined(__LITTLE_ENDIAN__) 388 dst += 2; 389#endif 390 if (ma->from(dst, srcu, 2)) 391 goto fetch_fault; 392 sign_extend(2, dst); 393 ret = 0; 394 break; 395 } 396 break; 397 } 398 return ret; 399 400 fetch_fault: 401 /* Argh. Address not only misaligned but also non-existent. 402 * Raise an EFAULT and see if it's trapped 403 */ 404 die_if_no_fixup("Fault in unaligned fixup", regs, 0); 405 return -EFAULT; 406} 407 408/* 409 * emulate the instruction in the delay slot 410 * - fetches the instruction from PC+2 411 */ 412static inline int handle_delayslot(struct pt_regs *regs, 413 insn_size_t old_instruction, 414 struct mem_access *ma) 415{ 416 insn_size_t instruction; 417 void __user *addr = (void __user *)(regs->pc + 418 instruction_size(old_instruction)); 419 420 if (copy_from_user(&instruction, addr, sizeof(instruction))) { 421 /* the instruction-fetch faulted */ 422 if (user_mode(regs)) 423 return -EFAULT; 424 425 /* kernel */ 426 die("delay-slot-insn faulting in handle_unaligned_delayslot", 427 regs, 0); 428 } 429 430 return handle_unaligned_ins(instruction, regs, ma); 431} 432 433/* 434 * handle an instruction that does an unaligned memory access 435 * - have to be careful of branch delay-slot instructions that fault 436 * SH3: 437 * - if the branch would be taken PC points to the branch 438 * - if the branch would not be taken, PC points to delay-slot 439 * SH4: 440 * - PC always points to delayed branch 441 * - return 0 if handled, -EFAULT if failed (may not return if in kernel) 442 */ 443 444/* Macros to determine offset from current PC for branch instructions */ 445/* Explicit type coercion is used to force sign extension where needed */ 446#define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) 447#define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) 448 449int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, 450 struct mem_access *ma, int expected) 451{ 452 u_int rm; 453 int ret, index; 454 455 index = (instruction>>8)&15; /* 0x0F00 */ 456 rm = regs->regs[index]; 457 458 /* shout about fixups */ 459 if (!expected && printk_ratelimit()) 460 printk(KERN_NOTICE "Fixing up unaligned %s access " 461 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 462 user_mode(regs) ? "userspace" : "kernel", 463 current->comm, task_pid_nr(current), 464 (void *)regs->pc, instruction); 465 466 ret = -EFAULT; 467 switch (instruction&0xF000) { 468 case 0x0000: 469 if (instruction==0x000B) { 470 /* rts */ 471 ret = handle_delayslot(regs, instruction, ma); 472 if (ret==0) 473 regs->pc = regs->pr; 474 } 475 else if ((instruction&0x00FF)==0x0023) { 476 /* braf @Rm */ 477 ret = handle_delayslot(regs, instruction, ma); 478 if (ret==0) 479 regs->pc += rm + 4; 480 } 481 else if ((instruction&0x00FF)==0x0003) { 482 /* bsrf @Rm */ 483 ret = handle_delayslot(regs, instruction, ma); 484 if (ret==0) { 485 regs->pr = regs->pc + 4; 486 regs->pc += rm + 4; 487 } 488 } 489 else { 490 /* mov.[bwl] to/from memory via r0+rn */ 491 goto simple; 492 } 493 break; 494 495 case 0x1000: /* mov.l Rm,@(disp,Rn) */ 496 goto simple; 497 498 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ 499 goto simple; 500 501 case 0x4000: 502 if ((instruction&0x00FF)==0x002B) { 503 /* jmp @Rm */ 504 ret = handle_delayslot(regs, instruction, ma); 505 if (ret==0) 506 regs->pc = rm; 507 } 508 else if ((instruction&0x00FF)==0x000B) { 509 /* jsr @Rm */ 510 ret = handle_delayslot(regs, instruction, ma); 511 if (ret==0) { 512 regs->pr = regs->pc + 4; 513 regs->pc = rm; 514 } 515 } 516 else { 517 /* mov.[bwl] to/from memory via r0+rn */ 518 goto simple; 519 } 520 break; 521 522 case 0x5000: /* mov.l @(disp,Rm),Rn */ 523 goto simple; 524 525 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ 526 goto simple; 527 528 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ 529 switch (instruction&0x0F00) { 530 case 0x0100: /* mov.w R0,@(disp,Rm) */ 531 goto simple; 532 case 0x0500: /* mov.w @(disp,Rm),R0 */ 533 goto simple; 534 case 0x0B00: /* bf lab - no delayslot*/ 535 break; 536 case 0x0F00: /* bf/s lab */ 537 ret = handle_delayslot(regs, instruction, ma); 538 if (ret==0) { 539#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 540 if ((regs->sr & 0x00000001) != 0) 541 regs->pc += 4; /* next after slot */ 542 else 543#endif 544 regs->pc += SH_PC_8BIT_OFFSET(instruction); 545 } 546 break; 547 case 0x0900: /* bt lab - no delayslot */ 548 break; 549 case 0x0D00: /* bt/s lab */ 550 ret = handle_delayslot(regs, instruction, ma); 551 if (ret==0) { 552#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) 553 if ((regs->sr & 0x00000001) == 0) 554 regs->pc += 4; /* next after slot */ 555 else 556#endif 557 regs->pc += SH_PC_8BIT_OFFSET(instruction); 558 } 559 break; 560 } 561 break; 562 563 case 0xA000: /* bra label */ 564 ret = handle_delayslot(regs, instruction, ma); 565 if (ret==0) 566 regs->pc += SH_PC_12BIT_OFFSET(instruction); 567 break; 568 569 case 0xB000: /* bsr label */ 570 ret = handle_delayslot(regs, instruction, ma); 571 if (ret==0) { 572 regs->pr = regs->pc + 4; 573 regs->pc += SH_PC_12BIT_OFFSET(instruction); 574 } 575 break; 576 } 577 return ret; 578 579 /* handle non-delay-slot instruction */ 580 simple: 581 ret = handle_unaligned_ins(instruction, regs, ma); 582 if (ret==0) 583 regs->pc += instruction_size(instruction); 584 return ret; 585} 586 587/* 588 * Handle various address error exceptions: 589 * - instruction address error: 590 * misaligned PC 591 * PC >= 0x80000000 in user mode 592 * - data address error (read and write) 593 * misaligned data access 594 * access to >= 0x80000000 is user mode 595 * Unfortuntaly we can't distinguish between instruction address error 596 * and data address errors caused by read accesses. 597 */ 598asmlinkage void do_address_error(struct pt_regs *regs, 599 unsigned long writeaccess, 600 unsigned long address) 601{ 602 unsigned long error_code = 0; 603 mm_segment_t oldfs; 604 siginfo_t info; 605 insn_size_t instruction; 606 int tmp; 607 608 /* Intentional ifdef */ 609#ifdef CONFIG_CPU_HAS_SR_RB 610 error_code = lookup_exception_vector(); 611#endif 612 613 oldfs = get_fs(); 614 615 if (user_mode(regs)) { 616 int si_code = BUS_ADRERR; 617 618 local_irq_enable(); 619 620 se_user += 1; 621 622#ifndef CONFIG_CPU_SH2A 623 set_fs(USER_DS); 624 if (copy_from_user(&instruction, (u16 *)(regs->pc & ~1), 2)) { 625 set_fs(oldfs); 626 goto uspace_segv; 627 } 628 set_fs(oldfs); 629 630 /* shout about userspace fixups */ 631 if (se_usermode & 1) 632 printk(KERN_NOTICE "Unaligned userspace access " 633 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 634 current->comm, current->pid, (void *)regs->pc, 635 instruction); 636#endif 637 638 if (se_usermode & 2) 639 goto fixup; 640 641 if (se_usermode & 4) 642 goto uspace_segv; 643 else { 644 /* ignore */ 645 regs->pc += instruction_size(instruction); 646 return; 647 } 648 649fixup: 650 /* bad PC is not something we can fix */ 651 if (regs->pc & 1) { 652 si_code = BUS_ADRALN; 653 goto uspace_segv; 654 } 655 656 set_fs(USER_DS); 657 tmp = handle_unaligned_access(instruction, regs, 658 &user_mem_access, 0); 659 set_fs(oldfs); 660 661 if (tmp==0) 662 return; /* sorted */ 663uspace_segv: 664 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " 665 "access (PC %lx PR %lx)\n", current->comm, regs->pc, 666 regs->pr); 667 668 info.si_signo = SIGBUS; 669 info.si_errno = 0; 670 info.si_code = si_code; 671 info.si_addr = (void __user *)address; 672 force_sig_info(SIGBUS, &info, current); 673 } else { 674 se_sys += 1; 675 676 if (se_kernmode_warn) 677 printk(KERN_NOTICE "Unaligned kernel access " 678 "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n", 679 current->comm, current->pid, (void *)regs->pc, 680 instruction); 681 682 if (regs->pc & 1) 683 die("unaligned program counter", regs, error_code); 684 685 set_fs(KERNEL_DS); 686 if (copy_from_user(&instruction, (void __user *)(regs->pc), 687 sizeof(instruction))) { 688 /* Argh. Fault on the instruction itself. 689 This should never happen non-SMP 690 */ 691 set_fs(oldfs); 692 die("insn faulting in do_address_error", regs, 0); 693 } 694 695 handle_unaligned_access(instruction, regs, 696 &user_mem_access, 0); 697 set_fs(oldfs); 698 } 699} 700 701#ifdef CONFIG_SH_DSP 702/* 703 * SH-DSP support gerg@snapgear.com. 704 */ 705int is_dsp_inst(struct pt_regs *regs) 706{ 707 unsigned short inst = 0; 708 709 /* 710 * Safe guard if DSP mode is already enabled or we're lacking 711 * the DSP altogether. 712 */ 713 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) 714 return 0; 715 716 get_user(inst, ((unsigned short *) regs->pc)); 717 718 inst &= 0xf000; 719 720 /* Check for any type of DSP or support instruction */ 721 if ((inst == 0xf000) || (inst == 0x4000)) 722 return 1; 723 724 return 0; 725} 726#else 727#define is_dsp_inst(regs) (0) 728#endif /* CONFIG_SH_DSP */ 729 730#ifdef CONFIG_CPU_SH2A 731asmlinkage void do_divide_error(unsigned long r4, unsigned long r5, 732 unsigned long r6, unsigned long r7, 733 struct pt_regs __regs) 734{ 735 siginfo_t info; 736 737 switch (r4) { 738 case TRAP_DIVZERO_ERROR: 739 info.si_code = FPE_INTDIV; 740 break; 741 case TRAP_DIVOVF_ERROR: 742 info.si_code = FPE_INTOVF; 743 break; 744 } 745 746 force_sig_info(SIGFPE, &info, current); 747} 748#endif 749 750asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5, 751 unsigned long r6, unsigned long r7, 752 struct pt_regs __regs) 753{ 754 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 755 unsigned long error_code; 756 struct task_struct *tsk = current; 757 758#ifdef CONFIG_SH_FPU_EMU 759 unsigned short inst = 0; 760 int err; 761 762 get_user(inst, (unsigned short*)regs->pc); 763 764 err = do_fpu_inst(inst, regs); 765 if (!err) { 766 regs->pc += instruction_size(inst); 767 return; 768 } 769 /* not a FPU inst. */ 770#endif 771 772#ifdef CONFIG_SH_DSP 773 /* Check if it's a DSP instruction */ 774 if (is_dsp_inst(regs)) { 775 /* Enable DSP mode, and restart instruction. */ 776 regs->sr |= SR_DSP; 777 /* Save DSP mode */ 778 tsk->thread.dsp_status.status |= SR_DSP; 779 return; 780 } 781#endif 782 783 error_code = lookup_exception_vector(); 784 785 local_irq_enable(); 786 force_sig(SIGILL, tsk); 787 die_if_no_fixup("reserved instruction", regs, error_code); 788} 789 790#ifdef CONFIG_SH_FPU_EMU 791static int emulate_branch(unsigned short inst, struct pt_regs *regs) 792{ 793 /* 794 * bfs: 8fxx: PC+=d*2+4; 795 * bts: 8dxx: PC+=d*2+4; 796 * bra: axxx: PC+=D*2+4; 797 * bsr: bxxx: PC+=D*2+4 after PR=PC+4; 798 * braf:0x23: PC+=Rn*2+4; 799 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; 800 * jmp: 4x2b: PC=Rn; 801 * jsr: 4x0b: PC=Rn after PR=PC+4; 802 * rts: 000b: PC=PR; 803 */ 804 if (((inst & 0xf000) == 0xb000) || /* bsr */ 805 ((inst & 0xf0ff) == 0x0003) || /* bsrf */ 806 ((inst & 0xf0ff) == 0x400b)) /* jsr */ 807 regs->pr = regs->pc + 4; 808 809 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ 810 regs->pc += SH_PC_8BIT_OFFSET(inst); 811 return 0; 812 } 813 814 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ 815 regs->pc += SH_PC_12BIT_OFFSET(inst); 816 return 0; 817 } 818 819 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ 820 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; 821 return 0; 822 } 823 824 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ 825 regs->pc = regs->regs[(inst & 0x0f00) >> 8]; 826 return 0; 827 } 828 829 if ((inst & 0xffff) == 0x000b) { /* rts */ 830 regs->pc = regs->pr; 831 return 0; 832 } 833 834 return 1; 835} 836#endif 837 838asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5, 839 unsigned long r6, unsigned long r7, 840 struct pt_regs __regs) 841{ 842 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 843 unsigned long inst; 844 struct task_struct *tsk = current; 845 846 if (kprobe_handle_illslot(regs->pc) == 0) 847 return; 848 849#ifdef CONFIG_SH_FPU_EMU 850 get_user(inst, (unsigned short *)regs->pc + 1); 851 if (!do_fpu_inst(inst, regs)) { 852 get_user(inst, (unsigned short *)regs->pc); 853 if (!emulate_branch(inst, regs)) 854 return; 855 /* fault in branch.*/ 856 } 857 /* not a FPU inst. */ 858#endif 859 860 inst = lookup_exception_vector(); 861 862 local_irq_enable(); 863 force_sig(SIGILL, tsk); 864 die_if_no_fixup("illegal slot instruction", regs, inst); 865} 866 867asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 868 unsigned long r6, unsigned long r7, 869 struct pt_regs __regs) 870{ 871 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 872 long ex; 873 874 ex = lookup_exception_vector(); 875 die_if_kernel("exception", regs, ex); 876} 877 878#if defined(CONFIG_SH_STANDARD_BIOS) 879void *gdb_vbr_vector; 880 881static inline void __init gdb_vbr_init(void) 882{ 883 register unsigned long vbr; 884 885 /* 886 * Read the old value of the VBR register to initialise 887 * the vector through which debug and BIOS traps are 888 * delegated by the Linux trap handler. 889 */ 890 asm volatile("stc vbr, %0" : "=r" (vbr)); 891 892 gdb_vbr_vector = (void *)(vbr + 0x100); 893 printk("Setting GDB trap vector to 0x%08lx\n", 894 (unsigned long)gdb_vbr_vector); 895} 896#endif 897 898void __cpuinit per_cpu_trap_init(void) 899{ 900 extern void *vbr_base; 901 902#ifdef CONFIG_SH_STANDARD_BIOS 903 if (raw_smp_processor_id() == 0) 904 gdb_vbr_init(); 905#endif 906 907 /* NOTE: The VBR value should be at P1 908 (or P2, virtural "fixed" address space). 909 It's definitely should not in physical address. */ 910 911 asm volatile("ldc %0, vbr" 912 : /* no output */ 913 : "r" (&vbr_base) 914 : "memory"); 915} 916 917void *set_exception_table_vec(unsigned int vec, void *handler) 918{ 919 extern void *exception_handling_table[]; 920 void *old_handler; 921 922 old_handler = exception_handling_table[vec]; 923 exception_handling_table[vec] = handler; 924 return old_handler; 925} 926 927void __init trap_init(void) 928{ 929 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); 930 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); 931 932#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ 933 defined(CONFIG_SH_FPU_EMU) 934 /* 935 * For SH-4 lacking an FPU, treat floating point instructions as 936 * reserved. They'll be handled in the math-emu case, or faulted on 937 * otherwise. 938 */ 939 set_exception_table_evt(0x800, do_reserved_inst); 940 set_exception_table_evt(0x820, do_illegal_slot_inst); 941#elif defined(CONFIG_SH_FPU) 942#ifdef CONFIG_CPU_SUBTYPE_SHX3 943 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler); 944 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler); 945#else 946 set_exception_table_evt(0x800, fpu_state_restore_trap_handler); 947 set_exception_table_evt(0x820, fpu_state_restore_trap_handler); 948#endif 949#endif 950 951#ifdef CONFIG_CPU_SH2 952 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); 953#endif 954#ifdef CONFIG_CPU_SH2A 955 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); 956 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); 957#ifdef CONFIG_SH_FPU 958 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); 959#endif 960#endif 961 962#ifdef TRAP_UBC 963 set_exception_table_vec(TRAP_UBC, break_point_trap); 964#endif 965 966 /* Setup VBR for boot cpu */ 967 per_cpu_trap_init(); 968} 969 970void show_stack(struct task_struct *tsk, unsigned long *sp) 971{ 972 unsigned long stack; 973 974 if (!tsk) 975 tsk = current; 976 if (tsk == current) 977 sp = (unsigned long *)current_stack_pointer; 978 else 979 sp = (unsigned long *)tsk->thread.sp; 980 981 stack = (unsigned long)sp; 982 dump_mem("Stack: ", stack, THREAD_SIZE + 983 (unsigned long)task_stack_page(tsk)); 984 show_trace(tsk, sp, NULL); 985} 986 987void dump_stack(void) 988{ 989 show_stack(NULL, NULL); 990} 991EXPORT_SYMBOL(dump_stack); 992 993#ifdef CONFIG_PROC_FS 994/* 995 * This needs to be done after sysctl_init, otherwise sys/ will be 996 * overwritten. Actually, this shouldn't be in sys/ at all since 997 * it isn't a sysctl, and it doesn't contain sysctl information. 998 * We now locate it in /proc/cpu/alignment instead. 999 */ 1000static int __init alignment_init(void) 1001{ 1002 struct proc_dir_entry *dir, *res; 1003 1004 dir = proc_mkdir("cpu", NULL); 1005 if (!dir) 1006 return -ENOMEM; 1007 1008 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir); 1009 if (!res) 1010 return -ENOMEM; 1011 1012 res->read_proc = proc_alignment_read; 1013 res->write_proc = proc_alignment_write; 1014 1015 res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir); 1016 if (!res) 1017 return -ENOMEM; 1018 1019 res->read_proc = proc_alignment_read; 1020 res->write_proc = proc_alignment_kern_write; 1021 1022 return 0; 1023} 1024 1025fs_initcall(alignment_init); 1026#endif 1027