1a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#ifndef _SPARC64_BACKOFF_H 2a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#define _SPARC64_BACKOFF_H 3a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 4187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller/* The macros in this file implement an exponential backoff facility 5187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * for atomic operations. 6187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * 7187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * When multiple threads compete on an atomic operation, it is 8187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * possible for one thread to be continually denied a successful 9187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * completion of the compare-and-swap instruction. Heavily 10187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * threaded cpu implementations like Niagara can compound this 11187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * problem even further. 12187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * 13187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * When an atomic operation fails and needs to be retried, we spin a 14187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * certain number of times. At each subsequent failure of the same 15187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * operation we double the spin count, realizing an exponential 16187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * backoff. 17187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * 18187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * When we spin, we try to use an operation that will cause the 19187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * current cpu strand to block, and therefore make the core fully 20187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * available to any other other runnable strands. There are two 21187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * options, based upon cpu capabilities. 22187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * 23187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * On all cpus prior to SPARC-T4 we do three dummy reads of the 24187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * condition code register. Each read blocks the strand for something 25187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * between 40 and 50 cpu cycles. 26187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * 27187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * For SPARC-T4 and later we have a special "pause" instruction 28187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * available. This is implemented using writes to register %asr27. 29187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * The cpu will block the number of cycles written into the register, 30187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * unless a disrupting trap happens first. SPARC-T4 specifically 31187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * implements pause with a granularity of 8 cycles. Each strand has 32187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * an internal pause counter which decrements every 8 cycles. So the 33187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * chip shifts the %asr27 value down by 3 bits, and writes the result 34187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * into the pause counter. If a value smaller than 8 is written, the 35187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * chip blocks for 1 cycle. 36187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * 37187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * To achieve the same amount of backoff as the three %ccr reads give 38187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * on earlier chips, we shift the backoff value up by 7 bits. (Three 39187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * %ccr reads block for about 128 cycles, 1 << 7 == 128) We write the 40187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * whole amount we want to block into the pause register, rather than 41187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller * loop writing 128 each time. 42187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller */ 43187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller 44a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#define BACKOFF_LIMIT (4 * 1024) 45a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 46a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#ifdef CONFIG_SMP 47a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 48a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#define BACKOFF_SETUP(reg) \ 49a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg mov 1, reg 50a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 510f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller#define BACKOFF_LABEL(spin_label, continue_label) \ 520f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller spin_label 530f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller 54e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller#define BACKOFF_SPIN(reg, tmp, label) \ 55e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller mov reg, tmp; \ 56e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller88: rd %ccr, %g0; \ 57e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller rd %ccr, %g0; \ 58e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller rd %ccr, %g0; \ 59187818cd6a5ab6343eac47e52da2f3e40c544b98David S. Miller .section .pause_3insn_patch,"ax";\ 60e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller .word 88b; \ 61e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller sllx tmp, 7, tmp; \ 62e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller wr tmp, 0, %asr27; \ 63e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller clr tmp; \ 64e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller .previous; \ 65e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller brnz,pt tmp, 88b; \ 66e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller sub tmp, 1, tmp; \ 67e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller set BACKOFF_LIMIT, tmp; \ 68e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller cmp reg, tmp; \ 69e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller bg,pn %xcc, label; \ 70e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller nop; \ 71e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller ba,pt %xcc, label; \ 72e9b9eb59ffcdee09ec96b040f85c919618f4043eDavid S. Miller sllx reg, 1, reg; 73a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 74a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#else 75a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 76a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#define BACKOFF_SETUP(reg) 770f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller 780f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller#define BACKOFF_LABEL(spin_label, continue_label) \ 790f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller continue_label 800f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller 810f58189d4a3ca96d7959501ecb203177efdbc5bdDavid S. Miller#define BACKOFF_SPIN(reg, tmp, label) 82a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 83a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#endif 84a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg 85a00736e936c2a1e9c36f22f6f3a69392eaab51f4Sam Ravnborg#endif /* _SPARC64_BACKOFF_H */ 86