1867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf/* 2867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * Copyright 2010 Tilera Corporation. All Rights Reserved. 3867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * 4867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * This program is free software; you can redistribute it and/or 5867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * modify it under the terms of the GNU General Public License 6867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * as published by the Free Software Foundation, version 2. 7867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * 8867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * This program is distributed in the hope that it will be useful, but 9867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * WITHOUT ANY WARRANTY; without even the implied warranty of 10867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * NON INFRINGEMENT. See the GNU General Public License for 12867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * more details. 13867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf */ 14867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 15867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf#ifndef _ASM_TILE_PCI_H 16867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf#define _ASM_TILE_PCI_H 17867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 1841bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#include <linux/dma-mapping.h> 19f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf#include <linux/pci.h> 20845501213033d0058945776349f15502823359d8Michael S. Tsirkin#include <asm-generic/pci_iomap.h> 21f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf 22129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#ifndef __tilegx__ 23129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 24f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf/* 25f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf * Structure of a PCI controller (host bridge) 26f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf */ 27f02cbbe657939489347cbda598401a56913ffcbdChris Metcalfstruct pci_controller { 28f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf int index; /* PCI domain number */ 29f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf struct pci_bus *root_bus; 30f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf 31f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf int last_busno; 32f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf 33f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */ 34f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf int hv_mem_fd; /* fd to Hypervisor for MMIO operations */ 35f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf 36f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf struct pci_ops *ops; 37f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf 38f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf int irq_base; /* Base IRQ from the Hypervisor */ 39f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf int plx_gen1; /* flag for PLX Gen 1 configuration */ 40f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf 41f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf /* Address ranges that are routed to this controller/bridge. */ 42f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf struct resource mem_resources[3]; 43f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf}; 44867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 45867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf/* 46129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * This flag tells if the platform is TILEmpower that needs 47129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * special configuration for the PLX switch chip. 48129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 49129622672d70711c6c844fb529381ff0dad9085aChris Metcalfextern int tile_plx_gen1; 50129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 51129622672d70711c6c844fb529381ff0dad9085aChris Metcalfstatic inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {} 52129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 53129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#define TILE_NUM_PCIE 2 54129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 5541bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* 5641bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * The hypervisor maps the entirety of CPA-space as bus addresses, so 5741bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * bus addresses are physical addresses. The networking and block 5841bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * device layers use this boolean for bounce buffer decisions. 5941bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf */ 6041bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define PCI_DMA_BUS_IS_PHYS 1 6141bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 6241bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* generic pci stuff */ 6341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#include <asm-generic/pci.h> 6441bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 65129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#else 66129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 67129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#include <asm/page.h> 68129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#include <gxio/trio.h> 69129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 70129622672d70711c6c844fb529381ff0dad9085aChris Metcalf/** 71129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * We reserve the hugepage-size address range at the top of the 64-bit address 72129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * space to serve as the PCI window, emulating the BAR0 space of an endpoint 73129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * device. This window is used by the chip-to-chip applications running on 74129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * the RC node. The reason for carving out this window is that Mem-Maps that 75129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * back up this window will not overlap with those that map the real physical 76129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * memory. 77129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 78129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#define PCIE_HOST_BAR0_SIZE HPAGE_SIZE 79129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#define PCIE_HOST_BAR0_START HPAGE_MASK 80129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 81129622672d70711c6c844fb529381ff0dad9085aChris Metcalf/** 82129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * The first PAGE_SIZE of the above "BAR" window is mapped to the 83129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * gxpci_host_regs structure. 84129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 85129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#define PCIE_HOST_REGS_SIZE PAGE_SIZE 86129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 87129622672d70711c6c844fb529381ff0dad9085aChris Metcalf/* 88129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * This is the PCI address where the Mem-Map interrupt regions start. 89129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * We use the 2nd to the last huge page of the 64-bit address space. 90129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * The last huge page is used for the rootcomplex "bar", for C2C purpose. 91129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 92129622672d70711c6c844fb529381ff0dad9085aChris Metcalf#define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE) 93129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 94129622672d70711c6c844fb529381ff0dad9085aChris Metcalf/* 95129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * Each Mem-Map interrupt region occupies 4KB. 96129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 9741bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define MEM_MAP_INTR_REGION_SIZE (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT) 9841bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 9941bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* 10041bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * Allocate the PCI BAR window right below 4GB. 10141bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf */ 10241bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define TILE_PCI_BAR_WINDOW_TOP (1ULL << 32) 10341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 10441bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* 10541bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * Allocate 1GB for the PCI BAR window. 10641bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf */ 10741bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define TILE_PCI_BAR_WINDOW_SIZE (1 << 30) 10841bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 10941bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* 11041bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * This is the highest bus address targeting the host memory that 11141bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * can be generated by legacy PCI devices with 32-bit or less 11241bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * DMA capability, dictated by the BAR window size and location. 11341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf */ 11441bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \ 11541bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1) 11641bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 11741bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* 11841bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * We shift the PCI bus range for all the physical memory up by the whole PA 11941bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * range. The corresponding CPA of an incoming PCI request will be the PCI 12041bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies 12141bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * that the 64-bit capable devices will be given DMA addresses as 12241bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit 12341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * devices, we create a separate map region that handles the low 12441bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * 4GB. 1255e7705df28720c424c11bdedf0d568177351c55aChris Metcalf * 1265e7705df28720c424c11bdedf0d568177351c55aChris Metcalf * This design lets us avoid the "PCI hole" problem where the host bridge 1275e7705df28720c424c11bdedf0d568177351c55aChris Metcalf * won't pass DMA traffic with target addresses that happen to fall within the 1285e7705df28720c424c11bdedf0d568177351c55aChris Metcalf * BAR space. This enables us to use all the physical memory for DMA, instead 1295e7705df28720c424c11bdedf0d568177351c55aChris Metcalf * of wasting the same amount of physical memory as the BAR window size. 13041bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf */ 13141bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH()) 13241bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 13341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf/* 134f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf * Start of the PCI memory resource, which starts at the end of the 135f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf * maximum system physical RAM address. 13641bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf */ 137f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf#define TILE_PCI_MEM_START (1ULL << CHIP_PA_WIDTH()) 138129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 139129622672d70711c6c844fb529381ff0dad9085aChris Metcalf/* 140129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * Structure of a PCI controller (host bridge) on Gx. 141129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 142129622672d70711c6c844fb529381ff0dad9085aChris Metcalfstruct pci_controller { 143129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 144129622672d70711c6c844fb529381ff0dad9085aChris Metcalf /* Pointer back to the TRIO that this PCIe port is connected to. */ 145129622672d70711c6c844fb529381ff0dad9085aChris Metcalf gxio_trio_context_t *trio; 146129622672d70711c6c844fb529381ff0dad9085aChris Metcalf int mac; /* PCIe mac index on the TRIO shim */ 147129622672d70711c6c844fb529381ff0dad9085aChris Metcalf int trio_index; /* Index of TRIO shim that contains the MAC. */ 148129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 149129622672d70711c6c844fb529381ff0dad9085aChris Metcalf int pio_mem_index; /* PIO region index for memory access */ 150129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 151cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf#ifdef CONFIG_TILE_PCI_IO 152cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf int pio_io_index; /* PIO region index for I/O space access */ 153cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf#endif 154cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf 155129622672d70711c6c844fb529381ff0dad9085aChris Metcalf /* 156129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * Mem-Map regions for all the memory controllers so that Linux can 157129622672d70711c6c844fb529381ff0dad9085aChris Metcalf * map all of its physical memory space to the PCI bus. 158129622672d70711c6c844fb529381ff0dad9085aChris Metcalf */ 159129622672d70711c6c844fb529381ff0dad9085aChris Metcalf int mem_maps[MAX_NUMNODES]; 160129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 161129622672d70711c6c844fb529381ff0dad9085aChris Metcalf int index; /* PCI domain number */ 162129622672d70711c6c844fb529381ff0dad9085aChris Metcalf struct pci_bus *root_bus; 163129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 164cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf /* PCI I/O space resource for this controller. */ 165cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf struct resource io_space; 166cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf char io_space_name[32]; 167cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf 168f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf /* PCI memory space resource for this controller. */ 169f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf struct resource mem_space; 170f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf char mem_space_name[32]; 171f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf 17241bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf uint64_t mem_offset; /* cpu->bus memory mapping offset. */ 17341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 174f6d2ce00da145ae31ec22d21daca6ca5e22b3c84Chris Metcalf int first_busno; 175129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 176129622672d70711c6c844fb529381ff0dad9085aChris Metcalf struct pci_ops *ops; 177129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 178129622672d70711c6c844fb529381ff0dad9085aChris Metcalf /* Table that maps the INTx numbers to Linux irq numbers. */ 179129622672d70711c6c844fb529381ff0dad9085aChris Metcalf int irq_intx_table[4]; 180129622672d70711c6c844fb529381ff0dad9085aChris Metcalf}; 181129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 182129622672d70711c6c844fb529381ff0dad9085aChris Metcalfextern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES]; 183129622672d70711c6c844fb529381ff0dad9085aChris Metcalfextern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO]; 1841c43649a9929ca4394ae389b4510c61f3876a12bChris Metcalfextern int num_trio_shims; 185129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 186129622672d70711c6c844fb529381ff0dad9085aChris Metcalfextern void pci_iounmap(struct pci_dev *dev, void __iomem *); 187129622672d70711c6c844fb529381ff0dad9085aChris Metcalf 188129622672d70711c6c844fb529381ff0dad9085aChris Metcalf/* 18941bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * The PCI address space does not equal the physical memory address 19041bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * space (we have an IOMMU). The IDE and SCSI device layers use this 19141bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf * boolean for bounce buffer decisions. 192867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf */ 19341bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#define PCI_DMA_BUS_IS_PHYS 0 19441bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf 19541bb38fc5398ae878c799647f3c4b25374029afbChris Metcalf#endif /* __tilegx__ */ 196867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 19705ef1b79d46347f94d9a78214cc745046c03e45aChris Metcalfint __init tile_pci_init(void); 19805ef1b79d46347f94d9a78214cc745046c03e45aChris Metcalfint __init pcibios_init(void); 199867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 200b881bc469bdbdcca60e75047885509eb9886d3a2Greg Kroah-Hartmanvoid pcibios_fixup_bus(struct pci_bus *bus); 201867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 202867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index) 203867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 204867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf/* 205867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf * This decides whether to display the domain number in /proc. 206867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf */ 207867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalfstatic inline int pci_proc_domain(struct pci_bus *bus) 208867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf{ 209867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf return 1; 210867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf} 211867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 212867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf/* 213f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf * pcibios_assign_all_busses() tells whether or not the bus numbers 214f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf * should be reassigned, in case the BIOS didn't do it correctly, or 215f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf * in case we don't have a BIOS and we want to let Linux do it. 216867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf */ 217f02cbbe657939489347cbda598401a56913ffcbdChris Metcalfstatic inline int pcibios_assign_all_busses(void) 218f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf{ 219f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf return 1; 220f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf} 221867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 222867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf#define PCIBIOS_MIN_MEM 0 223cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf/* Minimum PCI I/O address, starting at the page boundary. */ 224cf89c4262bd5fa70e67953126001c08ecea4f346Chris Metcalf#define PCIBIOS_MIN_IO PAGE_SIZE 225867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 226f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf/* Use any cpu for PCI. */ 227f02cbbe657939489347cbda598401a56913ffcbdChris Metcalf#define cpumask_of_pcibus(bus) cpu_online_mask 228867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 229867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf/* implement the pci_ DMA API in terms of the generic device dma_ one */ 230867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf#include <asm-generic/pci-dma-compat.h> 231867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf 232867e359b97c970a60626d5d76bbe2a8fadbf38fbChris Metcalf#endif /* _ASM_TILE_PCI_H */ 233