apic.h revision f1157141636848f52c5f74040bed0ba355cf59b7 
1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
3
4#include <linux/cpumask.h>
5#include <linux/delay.h>
6#include <linux/pm.h>
7
8#include <asm/alternative.h>
9#include <asm/cpufeature.h>
10#include <asm/processor.h>
11#include <asm/apicdef.h>
12#include <asm/atomic.h>
13#include <asm/fixmap.h>
14#include <asm/mpspec.h>
15#include <asm/system.h>
16#include <asm/msr.h>
17
18#define ARCH_APICTIMER_STOPS_ON_C3	1
19
20/*
21 * Debugging macros
22 */
23#define APIC_QUIET   0
24#define APIC_VERBOSE 1
25#define APIC_DEBUG   2
26
27/*
28 * Define the default level of output to be very little
29 * This can be turned up by using apic=verbose for more
30 * information and apic=debug for _lots_ of information.
31 * apic_verbosity is defined in apic.c
32 */
33#define apic_printk(v, s, a...) do {       \
34		if ((v) <= apic_verbosity) \
35			printk(s, ##a);    \
36	} while (0)
37
38
39#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
40extern void generic_apic_probe(void);
41#else
42static inline void generic_apic_probe(void)
43{
44}
45#endif
46
47#ifdef CONFIG_X86_LOCAL_APIC
48
49extern unsigned int apic_verbosity;
50extern int local_apic_timer_c2_ok;
51
52extern int disable_apic;
53
54#ifdef CONFIG_SMP
55extern void __inquire_remote_apic(int apicid);
56#else /* CONFIG_SMP */
57static inline void __inquire_remote_apic(int apicid)
58{
59}
60#endif /* CONFIG_SMP */
61
62static inline void default_inquire_remote_apic(int apicid)
63{
64	if (apic_verbosity >= APIC_DEBUG)
65		__inquire_remote_apic(apicid);
66}
67
68/*
69 * With 82489DX we can't rely on apic feature bit
70 * retrieved via cpuid but still have to deal with
71 * such an apic chip so we assume that SMP configuration
72 * is found from MP table (64bit case uses ACPI mostly
73 * which set smp presence flag as well so we are safe
74 * to use this helper too).
75 */
76static inline bool apic_from_smp_config(void)
77{
78	return smp_found_config && !disable_apic;
79}
80
81/*
82 * Basic functions accessing APICs.
83 */
84#ifdef CONFIG_PARAVIRT
85#include <asm/paravirt.h>
86#endif
87
88#ifdef CONFIG_X86_64
89extern int is_vsmp_box(void);
90#else
91static inline int is_vsmp_box(void)
92{
93	return 0;
94}
95#endif
96extern void xapic_wait_icr_idle(void);
97extern u32 safe_xapic_wait_icr_idle(void);
98extern void xapic_icr_write(u32, u32);
99extern int setup_profiling_timer(unsigned int);
100
101static inline void native_apic_mem_write(u32 reg, u32 v)
102{
103	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
104
105	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
106		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
107		       ASM_OUTPUT2("0" (v), "m" (*addr)));
108}
109
110static inline u32 native_apic_mem_read(u32 reg)
111{
112	return *((volatile u32 *)(APIC_BASE + reg));
113}
114
115extern void native_apic_wait_icr_idle(void);
116extern u32 native_safe_apic_wait_icr_idle(void);
117extern void native_apic_icr_write(u32 low, u32 id);
118extern u64 native_apic_icr_read(void);
119
120extern int x2apic_mode;
121
122#ifdef CONFIG_X86_X2APIC
123/*
124 * Make previous memory operations globally visible before
125 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
126 * mfence for this.
127 */
128static inline void x2apic_wrmsr_fence(void)
129{
130	asm volatile("mfence" : : : "memory");
131}
132
133static inline void native_apic_msr_write(u32 reg, u32 v)
134{
135	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
136	    reg == APIC_LVR)
137		return;
138
139	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
140}
141
142static inline u32 native_apic_msr_read(u32 reg)
143{
144	u64 msr;
145
146	if (reg == APIC_DFR)
147		return -1;
148
149	rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
150	return (u32)msr;
151}
152
153static inline void native_x2apic_wait_icr_idle(void)
154{
155	/* no need to wait for icr idle in x2apic */
156	return;
157}
158
159static inline u32 native_safe_x2apic_wait_icr_idle(void)
160{
161	/* no need to wait for icr idle in x2apic */
162	return 0;
163}
164
165static inline void native_x2apic_icr_write(u32 low, u32 id)
166{
167	wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
168}
169
170static inline u64 native_x2apic_icr_read(void)
171{
172	unsigned long val;
173
174	rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
175	return val;
176}
177
178extern int x2apic_phys;
179extern void check_x2apic(void);
180extern void enable_x2apic(void);
181extern void x2apic_icr_write(u32 low, u32 id);
182static inline int x2apic_enabled(void)
183{
184	u64 msr;
185
186	if (!cpu_has_x2apic)
187		return 0;
188
189	rdmsrl(MSR_IA32_APICBASE, msr);
190	if (msr & X2APIC_ENABLE)
191		return 1;
192	return 0;
193}
194
195#define x2apic_supported()	(cpu_has_x2apic)
196static inline void x2apic_force_phys(void)
197{
198	x2apic_phys = 1;
199}
200#else
201static inline void check_x2apic(void)
202{
203}
204static inline void enable_x2apic(void)
205{
206}
207static inline int x2apic_enabled(void)
208{
209	return 0;
210}
211static inline void x2apic_force_phys(void)
212{
213}
214
215#define	x2apic_preenabled 0
216#define	x2apic_supported()	0
217#endif
218
219extern void enable_IR_x2apic(void);
220
221extern int get_physical_broadcast(void);
222
223extern void apic_disable(void);
224extern int lapic_get_maxlvt(void);
225extern void clear_local_APIC(void);
226extern void connect_bsp_APIC(void);
227extern void disconnect_bsp_APIC(int virt_wire_setup);
228extern void disable_local_APIC(void);
229extern void lapic_shutdown(void);
230extern int verify_local_APIC(void);
231extern void cache_APIC_registers(void);
232extern void sync_Arb_IDs(void);
233extern void init_bsp_APIC(void);
234extern void setup_local_APIC(void);
235extern void end_local_APIC_setup(void);
236extern void init_apic_mappings(void);
237void register_lapic_address(unsigned long address);
238extern void setup_boot_APIC_clock(void);
239extern void setup_secondary_APIC_clock(void);
240extern int APIC_init_uniprocessor(void);
241extern void enable_NMI_through_LVT0(void);
242extern int apic_force_enable(void);
243
244/*
245 * On 32bit this is mach-xxx local
246 */
247#ifdef CONFIG_X86_64
248extern int apic_is_clustered_box(void);
249#else
250static inline int apic_is_clustered_box(void)
251{
252	return 0;
253}
254#endif
255
256extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
257
258#else /* !CONFIG_X86_LOCAL_APIC */
259static inline void lapic_shutdown(void) { }
260#define local_apic_timer_c2_ok		1
261static inline void init_apic_mappings(void) { }
262static inline void disable_local_APIC(void) { }
263static inline void apic_disable(void) { }
264# define setup_boot_APIC_clock x86_init_noop
265# define setup_secondary_APIC_clock x86_init_noop
266#endif /* !CONFIG_X86_LOCAL_APIC */
267
268#ifdef CONFIG_X86_64
269#define	SET_APIC_ID(x)		(apic->set_apic_id(x))
270#else
271
272#endif
273
274/*
275 * Copyright 2004 James Cleverdon, IBM.
276 * Subject to the GNU Public License, v.2
277 *
278 * Generic APIC sub-arch data struct.
279 *
280 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
281 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
282 * James Cleverdon.
283 */
284struct apic {
285	char *name;
286
287	int (*probe)(void);
288	int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
289	int (*apic_id_registered)(void);
290
291	u32 irq_delivery_mode;
292	u32 irq_dest_mode;
293
294	const struct cpumask *(*target_cpus)(void);
295
296	int disable_esr;
297
298	int dest_logical;
299	unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
300	unsigned long (*check_apicid_present)(int apicid);
301
302	void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
303	void (*init_apic_ldr)(void);
304
305	void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
306
307	void (*setup_apic_routing)(void);
308	int (*multi_timer_check)(int apic, int irq);
309	int (*apicid_to_node)(int logical_apicid);
310	int (*cpu_to_logical_apicid)(int cpu);
311	int (*cpu_present_to_apicid)(int mps_cpu);
312	void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
313	void (*setup_portio_remap)(void);
314	int (*check_phys_apicid_present)(int phys_apicid);
315	void (*enable_apic_mode)(void);
316	int (*phys_pkg_id)(int cpuid_apic, int index_msb);
317
318	/*
319	 * When one of the next two hooks returns 1 the apic
320	 * is switched to this. Essentially they are additional
321	 * probe functions:
322	 */
323	int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
324
325	unsigned int (*get_apic_id)(unsigned long x);
326	unsigned long (*set_apic_id)(unsigned int id);
327	unsigned long apic_id_mask;
328
329	unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
330	unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
331					       const struct cpumask *andmask);
332
333	/* ipi */
334	void (*send_IPI_mask)(const struct cpumask *mask, int vector);
335	void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
336					 int vector);
337	void (*send_IPI_allbutself)(int vector);
338	void (*send_IPI_all)(int vector);
339	void (*send_IPI_self)(int vector);
340
341	/* wakeup_secondary_cpu */
342	int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
343
344	int trampoline_phys_low;
345	int trampoline_phys_high;
346
347	void (*wait_for_init_deassert)(atomic_t *deassert);
348	void (*smp_callin_clear_local_apic)(void);
349	void (*inquire_remote_apic)(int apicid);
350
351	/* apic ops */
352	u32 (*read)(u32 reg);
353	void (*write)(u32 reg, u32 v);
354	u64 (*icr_read)(void);
355	void (*icr_write)(u32 low, u32 high);
356	void (*wait_icr_idle)(void);
357	u32 (*safe_wait_icr_idle)(void);
358};
359
360/*
361 * Pointer to the local APIC driver in use on this system (there's
362 * always just one such driver in use - the kernel decides via an
363 * early probing process which one it picks - and then sticks to it):
364 */
365extern struct apic *apic;
366
367/*
368 * APIC functionality to boot other CPUs - only used on SMP:
369 */
370#ifdef CONFIG_SMP
371extern atomic_t init_deasserted;
372extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
373#endif
374
375#ifdef CONFIG_X86_LOCAL_APIC
376static inline u32 apic_read(u32 reg)
377{
378	return apic->read(reg);
379}
380
381static inline void apic_write(u32 reg, u32 val)
382{
383	apic->write(reg, val);
384}
385
386static inline u64 apic_icr_read(void)
387{
388	return apic->icr_read();
389}
390
391static inline void apic_icr_write(u32 low, u32 high)
392{
393	apic->icr_write(low, high);
394}
395
396static inline void apic_wait_icr_idle(void)
397{
398	apic->wait_icr_idle();
399}
400
401static inline u32 safe_apic_wait_icr_idle(void)
402{
403	return apic->safe_wait_icr_idle();
404}
405
406#else /* CONFIG_X86_LOCAL_APIC */
407
408static inline u32 apic_read(u32 reg) { return 0; }
409static inline void apic_write(u32 reg, u32 val) { }
410static inline u64 apic_icr_read(void) { return 0; }
411static inline void apic_icr_write(u32 low, u32 high) { }
412static inline void apic_wait_icr_idle(void) { }
413static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
414
415#endif /* CONFIG_X86_LOCAL_APIC */
416
417static inline void ack_APIC_irq(void)
418{
419	/*
420	 * ack_APIC_irq() actually gets compiled as a single instruction
421	 * ... yummie.
422	 */
423
424	/* Docs say use 0 for future compatibility */
425	apic_write(APIC_EOI, 0);
426}
427
428static inline unsigned default_get_apic_id(unsigned long x)
429{
430	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
431
432	if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
433		return (x >> 24) & 0xFF;
434	else
435		return (x >> 24) & 0x0F;
436}
437
438/*
439 * Warm reset vector default position:
440 */
441#define DEFAULT_TRAMPOLINE_PHYS_LOW		0x467
442#define DEFAULT_TRAMPOLINE_PHYS_HIGH		0x469
443
444#ifdef CONFIG_X86_64
445extern struct apic apic_flat;
446extern struct apic apic_physflat;
447extern struct apic apic_x2apic_cluster;
448extern struct apic apic_x2apic_phys;
449extern int default_acpi_madt_oem_check(char *, char *);
450
451extern void apic_send_IPI_self(int vector);
452
453extern struct apic apic_x2apic_uv_x;
454DECLARE_PER_CPU(int, x2apic_extra_bits);
455
456extern int default_cpu_present_to_apicid(int mps_cpu);
457extern int default_check_phys_apicid_present(int phys_apicid);
458#endif
459
460static inline void default_wait_for_init_deassert(atomic_t *deassert)
461{
462	while (!atomic_read(deassert))
463		cpu_relax();
464	return;
465}
466
467extern void generic_bigsmp_probe(void);
468
469
470#ifdef CONFIG_X86_LOCAL_APIC
471
472#include <asm/smp.h>
473
474#define APIC_DFR_VALUE	(APIC_DFR_FLAT)
475
476static inline const struct cpumask *default_target_cpus(void)
477{
478#ifdef CONFIG_SMP
479	return cpu_online_mask;
480#else
481	return cpumask_of(0);
482#endif
483}
484
485DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
486
487
488static inline unsigned int read_apic_id(void)
489{
490	unsigned int reg;
491
492	reg = apic_read(APIC_ID);
493
494	return apic->get_apic_id(reg);
495}
496
497extern void default_setup_apic_routing(void);
498
499extern struct apic apic_noop;
500
501#ifdef CONFIG_X86_32
502
503extern struct apic apic_default;
504
505/*
506 * Set up the logical destination ID.
507 *
508 * Intel recommends to set DFR, LDR and TPR before enabling
509 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
510 * document number 292116).  So here it goes...
511 */
512extern void default_init_apic_ldr(void);
513
514static inline int default_apic_id_registered(void)
515{
516	return physid_isset(read_apic_id(), phys_cpu_present_map);
517}
518
519static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
520{
521	return cpuid_apic >> index_msb;
522}
523
524extern int default_apicid_to_node(int logical_apicid);
525
526#endif
527
528static inline unsigned int
529default_cpu_mask_to_apicid(const struct cpumask *cpumask)
530{
531	return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
532}
533
534static inline unsigned int
535default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
536			       const struct cpumask *andmask)
537{
538	unsigned long mask1 = cpumask_bits(cpumask)[0];
539	unsigned long mask2 = cpumask_bits(andmask)[0];
540	unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
541
542	return (unsigned int)(mask1 & mask2 & mask3);
543}
544
545static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
546{
547	return physid_isset(apicid, *map);
548}
549
550static inline unsigned long default_check_apicid_present(int bit)
551{
552	return physid_isset(bit, phys_cpu_present_map);
553}
554
555static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
556{
557	*retmap = *phys_map;
558}
559
560/* Mapping from cpu number to logical apicid */
561static inline int default_cpu_to_logical_apicid(int cpu)
562{
563	return 1 << cpu;
564}
565
566static inline int __default_cpu_present_to_apicid(int mps_cpu)
567{
568	if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
569		return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
570	else
571		return BAD_APICID;
572}
573
574static inline int
575__default_check_phys_apicid_present(int phys_apicid)
576{
577	return physid_isset(phys_apicid, phys_cpu_present_map);
578}
579
580#ifdef CONFIG_X86_32
581static inline int default_cpu_present_to_apicid(int mps_cpu)
582{
583	return __default_cpu_present_to_apicid(mps_cpu);
584}
585
586static inline int
587default_check_phys_apicid_present(int phys_apicid)
588{
589	return __default_check_phys_apicid_present(phys_apicid);
590}
591#else
592extern int default_cpu_present_to_apicid(int mps_cpu);
593extern int default_check_phys_apicid_present(int phys_apicid);
594#endif
595
596#endif /* CONFIG_X86_LOCAL_APIC */
597
598#ifdef CONFIG_X86_32
599extern u8 cpu_2_logical_apicid[NR_CPUS];
600#endif
601
602#endif /* _ASM_X86_APIC_H */
603