fpu-internal.h revision 377ffbcc536a5a6666dc077395163ab149c02610 
1/*
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 *	Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
8 */
9
10#ifndef _FPU_INTERNAL_H
11#define _FPU_INTERNAL_H
12
13#include <linux/kernel_stat.h>
14#include <linux/regset.h>
15#include <linux/compat.h>
16#include <linux/slab.h>
17#include <asm/asm.h>
18#include <asm/cpufeature.h>
19#include <asm/processor.h>
20#include <asm/sigcontext.h>
21#include <asm/user.h>
22#include <asm/uaccess.h>
23#include <asm/xsave.h>
24
25#ifdef CONFIG_X86_64
26# include <asm/sigcontext32.h>
27# include <asm/user32.h>
28int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
29			compat_sigset_t *set, struct pt_regs *regs);
30int ia32_setup_frame(int sig, struct k_sigaction *ka,
31		     compat_sigset_t *set, struct pt_regs *regs);
32#else
33# define user_i387_ia32_struct	user_i387_struct
34# define user32_fxsr_struct	user_fxsr_struct
35# define ia32_setup_frame	__setup_frame
36# define ia32_setup_rt_frame	__setup_rt_frame
37#endif
38
39extern unsigned int mxcsr_feature_mask;
40extern void fpu_init(void);
41
42DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
43
44extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
45			      struct task_struct *tsk);
46extern void convert_to_fxsr(struct task_struct *tsk,
47			    const struct user_i387_ia32_struct *env);
48
49extern user_regset_active_fn fpregs_active, xfpregs_active;
50extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
51				xstateregs_get;
52extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
53				 xstateregs_set;
54
55/*
56 * xstateregs_active == fpregs_active. Please refer to the comment
57 * at the definition of fpregs_active.
58 */
59#define xstateregs_active	fpregs_active
60
61#ifdef CONFIG_MATH_EMULATION
62# define HAVE_HWFP		(boot_cpu_data.hard_math)
63extern void finit_soft_fpu(struct i387_soft_struct *soft);
64#else
65# define HAVE_HWFP		1
66static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
67#endif
68
69static inline int is_ia32_compat_frame(void)
70{
71	return config_enabled(CONFIG_IA32_EMULATION) &&
72	       test_thread_flag(TIF_IA32);
73}
74
75static inline int is_ia32_frame(void)
76{
77	return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame();
78}
79
80static inline int is_x32_frame(void)
81{
82	return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
83}
84
85#define X87_FSW_ES (1 << 7)	/* Exception Summary */
86
87static __always_inline __pure bool use_xsaveopt(void)
88{
89	return static_cpu_has(X86_FEATURE_XSAVEOPT);
90}
91
92static __always_inline __pure bool use_xsave(void)
93{
94	return static_cpu_has(X86_FEATURE_XSAVE);
95}
96
97static __always_inline __pure bool use_fxsr(void)
98{
99        return static_cpu_has(X86_FEATURE_FXSR);
100}
101
102extern void __sanitize_i387_state(struct task_struct *);
103
104static inline void sanitize_i387_state(struct task_struct *tsk)
105{
106	if (!use_xsaveopt())
107		return;
108	__sanitize_i387_state(tsk);
109}
110
111#define check_insn(insn, output, input...)				\
112({									\
113	int err;							\
114	asm volatile("1:" #insn "\n\t"					\
115		     "2:\n"						\
116		     ".section .fixup,\"ax\"\n"				\
117		     "3:  movl $-1,%[err]\n"				\
118		     "    jmp  2b\n"					\
119		     ".previous\n"					\
120		     _ASM_EXTABLE(1b, 3b)				\
121		     : [err] "=r" (err), output				\
122		     : "0"(0), input);					\
123	err;								\
124})
125
126static inline int fsave_user(struct i387_fsave_struct __user *fx)
127{
128	return check_insn(fnsave %[fx]; fwait,  [fx] "=m" (*fx), "m" (*fx));
129}
130
131static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
132{
133	if (config_enabled(CONFIG_X86_32))
134		return check_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
135	else if (config_enabled(CONFIG_AS_FXSAVEQ))
136		return check_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
137
138	/* See comment in fpu_fxsave() below. */
139	return check_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
140}
141
142static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
143{
144	if (config_enabled(CONFIG_X86_32))
145		return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
146	else if (config_enabled(CONFIG_AS_FXSAVEQ))
147		return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
148
149	/* See comment in fpu_fxsave() below. */
150	return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
151			  "m" (*fx));
152}
153
154static inline int frstor_checking(struct i387_fsave_struct *fx)
155{
156	return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
157}
158
159static inline void fpu_fxsave(struct fpu *fpu)
160{
161	if (config_enabled(CONFIG_X86_32))
162		asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
163	else if (config_enabled(CONFIG_AS_FXSAVEQ))
164		asm volatile("fxsaveq %0" : "=m" (fpu->state->fxsave));
165	else {
166		/* Using "rex64; fxsave %0" is broken because, if the memory
167		 * operand uses any extended registers for addressing, a second
168		 * REX prefix will be generated (to the assembler, rex64
169		 * followed by semicolon is a separate instruction), and hence
170		 * the 64-bitness is lost.
171		 *
172		 * Using "fxsaveq %0" would be the ideal choice, but is only
173		 * supported starting with gas 2.16.
174		 *
175		 * Using, as a workaround, the properly prefixed form below
176		 * isn't accepted by any binutils version so far released,
177		 * complaining that the same type of prefix is used twice if
178		 * an extended register is needed for addressing (fix submitted
179		 * to mainline 2005-11-21).
180		 *
181		 *  asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
182		 *
183		 * This, however, we can work around by forcing the compiler to
184		 * select an addressing mode that doesn't require extended
185		 * registers.
186		 */
187		asm volatile( "rex64/fxsave (%[fx])"
188			     : "=m" (fpu->state->fxsave)
189			     : [fx] "R" (&fpu->state->fxsave));
190	}
191}
192
193/*
194 * These must be called with preempt disabled. Returns
195 * 'true' if the FPU state is still intact.
196 */
197static inline int fpu_save_init(struct fpu *fpu)
198{
199	if (use_xsave()) {
200		fpu_xsave(fpu);
201
202		/*
203		 * xsave header may indicate the init state of the FP.
204		 */
205		if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
206			return 1;
207	} else if (use_fxsr()) {
208		fpu_fxsave(fpu);
209	} else {
210		asm volatile("fnsave %[fx]; fwait"
211			     : [fx] "=m" (fpu->state->fsave));
212		return 0;
213	}
214
215	/*
216	 * If exceptions are pending, we need to clear them so
217	 * that we don't randomly get exceptions later.
218	 *
219	 * FIXME! Is this perhaps only true for the old-style
220	 * irq13 case? Maybe we could leave the x87 state
221	 * intact otherwise?
222	 */
223	if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
224		asm volatile("fnclex");
225		return 0;
226	}
227	return 1;
228}
229
230static inline int __save_init_fpu(struct task_struct *tsk)
231{
232	return fpu_save_init(&tsk->thread.fpu);
233}
234
235static inline int fpu_restore_checking(struct fpu *fpu)
236{
237	if (use_xsave())
238		return fpu_xrstor_checking(&fpu->state->xsave);
239	else if (use_fxsr())
240		return fxrstor_checking(&fpu->state->fxsave);
241	else
242		return frstor_checking(&fpu->state->fsave);
243}
244
245static inline int restore_fpu_checking(struct task_struct *tsk)
246{
247	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
248	   is pending.  Clear the x87 state here by setting it to fixed
249	   values. "m" is a random variable that should be in L1 */
250	alternative_input(
251		ASM_NOP8 ASM_NOP2,
252		"emms\n\t"		/* clear stack tags */
253		"fildl %P[addr]",	/* set F?P to defined value */
254		X86_FEATURE_FXSAVE_LEAK,
255		[addr] "m" (tsk->thread.fpu.has_fpu));
256
257	return fpu_restore_checking(&tsk->thread.fpu);
258}
259
260/*
261 * Software FPU state helpers. Careful: these need to
262 * be preemption protection *and* they need to be
263 * properly paired with the CR0.TS changes!
264 */
265static inline int __thread_has_fpu(struct task_struct *tsk)
266{
267	return tsk->thread.fpu.has_fpu;
268}
269
270/* Must be paired with an 'stts' after! */
271static inline void __thread_clear_has_fpu(struct task_struct *tsk)
272{
273	tsk->thread.fpu.has_fpu = 0;
274	this_cpu_write(fpu_owner_task, NULL);
275}
276
277/* Must be paired with a 'clts' before! */
278static inline void __thread_set_has_fpu(struct task_struct *tsk)
279{
280	tsk->thread.fpu.has_fpu = 1;
281	this_cpu_write(fpu_owner_task, tsk);
282}
283
284/*
285 * Encapsulate the CR0.TS handling together with the
286 * software flag.
287 *
288 * These generally need preemption protection to work,
289 * do try to avoid using these on their own.
290 */
291static inline void __thread_fpu_end(struct task_struct *tsk)
292{
293	__thread_clear_has_fpu(tsk);
294	stts();
295}
296
297static inline void __thread_fpu_begin(struct task_struct *tsk)
298{
299	clts();
300	__thread_set_has_fpu(tsk);
301}
302
303/*
304 * FPU state switching for scheduling.
305 *
306 * This is a two-stage process:
307 *
308 *  - switch_fpu_prepare() saves the old state and
309 *    sets the new state of the CR0.TS bit. This is
310 *    done within the context of the old process.
311 *
312 *  - switch_fpu_finish() restores the new state as
313 *    necessary.
314 */
315typedef struct { int preload; } fpu_switch_t;
316
317/*
318 * FIXME! We could do a totally lazy restore, but we need to
319 * add a per-cpu "this was the task that last touched the FPU
320 * on this CPU" variable, and the task needs to have a "I last
321 * touched the FPU on this CPU" and check them.
322 *
323 * We don't do that yet, so "fpu_lazy_restore()" always returns
324 * false, but some day..
325 */
326static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
327{
328	return new == this_cpu_read_stable(fpu_owner_task) &&
329		cpu == new->thread.fpu.last_cpu;
330}
331
332static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
333{
334	fpu_switch_t fpu;
335
336	fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
337	if (__thread_has_fpu(old)) {
338		if (!__save_init_fpu(old))
339			cpu = ~0;
340		old->thread.fpu.last_cpu = cpu;
341		old->thread.fpu.has_fpu = 0;	/* But leave fpu_owner_task! */
342
343		/* Don't change CR0.TS if we just switch! */
344		if (fpu.preload) {
345			new->fpu_counter++;
346			__thread_set_has_fpu(new);
347			prefetch(new->thread.fpu.state);
348		} else
349			stts();
350	} else {
351		old->fpu_counter = 0;
352		old->thread.fpu.last_cpu = ~0;
353		if (fpu.preload) {
354			new->fpu_counter++;
355			if (fpu_lazy_restore(new, cpu))
356				fpu.preload = 0;
357			else
358				prefetch(new->thread.fpu.state);
359			__thread_fpu_begin(new);
360		}
361	}
362	return fpu;
363}
364
365/*
366 * By the time this gets called, we've already cleared CR0.TS and
367 * given the process the FPU if we are going to preload the FPU
368 * state - all we need to do is to conditionally restore the register
369 * state itself.
370 */
371static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
372{
373	if (fpu.preload) {
374		if (unlikely(restore_fpu_checking(new)))
375			__thread_fpu_end(new);
376	}
377}
378
379/*
380 * Signal frame handlers...
381 */
382extern int save_xstate_sig(void __user *buf, void __user *fx, int size);
383extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size);
384
385static inline int xstate_sigframe_size(void)
386{
387	return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
388}
389
390static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
391{
392	void __user *buf_fx = buf;
393	int size = xstate_sigframe_size();
394
395	if (ia32_frame && use_fxsr()) {
396		buf_fx = buf + sizeof(struct i387_fsave_struct);
397		size += sizeof(struct i387_fsave_struct);
398	}
399
400	return __restore_xstate_sig(buf, buf_fx, size);
401}
402
403static inline void __drop_fpu(struct task_struct *tsk)
404{
405	if (__thread_has_fpu(tsk)) {
406		/* Ignore delayed exceptions from user space */
407		asm volatile("1: fwait\n"
408			     "2:\n"
409			     _ASM_EXTABLE(1b, 2b));
410		__thread_fpu_end(tsk);
411	}
412}
413
414/*
415 * Need to be preemption-safe.
416 *
417 * NOTE! user_fpu_begin() must be used only immediately before restoring
418 * it. This function does not do any save/restore on their own.
419 */
420static inline void user_fpu_begin(void)
421{
422	preempt_disable();
423	if (!user_has_fpu())
424		__thread_fpu_begin(current);
425	preempt_enable();
426}
427
428/*
429 * These disable preemption on their own and are safe
430 */
431static inline void save_init_fpu(struct task_struct *tsk)
432{
433	WARN_ON_ONCE(!__thread_has_fpu(tsk));
434	preempt_disable();
435	__save_init_fpu(tsk);
436	__thread_fpu_end(tsk);
437	preempt_enable();
438}
439
440static inline void drop_fpu(struct task_struct *tsk)
441{
442	/*
443	 * Forget coprocessor state..
444	 */
445	tsk->fpu_counter = 0;
446	preempt_disable();
447	__drop_fpu(tsk);
448	preempt_enable();
449	clear_used_math();
450}
451
452/*
453 * i387 state interaction
454 */
455static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
456{
457	if (cpu_has_fxsr) {
458		return tsk->thread.fpu.state->fxsave.cwd;
459	} else {
460		return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
461	}
462}
463
464static inline unsigned short get_fpu_swd(struct task_struct *tsk)
465{
466	if (cpu_has_fxsr) {
467		return tsk->thread.fpu.state->fxsave.swd;
468	} else {
469		return (unsigned short)tsk->thread.fpu.state->fsave.swd;
470	}
471}
472
473static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
474{
475	if (cpu_has_xmm) {
476		return tsk->thread.fpu.state->fxsave.mxcsr;
477	} else {
478		return MXCSR_DEFAULT;
479	}
480}
481
482static bool fpu_allocated(struct fpu *fpu)
483{
484	return fpu->state != NULL;
485}
486
487static inline int fpu_alloc(struct fpu *fpu)
488{
489	if (fpu_allocated(fpu))
490		return 0;
491	fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
492	if (!fpu->state)
493		return -ENOMEM;
494	WARN_ON((unsigned long)fpu->state & 15);
495	return 0;
496}
497
498static inline void fpu_free(struct fpu *fpu)
499{
500	if (fpu->state) {
501		kmem_cache_free(task_xstate_cachep, fpu->state);
502		fpu->state = NULL;
503	}
504}
505
506static inline void fpu_copy(struct fpu *dst, struct fpu *src)
507{
508	memcpy(dst->state, src->state, xstate_size);
509}
510
511extern void fpu_finit(struct fpu *fpu);
512
513static inline unsigned long
514alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
515		unsigned long *size)
516{
517	unsigned long frame_size = xstate_sigframe_size();
518
519	*buf_fx = sp = round_down(sp - frame_size, 64);
520	if (ia32_frame && use_fxsr()) {
521		frame_size += sizeof(struct i387_fsave_struct);
522		sp -= sizeof(struct i387_fsave_struct);
523	}
524
525	*size = frame_size;
526	return sp;
527}
528
529#endif
530