11965aae3c98397aad957412413c07e97b1bd4e64H. Peter Anvin#ifndef _ASM_X86_PGTABLE_3LEVEL_H 21965aae3c98397aad957412413c07e97b1bd4e64H. Peter Anvin#define _ASM_X86_PGTABLE_3LEVEL_H 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Intel Physical Address Extension (PAE) Mode - three-level page 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * tables on PPro+ CPUs. 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com> 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 114b01fef89a10cedbae9857e76283616af3f177cdJoe Perches#define pte_ERROR(e) \ 12c767a54ba0657e52e6edaa97cbe0b0a8bf1c1655Joe Perches pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \ 134b01fef89a10cedbae9857e76283616af3f177cdJoe Perches __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) 144b01fef89a10cedbae9857e76283616af3f177cdJoe Perches#define pmd_ERROR(e) \ 15c767a54ba0657e52e6edaa97cbe0b0a8bf1c1655Joe Perches pr_err("%s:%d: bad pmd %p(%016Lx)\n", \ 164b01fef89a10cedbae9857e76283616af3f177cdJoe Perches __FILE__, __LINE__, &(e), pmd_val(e)) 174b01fef89a10cedbae9857e76283616af3f177cdJoe Perches#define pgd_ERROR(e) \ 18c767a54ba0657e52e6edaa97cbe0b0a8bf1c1655Joe Perches pr_err("%s:%d: bad pgd %p(%016Lx)\n", \ 194b01fef89a10cedbae9857e76283616af3f177cdJoe Perches __FILE__, __LINE__, &(e), pgd_val(e)) 206194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Rules for using set_pte: the pte being assigned *must* be 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * either not present or in a state where the hardware will 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * not attempt to update the pte. In places where this is 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * not possible, use pte_get_and_clear to obtain the old pte 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * value and then use set_pte to update it. -ben 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 273dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardingestatic inline void native_set_pte(pte_t *ptep, pte_t pte) 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ptep->pte_high = pte.pte_high; 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds smp_wmb(); 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ptep->pte_low = pte.pte_low; 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3426c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli#define pmd_read_atomic pmd_read_atomic 3526c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli/* 3626c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * pte_offset_map_lock on 32bit PAE kernels was reading the pmd_t with 3726c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * a "*pmdp" dereference done by gcc. Problem is, in certain places 3826c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * where pte_offset_map_lock is called, concurrent page faults are 3926c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * allowed, if the mmap_sem is hold for reading. An example is mincore 4026c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * vs page faults vs MADV_DONTNEED. On the page fault side 4126c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * pmd_populate rightfully does a set_64bit, but if we're reading the 4226c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * pmd_t with a "*pmdp" on the mincore side, a SMP race can happen 4326c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * because gcc will not read the 64bit of the pmd atomically. To fix 4426c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * this all places running pmd_offset_map_lock() while holding the 4526c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * mmap_sem in read mode, shall read the pmdp pointer using this 4626c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * function to know if the pmd is null nor not, and in turn to know if 4726c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * they can run pmd_offset_map_lock or pmd_trans_huge or other pmd 4826c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * operations. 4926c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * 50e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * Without THP if the mmap_sem is hold for reading, the pmd can only 51e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * transition from null to not null while pmd_read_atomic runs. So 52e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * we can always return atomic pmd values with this function. 5326c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * 5426c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * With THP if the mmap_sem is hold for reading, the pmd can become 55e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * trans_huge or none or point to a pte (and in turn become "stable") 56e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * at any time under pmd_read_atomic. We could read it really 57e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * atomically here with a atomic64_read for the THP enabled case (and 58e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * it would be a whole lot simpler), but to avoid using cmpxchg8b we 59e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * only return an atomic pmdval if the low part of the pmdval is later 60e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * found stable (i.e. pointing to a pte). And we're returning a none 61e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * pmdval if the low part of the pmd is none. In some cases the high 62e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * and low part of the pmdval returned may not be consistent if THP is 63e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * enabled (the low part may point to previously mapped hugepage, 64e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * while the high part may point to a more recently mapped hugepage), 65e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * but pmd_none_or_trans_huge_or_clear_bad() only needs the low part 66e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * of the pmd to be read atomically to decide if the pmd is unstable 67e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * or not, with the only exception of when the low part of the pmd is 68e4eed03fd06578571c01d4f1478c874bb432c815Andrea Arcangeli * zero in which case we return a none pmd. 6926c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli */ 7026c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangelistatic inline pmd_t pmd_read_atomic(pmd_t *pmdp) 7126c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli{ 7226c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli pmdval_t ret; 7326c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli u32 *tmp = (u32 *)pmdp; 7426c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli 7526c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli ret = (pmdval_t) (*tmp); 7626c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli if (ret) { 7726c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli /* 7826c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * If the low part is null, we must not read the high part 7926c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli * or we can end up with a partial pmd. 8026c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli */ 8126c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli smp_rmb(); 8226c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli ret |= ((pmdval_t)*(tmp + 1)) << 32; 8326c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli } 8426c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli 8526c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli return (pmd_t) { ret }; 8626c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli} 8726c191788f18129af0eb32a358cdaea0c7479626Andrea Arcangeli 883dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardingestatic inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) 893dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge{ 904b01fef89a10cedbae9857e76283616af3f177cdJoe Perches set_64bit((unsigned long long *)(ptep), native_pte_val(pte)); 913dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge} 924b01fef89a10cedbae9857e76283616af3f177cdJoe Perches 933dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardingestatic inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) 943dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge{ 954b01fef89a10cedbae9857e76283616af3f177cdJoe Perches set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd)); 963dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge} 974b01fef89a10cedbae9857e76283616af3f177cdJoe Perches 983dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardingestatic inline void native_set_pud(pud_t *pudp, pud_t pud) 993dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge{ 1004b01fef89a10cedbae9857e76283616af3f177cdJoe Perches set_64bit((unsigned long long *)(pudp), native_pud_val(pud)); 1013dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge} 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1046e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden * For PTEs and PDEs, we must clear the P-bit first when clearing a page table 1056e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden * entry, so clear the bottom half first and enforce ordering with a compiler 1066e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden * barrier. 1076e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden */ 1084b01fef89a10cedbae9857e76283616af3f177cdJoe Perchesstatic inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, 1094b01fef89a10cedbae9857e76283616af3f177cdJoe Perches pte_t *ptep) 1106e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden{ 1116e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden ptep->pte_low = 0; 1126e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden smp_wmb(); 1136e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden ptep->pte_high = 0; 1146e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden} 1156e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden 1163dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardingestatic inline void native_pmd_clear(pmd_t *pmd) 1176e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden{ 1186e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden u32 *tmp = (u32 *)pmd; 1196e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden *tmp = 0; 1206e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden smp_wmb(); 1216e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden *(tmp + 1) = 0; 1226e5882cfa24e1456702e463f6920fc0ca3c3d2b8Zachary Amsden} 1233dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardinge 1246194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardingestatic inline void pud_clear(pud_t *pudp) 1256194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge{ 1266194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge set_pud(pudp, __pud(0)); 1276194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge 1286194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge /* 129f5430f93257d336346a9018c915e879ce43f5f89Jeremy Fitzhardinge * According to Intel App note "TLBs, Paging-Structure Caches, 130f5430f93257d336346a9018c915e879ce43f5f89Jeremy Fitzhardinge * and Their Invalidation", April 2007, document 317080-001, 131f5430f93257d336346a9018c915e879ce43f5f89Jeremy Fitzhardinge * section 8.1: in PAE mode we explicitly have to flush the 132f5430f93257d336346a9018c915e879ce43f5f89Jeremy Fitzhardinge * TLB via cr3 if the top-level pgd is changed... 1336194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge * 1344981d01eada5354d81c8929d5b2836829ba3df7bShaohua Li * Currently all places where pud_clear() is called either have 1354981d01eada5354d81c8929d5b2836829ba3df7bShaohua Li * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or 1364981d01eada5354d81c8929d5b2836829ba3df7bShaohua Li * pud_clear_bad()), so we don't need TLB flush here. 1376194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge */ 1386194ba6ff6ccf8d5c54c857600843c67aa82c407Jeremy Fitzhardinge} 139da181a8b3916aa7f2e3c5775d2bd2fe3454cf82dRusty Russell 140142dd975911fdd82b1b6f6617cd20ac90a8ccf00Zachary Amsden#ifdef CONFIG_SMP 1413dc494e86d1c93afd4c66385f270899dbfae483dJeremy Fitzhardingestatic inline pte_t native_ptep_get_and_clear(pte_t *ptep) 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pte_t res; 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* xchg acts as a barrier before the setting of the high bits */ 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds res.pte_low = xchg(&ptep->pte_low, 0); 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds res.pte_high = ptep->pte_high; 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ptep->pte_high = 0; 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return res; 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 152142dd975911fdd82b1b6f6617cd20ac90a8ccf00Zachary Amsden#else 153142dd975911fdd82b1b6f6617cd20ac90a8ccf00Zachary Amsden#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) 154142dd975911fdd82b1b6f6617cd20ac90a8ccf00Zachary Amsden#endif 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 156f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner#ifdef CONFIG_SMP 157f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weinerunion split_pmd { 158f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner struct { 159f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner u32 pmd_low; 160f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner u32 pmd_high; 161f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner }; 162f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner pmd_t pmd; 163f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner}; 164f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weinerstatic inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp) 165f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner{ 166f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner union split_pmd res, *orig = (union split_pmd *)pmdp; 167f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner 168f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner /* xchg acts as a barrier before setting of the high bits */ 169f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner res.pmd_low = xchg(&orig->pmd_low, 0); 170f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner res.pmd_high = orig->pmd_high; 171f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner orig->pmd_high = 0; 172f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner 173f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner return res.pmd; 174f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner} 175f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner#else 176f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp) 177f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner#endif 178f2d6bfe9ff0acec30b713614260e78b03d20e909Johannes Weiner 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Bits 0, 6 and 7 are taken in the low part of the pte, 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * put the 32 bits of offset into the high part. 18241bb3476b361ef38576cf9d539b19bae2ac93167Cyrill Gorcunov * 18341bb3476b361ef38576cf9d539b19bae2ac93167Cyrill Gorcunov * For soft-dirty tracking 11 bit is taken from 18441bb3476b361ef38576cf9d539b19bae2ac93167Cyrill Gorcunov * the low part of pte as well. 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define pte_to_pgoff(pte) ((pte).pte_high) 1874b01fef89a10cedbae9857e76283616af3f177cdJoe Perches#define pgoff_to_pte(off) \ 1884b01fef89a10cedbae9857e76283616af3f177cdJoe Perches ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } }) 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PTE_FILE_MAX_BITS 32 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Encode and de-code a swap entry */ 1921796316a8b028a148be48ba5d4e7be493a39d173Jan Beulich#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5) 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __swp_type(x) (((x).val) & 0x1f) 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __swp_offset(x) ((x).val >> 5) 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5}) 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high }) 197c8e5393ab38564d2f45b560a2f95bc8f9ff6f823Jeremy Fitzhardinge#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } }) 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1991965aae3c98397aad957412413c07e97b1bd4e64H. Peter Anvin#endif /* _ASM_X86_PGTABLE_3LEVEL_H */ 200