1#include <linux/kernel.h> 2 3#include <linux/string.h> 4#include <linux/bitops.h> 5#include <linux/smp.h> 6#include <linux/sched.h> 7#include <linux/thread_info.h> 8#include <linux/module.h> 9#include <linux/uaccess.h> 10 11#include <asm/processor.h> 12#include <asm/pgtable.h> 13#include <asm/msr.h> 14#include <asm/bugs.h> 15#include <asm/cpu.h> 16 17#ifdef CONFIG_X86_64 18#include <linux/topology.h> 19#endif 20 21#include "cpu.h" 22 23#ifdef CONFIG_X86_LOCAL_APIC 24#include <asm/mpspec.h> 25#include <asm/apic.h> 26#endif 27 28static void early_init_intel(struct cpuinfo_x86 *c) 29{ 30 u64 misc_enable; 31 32 /* Unmask CPUID levels if masked: */ 33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) { 36 c->cpuid_level = cpuid_eax(0); 37 get_cpu_cap(c); 38 } 39 } 40 41 if ((c->x86 == 0xf && c->x86_model >= 0x03) || 42 (c->x86 == 0x6 && c->x86_model >= 0x0e)) 43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 44 45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) { 46 unsigned lower_word; 47 48 wrmsr(MSR_IA32_UCODE_REV, 0, 0); 49 /* Required by the SDM */ 50 sync_core(); 51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode); 52 } 53 54 /* 55 * Atom erratum AAE44/AAF40/AAG38/AAH41: 56 * 57 * A race condition between speculative fetches and invalidating 58 * a large page. This is worked around in microcode, but we 59 * need the microcode to have already been loaded... so if it is 60 * not, recommend a BIOS update and disable large pages. 61 */ 62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 && 63 c->microcode < 0x20e) { 64 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n"); 65 clear_cpu_cap(c, X86_FEATURE_PSE); 66 } 67 68#ifdef CONFIG_X86_64 69 set_cpu_cap(c, X86_FEATURE_SYSENTER32); 70#else 71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ 72 if (c->x86 == 15 && c->x86_cache_alignment == 64) 73 c->x86_cache_alignment = 128; 74#endif 75 76 /* CPUID workaround for 0F33/0F34 CPU */ 77 if (c->x86 == 0xF && c->x86_model == 0x3 78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4)) 79 c->x86_phys_bits = 36; 80 81 /* 82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 83 * with P/T states and does not stop in deep C-states. 84 * 85 * It is also reliable across cores and sockets. (but not across 86 * cabinets - we turn it off in that case explicitly.) 87 */ 88 if (c->x86_power & (1 << 8)) { 89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 91 if (!check_tsc_unstable()) 92 set_sched_clock_stable(); 93 } 94 95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ 96 if (c->x86 == 6) { 97 switch (c->x86_model) { 98 case 0x27: /* Penwell */ 99 case 0x35: /* Cloverview */ 100 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); 101 break; 102 default: 103 break; 104 } 105 } 106 107 /* 108 * There is a known erratum on Pentium III and Core Solo 109 * and Core Duo CPUs. 110 * " Page with PAT set to WC while associated MTRR is UC 111 * may consolidate to UC " 112 * Because of this erratum, it is better to stick with 113 * setting WC in MTRR rather than using PAT on these CPUs. 114 * 115 * Enable PAT WC only on P4, Core 2 or later CPUs. 116 */ 117 if (c->x86 == 6 && c->x86_model < 15) 118 clear_cpu_cap(c, X86_FEATURE_PAT); 119 120#ifdef CONFIG_KMEMCHECK 121 /* 122 * P4s have a "fast strings" feature which causes single- 123 * stepping REP instructions to only generate a #DB on 124 * cache-line boundaries. 125 * 126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon 127 * (model 2) with the same problem. 128 */ 129 if (c->x86 == 15) 130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE, 131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0) 132 pr_info("kmemcheck: Disabling fast string operations\n"); 133#endif 134 135 /* 136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 137 * clear the fast string and enhanced fast string CPU capabilities. 138 */ 139 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { 140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); 141 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) { 142 printk(KERN_INFO "Disabled fast string operations\n"); 143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD); 144 setup_clear_cpu_cap(X86_FEATURE_ERMS); 145 } 146 } 147 148 /* 149 * Intel Quark Core DevMan_001.pdf section 6.4.11 150 * "The operating system also is required to invalidate (i.e., flush) 151 * the TLB when any changes are made to any of the page table entries. 152 * The operating system must reload CR3 to cause the TLB to be flushed" 153 * 154 * As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should 155 * be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE 156 * to be modified 157 */ 158 if (c->x86 == 5 && c->x86_model == 9) { 159 pr_info("Disabling PGE capability bit\n"); 160 setup_clear_cpu_cap(X86_FEATURE_PGE); 161 } 162} 163 164#ifdef CONFIG_X86_32 165/* 166 * Early probe support logic for ppro memory erratum #50 167 * 168 * This is called before we do cpu ident work 169 */ 170 171int ppro_with_ram_bug(void) 172{ 173 /* Uses data from early_cpu_detect now */ 174 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && 175 boot_cpu_data.x86 == 6 && 176 boot_cpu_data.x86_model == 1 && 177 boot_cpu_data.x86_mask < 8) { 178 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n"); 179 return 1; 180 } 181 return 0; 182} 183 184static void intel_smp_check(struct cpuinfo_x86 *c) 185{ 186 /* calling is from identify_secondary_cpu() ? */ 187 if (!c->cpu_index) 188 return; 189 190 /* 191 * Mask B, Pentium, but not Pentium MMX 192 */ 193 if (c->x86 == 5 && 194 c->x86_mask >= 1 && c->x86_mask <= 4 && 195 c->x86_model <= 3) { 196 /* 197 * Remember we have B step Pentia with bugs 198 */ 199 WARN_ONCE(1, "WARNING: SMP operation may be unreliable" 200 "with B stepping processors.\n"); 201 } 202} 203 204static int forcepae; 205static int __init forcepae_setup(char *__unused) 206{ 207 forcepae = 1; 208 return 1; 209} 210__setup("forcepae", forcepae_setup); 211 212static void intel_workarounds(struct cpuinfo_x86 *c) 213{ 214#ifdef CONFIG_X86_F00F_BUG 215 /* 216 * All models of Pentium and Pentium with MMX technology CPUs 217 * have the F0 0F bug, which lets nonprivileged users lock up the 218 * system. Announce that the fault handler will be checking for it. 219 * The Quark is also family 5, but does not have the same bug. 220 */ 221 clear_cpu_bug(c, X86_BUG_F00F); 222 if (!paravirt_enabled() && c->x86 == 5 && c->x86_model < 9) { 223 static int f00f_workaround_enabled; 224 225 set_cpu_bug(c, X86_BUG_F00F); 226 if (!f00f_workaround_enabled) { 227 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n"); 228 f00f_workaround_enabled = 1; 229 } 230 } 231#endif 232 233 /* 234 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until 235 * model 3 mask 3 236 */ 237 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) 238 clear_cpu_cap(c, X86_FEATURE_SEP); 239 240 /* 241 * PAE CPUID issue: many Pentium M report no PAE but may have a 242 * functionally usable PAE implementation. 243 * Forcefully enable PAE if kernel parameter "forcepae" is present. 244 */ 245 if (forcepae) { 246 printk(KERN_WARNING "PAE forced!\n"); 247 set_cpu_cap(c, X86_FEATURE_PAE); 248 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 249 } 250 251 /* 252 * P4 Xeon errata 037 workaround. 253 * Hardware prefetcher may cause stale data to be loaded into the cache. 254 */ 255 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) { 256 if (msr_set_bit(MSR_IA32_MISC_ENABLE, 257 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 258 > 0) { 259 pr_info("CPU: C0 stepping P4 Xeon detected.\n"); 260 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n"); 261 } 262 } 263 264 /* 265 * See if we have a good local APIC by checking for buggy Pentia, 266 * i.e. all B steppings and the C2 stepping of P54C when using their 267 * integrated APIC (see 11AP erratum in "Pentium Processor 268 * Specification Update"). 269 */ 270 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 && 271 (c->x86_mask < 0x6 || c->x86_mask == 0xb)) 272 set_cpu_bug(c, X86_BUG_11AP); 273 274 275#ifdef CONFIG_X86_INTEL_USERCOPY 276 /* 277 * Set up the preferred alignment for movsl bulk memory moves 278 */ 279 switch (c->x86) { 280 case 4: /* 486: untested */ 281 break; 282 case 5: /* Old Pentia: untested */ 283 break; 284 case 6: /* PII/PIII only like movsl with 8-byte alignment */ 285 movsl_mask.mask = 7; 286 break; 287 case 15: /* P4 is OK down to 8-byte alignment */ 288 movsl_mask.mask = 7; 289 break; 290 } 291#endif 292 293 intel_smp_check(c); 294} 295#else 296static void intel_workarounds(struct cpuinfo_x86 *c) 297{ 298} 299#endif 300 301static void srat_detect_node(struct cpuinfo_x86 *c) 302{ 303#ifdef CONFIG_NUMA 304 unsigned node; 305 int cpu = smp_processor_id(); 306 307 /* Don't do the funky fallback heuristics the AMD version employs 308 for now. */ 309 node = numa_cpu_node(cpu); 310 if (node == NUMA_NO_NODE || !node_online(node)) { 311 /* reuse the value from init_cpu_to_node() */ 312 node = cpu_to_node(cpu); 313 } 314 numa_set_node(cpu, node); 315#endif 316} 317 318/* 319 * find out the number of processor cores on the die 320 */ 321static int intel_num_cpu_cores(struct cpuinfo_x86 *c) 322{ 323 unsigned int eax, ebx, ecx, edx; 324 325 if (c->cpuid_level < 4) 326 return 1; 327 328 /* Intel has a non-standard dependency on %ecx for this CPUID level. */ 329 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); 330 if (eax & 0x1f) 331 return (eax >> 26) + 1; 332 else 333 return 1; 334} 335 336static void detect_vmx_virtcap(struct cpuinfo_x86 *c) 337{ 338 /* Intel VMX MSR indicated features */ 339#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000 340#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000 341#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000 342#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001 343#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002 344#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020 345 346 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2; 347 348 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 349 clear_cpu_cap(c, X86_FEATURE_VNMI); 350 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 351 clear_cpu_cap(c, X86_FEATURE_EPT); 352 clear_cpu_cap(c, X86_FEATURE_VPID); 353 354 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); 355 msr_ctl = vmx_msr_high | vmx_msr_low; 356 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW) 357 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW); 358 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI) 359 set_cpu_cap(c, X86_FEATURE_VNMI); 360 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) { 361 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, 362 vmx_msr_low, vmx_msr_high); 363 msr_ctl2 = vmx_msr_high | vmx_msr_low; 364 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) && 365 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)) 366 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY); 367 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) 368 set_cpu_cap(c, X86_FEATURE_EPT); 369 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID) 370 set_cpu_cap(c, X86_FEATURE_VPID); 371 } 372} 373 374static void init_intel(struct cpuinfo_x86 *c) 375{ 376 unsigned int l2 = 0; 377 378 early_init_intel(c); 379 380 intel_workarounds(c); 381 382 /* 383 * Detect the extended topology information if available. This 384 * will reinitialise the initial_apicid which will be used 385 * in init_intel_cacheinfo() 386 */ 387 detect_extended_topology(c); 388 389 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { 390 /* 391 * let's use the legacy cpuid vector 0x1 and 0x4 for topology 392 * detection. 393 */ 394 c->x86_max_cores = intel_num_cpu_cores(c); 395#ifdef CONFIG_X86_32 396 detect_ht(c); 397#endif 398 } 399 400 l2 = init_intel_cacheinfo(c); 401 402 /* Detect legacy cache sizes if init_intel_cacheinfo did not */ 403 if (l2 == 0) { 404 cpu_detect_cache_sizes(c); 405 l2 = c->x86_cache_size; 406 } 407 408 if (c->cpuid_level > 9) { 409 unsigned eax = cpuid_eax(10); 410 /* Check for version and the number of counters */ 411 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) 412 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); 413 } 414 415 if (cpu_has_xmm2) 416 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 417 if (cpu_has_ds) { 418 unsigned int l1; 419 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); 420 if (!(l1 & (1<<11))) 421 set_cpu_cap(c, X86_FEATURE_BTS); 422 if (!(l1 & (1<<12))) 423 set_cpu_cap(c, X86_FEATURE_PEBS); 424 } 425 426 if (c->x86 == 6 && cpu_has_clflush && 427 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) 428 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); 429 430#ifdef CONFIG_X86_64 431 if (c->x86 == 15) 432 c->x86_cache_alignment = c->x86_clflush_size * 2; 433 if (c->x86 == 6) 434 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 435#else 436 /* 437 * Names for the Pentium II/Celeron processors 438 * detectable only by also checking the cache size. 439 * Dixon is NOT a Celeron. 440 */ 441 if (c->x86 == 6) { 442 char *p = NULL; 443 444 switch (c->x86_model) { 445 case 5: 446 if (l2 == 0) 447 p = "Celeron (Covington)"; 448 else if (l2 == 256) 449 p = "Mobile Pentium II (Dixon)"; 450 break; 451 452 case 6: 453 if (l2 == 128) 454 p = "Celeron (Mendocino)"; 455 else if (c->x86_mask == 0 || c->x86_mask == 5) 456 p = "Celeron-A"; 457 break; 458 459 case 8: 460 if (l2 == 128) 461 p = "Celeron (Coppermine)"; 462 break; 463 } 464 465 if (p) 466 strcpy(c->x86_model_id, p); 467 } 468 469 if (c->x86 == 15) 470 set_cpu_cap(c, X86_FEATURE_P4); 471 if (c->x86 == 6) 472 set_cpu_cap(c, X86_FEATURE_P3); 473#endif 474 475 /* Work around errata */ 476 srat_detect_node(c); 477 478 if (cpu_has(c, X86_FEATURE_VMX)) 479 detect_vmx_virtcap(c); 480 481 /* 482 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not. 483 * x86_energy_perf_policy(8) is available to change it at run-time 484 */ 485 if (cpu_has(c, X86_FEATURE_EPB)) { 486 u64 epb; 487 488 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 489 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) { 490 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:" 491 " Set to 'normal', was 'performance'\n" 492 "ENERGY_PERF_BIAS: View and update with" 493 " x86_energy_perf_policy(8)\n"); 494 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL; 495 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb); 496 } 497 } 498} 499 500#ifdef CONFIG_X86_32 501static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 502{ 503 /* 504 * Intel PIII Tualatin. This comes in two flavours. 505 * One has 256kb of cache, the other 512. We have no way 506 * to determine which, so we use a boottime override 507 * for the 512kb model, and assume 256 otherwise. 508 */ 509 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) 510 size = 256; 511 512 /* 513 * Intel Quark SoC X1000 contains a 4-way set associative 514 * 16K cache with a 16 byte cache line and 256 lines per tag 515 */ 516 if ((c->x86 == 5) && (c->x86_model == 9)) 517 size = 16; 518 return size; 519} 520#endif 521 522#define TLB_INST_4K 0x01 523#define TLB_INST_4M 0x02 524#define TLB_INST_2M_4M 0x03 525 526#define TLB_INST_ALL 0x05 527#define TLB_INST_1G 0x06 528 529#define TLB_DATA_4K 0x11 530#define TLB_DATA_4M 0x12 531#define TLB_DATA_2M_4M 0x13 532#define TLB_DATA_4K_4M 0x14 533 534#define TLB_DATA_1G 0x16 535 536#define TLB_DATA0_4K 0x21 537#define TLB_DATA0_4M 0x22 538#define TLB_DATA0_2M_4M 0x23 539 540#define STLB_4K 0x41 541#define STLB_4K_2M 0x42 542 543static const struct _tlb_table intel_tlb_table[] = { 544 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" }, 545 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" }, 546 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" }, 547 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" }, 548 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" }, 549 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" }, 550 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" }, 551 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 552 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 553 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" }, 554 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 555 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" }, 556 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" }, 557 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" }, 558 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" }, 559 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" }, 560 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" }, 561 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, 562 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, 563 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, 564 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, 565 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, 566 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, 567 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 568 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 569 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 570 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" }, 571 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" }, 572 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 573 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 574 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 575 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" }, 576 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" }, 577 { 0x00, 0, 0 } 578}; 579 580static void intel_tlb_lookup(const unsigned char desc) 581{ 582 unsigned char k; 583 if (desc == 0) 584 return; 585 586 /* look up this descriptor in the table */ 587 for (k = 0; intel_tlb_table[k].descriptor != desc && \ 588 intel_tlb_table[k].descriptor != 0; k++) 589 ; 590 591 if (intel_tlb_table[k].tlb_type == 0) 592 return; 593 594 switch (intel_tlb_table[k].tlb_type) { 595 case STLB_4K: 596 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 597 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 598 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 599 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 600 break; 601 case STLB_4K_2M: 602 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 603 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 604 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 605 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 606 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 607 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 608 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 609 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 610 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 611 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 612 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 613 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 614 break; 615 case TLB_INST_ALL: 616 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 617 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 618 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 619 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 620 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 621 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 622 break; 623 case TLB_INST_4K: 624 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) 625 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; 626 break; 627 case TLB_INST_4M: 628 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 629 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 630 break; 631 case TLB_INST_2M_4M: 632 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) 633 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; 634 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) 635 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; 636 break; 637 case TLB_DATA_4K: 638 case TLB_DATA0_4K: 639 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 640 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 641 break; 642 case TLB_DATA_4M: 643 case TLB_DATA0_4M: 644 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 645 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 646 break; 647 case TLB_DATA_2M_4M: 648 case TLB_DATA0_2M_4M: 649 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) 650 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; 651 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 652 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 653 break; 654 case TLB_DATA_4K_4M: 655 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) 656 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; 657 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) 658 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; 659 break; 660 case TLB_DATA_1G: 661 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) 662 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; 663 break; 664 } 665} 666 667static void intel_detect_tlb(struct cpuinfo_x86 *c) 668{ 669 int i, j, n; 670 unsigned int regs[4]; 671 unsigned char *desc = (unsigned char *)regs; 672 673 if (c->cpuid_level < 2) 674 return; 675 676 /* Number of times to iterate */ 677 n = cpuid_eax(2) & 0xFF; 678 679 for (i = 0 ; i < n ; i++) { 680 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); 681 682 /* If bit 31 is set, this is an unknown format */ 683 for (j = 0 ; j < 3 ; j++) 684 if (regs[j] & (1 << 31)) 685 regs[j] = 0; 686 687 /* Byte 0 is level count, not a descriptor */ 688 for (j = 1 ; j < 16 ; j++) 689 intel_tlb_lookup(desc[j]); 690 } 691} 692 693static const struct cpu_dev intel_cpu_dev = { 694 .c_vendor = "Intel", 695 .c_ident = { "GenuineIntel" }, 696#ifdef CONFIG_X86_32 697 .legacy_models = { 698 { .family = 4, .model_names = 699 { 700 [0] = "486 DX-25/33", 701 [1] = "486 DX-50", 702 [2] = "486 SX", 703 [3] = "486 DX/2", 704 [4] = "486 SL", 705 [5] = "486 SX/2", 706 [7] = "486 DX/2-WB", 707 [8] = "486 DX/4", 708 [9] = "486 DX/4-WB" 709 } 710 }, 711 { .family = 5, .model_names = 712 { 713 [0] = "Pentium 60/66 A-step", 714 [1] = "Pentium 60/66", 715 [2] = "Pentium 75 - 200", 716 [3] = "OverDrive PODP5V83", 717 [4] = "Pentium MMX", 718 [7] = "Mobile Pentium 75 - 200", 719 [8] = "Mobile Pentium MMX", 720 [9] = "Quark SoC X1000", 721 } 722 }, 723 { .family = 6, .model_names = 724 { 725 [0] = "Pentium Pro A-step", 726 [1] = "Pentium Pro", 727 [3] = "Pentium II (Klamath)", 728 [4] = "Pentium II (Deschutes)", 729 [5] = "Pentium II (Deschutes)", 730 [6] = "Mobile Pentium II", 731 [7] = "Pentium III (Katmai)", 732 [8] = "Pentium III (Coppermine)", 733 [10] = "Pentium III (Cascades)", 734 [11] = "Pentium III (Tualatin)", 735 } 736 }, 737 { .family = 15, .model_names = 738 { 739 [0] = "Pentium 4 (Unknown)", 740 [1] = "Pentium 4 (Willamette)", 741 [2] = "Pentium 4 (Northwood)", 742 [4] = "Pentium 4 (Foster)", 743 [5] = "Pentium 4 (Foster)", 744 } 745 }, 746 }, 747 .legacy_cache_size = intel_size_cache, 748#endif 749 .c_detect_tlb = intel_detect_tlb, 750 .c_early_init = early_init_intel, 751 .c_init = init_intel, 752 .c_x86_vendor = X86_VENDOR_INTEL, 753}; 754 755cpu_dev_register(intel_cpu_dev); 756 757