mce.c revision 95022b8cf6ed7f3292b60c8e85fe59a12bfb1c9e
1/* 2 * Machine check handler. 3 * 4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. 5 * Rest from unknown author(s). 6 * 2004 Andi Kleen. Rewrote most of it. 7 * Copyright 2008 Intel Corporation 8 * Author: Andi Kleen 9 */ 10#include <linux/thread_info.h> 11#include <linux/capability.h> 12#include <linux/miscdevice.h> 13#include <linux/ratelimit.h> 14#include <linux/kallsyms.h> 15#include <linux/rcupdate.h> 16#include <linux/kobject.h> 17#include <linux/uaccess.h> 18#include <linux/kdebug.h> 19#include <linux/kernel.h> 20#include <linux/percpu.h> 21#include <linux/string.h> 22#include <linux/device.h> 23#include <linux/syscore_ops.h> 24#include <linux/delay.h> 25#include <linux/ctype.h> 26#include <linux/sched.h> 27#include <linux/sysfs.h> 28#include <linux/types.h> 29#include <linux/slab.h> 30#include <linux/init.h> 31#include <linux/kmod.h> 32#include <linux/poll.h> 33#include <linux/nmi.h> 34#include <linux/cpu.h> 35#include <linux/smp.h> 36#include <linux/fs.h> 37#include <linux/mm.h> 38#include <linux/debugfs.h> 39#include <linux/irq_work.h> 40#include <linux/export.h> 41 42#include <asm/processor.h> 43#include <asm/mce.h> 44#include <asm/msr.h> 45 46#include "mce-internal.h" 47 48static DEFINE_MUTEX(mce_chrdev_read_mutex); 49 50#define rcu_dereference_check_mce(p) \ 51 rcu_dereference_index_check((p), \ 52 rcu_read_lock_sched_held() || \ 53 lockdep_is_held(&mce_chrdev_read_mutex)) 54 55#define CREATE_TRACE_POINTS 56#include <trace/events/mce.h> 57 58int mce_disabled __read_mostly; 59 60#define MISC_MCELOG_MINOR 227 61 62#define SPINUNIT 100 /* 100ns */ 63 64atomic_t mce_entry; 65 66DEFINE_PER_CPU(unsigned, mce_exception_count); 67 68/* 69 * Tolerant levels: 70 * 0: always panic on uncorrected errors, log corrected errors 71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors 72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors 73 * 3: never panic or SIGBUS, log all errors (for testing only) 74 */ 75static int tolerant __read_mostly = 1; 76static int banks __read_mostly; 77static int rip_msr __read_mostly; 78static int mce_bootlog __read_mostly = -1; 79static int monarch_timeout __read_mostly = -1; 80static int mce_panic_timeout __read_mostly; 81static int mce_dont_log_ce __read_mostly; 82int mce_cmci_disabled __read_mostly; 83int mce_ignore_ce __read_mostly; 84int mce_ser __read_mostly; 85 86struct mce_bank *mce_banks __read_mostly; 87 88/* User mode helper program triggered by machine check event */ 89static unsigned long mce_need_notify; 90static char mce_helper[128]; 91static char *mce_helper_argv[2] = { mce_helper, NULL }; 92 93static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); 94 95static DEFINE_PER_CPU(struct mce, mces_seen); 96static int cpu_missing; 97 98/* MCA banks polled by the period polling timer for corrected events */ 99DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { 100 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL 101}; 102 103static DEFINE_PER_CPU(struct work_struct, mce_work); 104 105/* 106 * CPU/chipset specific EDAC code can register a notifier call here to print 107 * MCE errors in a human-readable form. 108 */ 109ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); 110 111/* Do initial initialization of a struct mce */ 112void mce_setup(struct mce *m) 113{ 114 memset(m, 0, sizeof(struct mce)); 115 m->cpu = m->extcpu = smp_processor_id(); 116 rdtscll(m->tsc); 117 /* We hope get_seconds stays lockless */ 118 m->time = get_seconds(); 119 m->cpuvendor = boot_cpu_data.x86_vendor; 120 m->cpuid = cpuid_eax(1); 121 m->socketid = cpu_data(m->extcpu).phys_proc_id; 122 m->apicid = cpu_data(m->extcpu).initial_apicid; 123 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); 124} 125 126DEFINE_PER_CPU(struct mce, injectm); 127EXPORT_PER_CPU_SYMBOL_GPL(injectm); 128 129/* 130 * Lockless MCE logging infrastructure. 131 * This avoids deadlocks on printk locks without having to break locks. Also 132 * separate MCEs from kernel messages to avoid bogus bug reports. 133 */ 134 135static struct mce_log mcelog = { 136 .signature = MCE_LOG_SIGNATURE, 137 .len = MCE_LOG_LEN, 138 .recordlen = sizeof(struct mce), 139}; 140 141void mce_log(struct mce *mce) 142{ 143 unsigned next, entry; 144 int ret = 0; 145 146 /* Emit the trace record: */ 147 trace_mce_record(mce); 148 149 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); 150 if (ret == NOTIFY_STOP) 151 return; 152 153 mce->finished = 0; 154 wmb(); 155 for (;;) { 156 entry = rcu_dereference_check_mce(mcelog.next); 157 for (;;) { 158 159 /* 160 * When the buffer fills up discard new entries. 161 * Assume that the earlier errors are the more 162 * interesting ones: 163 */ 164 if (entry >= MCE_LOG_LEN) { 165 set_bit(MCE_OVERFLOW, 166 (unsigned long *)&mcelog.flags); 167 return; 168 } 169 /* Old left over entry. Skip: */ 170 if (mcelog.entry[entry].finished) { 171 entry++; 172 continue; 173 } 174 break; 175 } 176 smp_rmb(); 177 next = entry + 1; 178 if (cmpxchg(&mcelog.next, entry, next) == entry) 179 break; 180 } 181 memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); 182 wmb(); 183 mcelog.entry[entry].finished = 1; 184 wmb(); 185 186 mce->finished = 1; 187 set_bit(0, &mce_need_notify); 188} 189 190static void drain_mcelog_buffer(void) 191{ 192 unsigned int next, i, prev = 0; 193 194 next = ACCESS_ONCE(mcelog.next); 195 196 do { 197 struct mce *m; 198 199 /* drain what was logged during boot */ 200 for (i = prev; i < next; i++) { 201 unsigned long start = jiffies; 202 unsigned retries = 1; 203 204 m = &mcelog.entry[i]; 205 206 while (!m->finished) { 207 if (time_after_eq(jiffies, start + 2*retries)) 208 retries++; 209 210 cpu_relax(); 211 212 if (!m->finished && retries >= 4) { 213 pr_err("MCE: skipping error being logged currently!\n"); 214 break; 215 } 216 } 217 smp_rmb(); 218 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); 219 } 220 221 memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); 222 prev = next; 223 next = cmpxchg(&mcelog.next, prev, 0); 224 } while (next != prev); 225} 226 227 228void mce_register_decode_chain(struct notifier_block *nb) 229{ 230 atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); 231 drain_mcelog_buffer(); 232} 233EXPORT_SYMBOL_GPL(mce_register_decode_chain); 234 235void mce_unregister_decode_chain(struct notifier_block *nb) 236{ 237 atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); 238} 239EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); 240 241static void print_mce(struct mce *m) 242{ 243 int ret = 0; 244 245 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", 246 m->extcpu, m->mcgstatus, m->bank, m->status); 247 248 if (m->ip) { 249 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", 250 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", 251 m->cs, m->ip); 252 253 if (m->cs == __KERNEL_CS) 254 print_symbol("{%s}", m->ip); 255 pr_cont("\n"); 256 } 257 258 pr_emerg(HW_ERR "TSC %llx ", m->tsc); 259 if (m->addr) 260 pr_cont("ADDR %llx ", m->addr); 261 if (m->misc) 262 pr_cont("MISC %llx ", m->misc); 263 264 pr_cont("\n"); 265 /* 266 * Note this output is parsed by external tools and old fields 267 * should not be changed. 268 */ 269 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", 270 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, 271 cpu_data(m->extcpu).microcode); 272 273 /* 274 * Print out human-readable details about the MCE error, 275 * (if the CPU has an implementation for that) 276 */ 277 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); 278 if (ret == NOTIFY_STOP) 279 return; 280 281 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); 282} 283 284#define PANIC_TIMEOUT 5 /* 5 seconds */ 285 286static atomic_t mce_paniced; 287 288static int fake_panic; 289static atomic_t mce_fake_paniced; 290 291/* Panic in progress. Enable interrupts and wait for final IPI */ 292static void wait_for_panic(void) 293{ 294 long timeout = PANIC_TIMEOUT*USEC_PER_SEC; 295 296 preempt_disable(); 297 local_irq_enable(); 298 while (timeout-- > 0) 299 udelay(1); 300 if (panic_timeout == 0) 301 panic_timeout = mce_panic_timeout; 302 panic("Panicing machine check CPU died"); 303} 304 305static void mce_panic(char *msg, struct mce *final, char *exp) 306{ 307 int i, apei_err = 0; 308 309 if (!fake_panic) { 310 /* 311 * Make sure only one CPU runs in machine check panic 312 */ 313 if (atomic_inc_return(&mce_paniced) > 1) 314 wait_for_panic(); 315 barrier(); 316 317 bust_spinlocks(1); 318 console_verbose(); 319 } else { 320 /* Don't log too much for fake panic */ 321 if (atomic_inc_return(&mce_fake_paniced) > 1) 322 return; 323 } 324 /* First print corrected ones that are still unlogged */ 325 for (i = 0; i < MCE_LOG_LEN; i++) { 326 struct mce *m = &mcelog.entry[i]; 327 if (!(m->status & MCI_STATUS_VAL)) 328 continue; 329 if (!(m->status & MCI_STATUS_UC)) { 330 print_mce(m); 331 if (!apei_err) 332 apei_err = apei_write_mce(m); 333 } 334 } 335 /* Now print uncorrected but with the final one last */ 336 for (i = 0; i < MCE_LOG_LEN; i++) { 337 struct mce *m = &mcelog.entry[i]; 338 if (!(m->status & MCI_STATUS_VAL)) 339 continue; 340 if (!(m->status & MCI_STATUS_UC)) 341 continue; 342 if (!final || memcmp(m, final, sizeof(struct mce))) { 343 print_mce(m); 344 if (!apei_err) 345 apei_err = apei_write_mce(m); 346 } 347 } 348 if (final) { 349 print_mce(final); 350 if (!apei_err) 351 apei_err = apei_write_mce(final); 352 } 353 if (cpu_missing) 354 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); 355 if (exp) 356 pr_emerg(HW_ERR "Machine check: %s\n", exp); 357 if (!fake_panic) { 358 if (panic_timeout == 0) 359 panic_timeout = mce_panic_timeout; 360 panic(msg); 361 } else 362 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); 363} 364 365/* Support code for software error injection */ 366 367static int msr_to_offset(u32 msr) 368{ 369 unsigned bank = __this_cpu_read(injectm.bank); 370 371 if (msr == rip_msr) 372 return offsetof(struct mce, ip); 373 if (msr == MSR_IA32_MCx_STATUS(bank)) 374 return offsetof(struct mce, status); 375 if (msr == MSR_IA32_MCx_ADDR(bank)) 376 return offsetof(struct mce, addr); 377 if (msr == MSR_IA32_MCx_MISC(bank)) 378 return offsetof(struct mce, misc); 379 if (msr == MSR_IA32_MCG_STATUS) 380 return offsetof(struct mce, mcgstatus); 381 return -1; 382} 383 384/* MSR access wrappers used for error injection */ 385static u64 mce_rdmsrl(u32 msr) 386{ 387 u64 v; 388 389 if (__this_cpu_read(injectm.finished)) { 390 int offset = msr_to_offset(msr); 391 392 if (offset < 0) 393 return 0; 394 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); 395 } 396 397 if (rdmsrl_safe(msr, &v)) { 398 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); 399 /* 400 * Return zero in case the access faulted. This should 401 * not happen normally but can happen if the CPU does 402 * something weird, or if the code is buggy. 403 */ 404 v = 0; 405 } 406 407 return v; 408} 409 410static void mce_wrmsrl(u32 msr, u64 v) 411{ 412 if (__this_cpu_read(injectm.finished)) { 413 int offset = msr_to_offset(msr); 414 415 if (offset >= 0) 416 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; 417 return; 418 } 419 wrmsrl(msr, v); 420} 421 422/* 423 * Collect all global (w.r.t. this processor) status about this machine 424 * check into our "mce" struct so that we can use it later to assess 425 * the severity of the problem as we read per-bank specific details. 426 */ 427static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) 428{ 429 mce_setup(m); 430 431 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); 432 if (regs) { 433 /* 434 * Get the address of the instruction at the time of 435 * the machine check error. 436 */ 437 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { 438 m->ip = regs->ip; 439 m->cs = regs->cs; 440 } 441 /* Use accurate RIP reporting if available. */ 442 if (rip_msr) 443 m->ip = mce_rdmsrl(rip_msr); 444 } 445} 446 447/* 448 * Simple lockless ring to communicate PFNs from the exception handler with the 449 * process context work function. This is vastly simplified because there's 450 * only a single reader and a single writer. 451 */ 452#define MCE_RING_SIZE 16 /* we use one entry less */ 453 454struct mce_ring { 455 unsigned short start; 456 unsigned short end; 457 unsigned long ring[MCE_RING_SIZE]; 458}; 459static DEFINE_PER_CPU(struct mce_ring, mce_ring); 460 461/* Runs with CPU affinity in workqueue */ 462static int mce_ring_empty(void) 463{ 464 struct mce_ring *r = &__get_cpu_var(mce_ring); 465 466 return r->start == r->end; 467} 468 469static int mce_ring_get(unsigned long *pfn) 470{ 471 struct mce_ring *r; 472 int ret = 0; 473 474 *pfn = 0; 475 get_cpu(); 476 r = &__get_cpu_var(mce_ring); 477 if (r->start == r->end) 478 goto out; 479 *pfn = r->ring[r->start]; 480 r->start = (r->start + 1) % MCE_RING_SIZE; 481 ret = 1; 482out: 483 put_cpu(); 484 return ret; 485} 486 487/* Always runs in MCE context with preempt off */ 488static int mce_ring_add(unsigned long pfn) 489{ 490 struct mce_ring *r = &__get_cpu_var(mce_ring); 491 unsigned next; 492 493 next = (r->end + 1) % MCE_RING_SIZE; 494 if (next == r->start) 495 return -1; 496 r->ring[r->end] = pfn; 497 wmb(); 498 r->end = next; 499 return 0; 500} 501 502int mce_available(struct cpuinfo_x86 *c) 503{ 504 if (mce_disabled) 505 return 0; 506 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); 507} 508 509static void mce_schedule_work(void) 510{ 511 if (!mce_ring_empty()) { 512 struct work_struct *work = &__get_cpu_var(mce_work); 513 if (!work_pending(work)) 514 schedule_work(work); 515 } 516} 517 518DEFINE_PER_CPU(struct irq_work, mce_irq_work); 519 520static void mce_irq_work_cb(struct irq_work *entry) 521{ 522 mce_notify_irq(); 523 mce_schedule_work(); 524} 525 526static void mce_report_event(struct pt_regs *regs) 527{ 528 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { 529 mce_notify_irq(); 530 /* 531 * Triggering the work queue here is just an insurance 532 * policy in case the syscall exit notify handler 533 * doesn't run soon enough or ends up running on the 534 * wrong CPU (can happen when audit sleeps) 535 */ 536 mce_schedule_work(); 537 return; 538 } 539 540 irq_work_queue(&__get_cpu_var(mce_irq_work)); 541} 542 543/* 544 * Read ADDR and MISC registers. 545 */ 546static void mce_read_aux(struct mce *m, int i) 547{ 548 if (m->status & MCI_STATUS_MISCV) 549 m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); 550 if (m->status & MCI_STATUS_ADDRV) { 551 m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); 552 553 /* 554 * Mask the reported address by the reported granularity. 555 */ 556 if (mce_ser && (m->status & MCI_STATUS_MISCV)) { 557 u8 shift = MCI_MISC_ADDR_LSB(m->misc); 558 m->addr >>= shift; 559 m->addr <<= shift; 560 } 561 } 562} 563 564DEFINE_PER_CPU(unsigned, mce_poll_count); 565 566/* 567 * Poll for corrected events or events that happened before reset. 568 * Those are just logged through /dev/mcelog. 569 * 570 * This is executed in standard interrupt context. 571 * 572 * Note: spec recommends to panic for fatal unsignalled 573 * errors here. However this would be quite problematic -- 574 * we would need to reimplement the Monarch handling and 575 * it would mess up the exclusion between exception handler 576 * and poll hander -- * so we skip this for now. 577 * These cases should not happen anyways, or only when the CPU 578 * is already totally * confused. In this case it's likely it will 579 * not fully execute the machine check handler either. 580 */ 581void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) 582{ 583 struct mce m; 584 int i; 585 586 percpu_inc(mce_poll_count); 587 588 mce_gather_info(&m, NULL); 589 590 for (i = 0; i < banks; i++) { 591 if (!mce_banks[i].ctl || !test_bit(i, *b)) 592 continue; 593 594 m.misc = 0; 595 m.addr = 0; 596 m.bank = i; 597 m.tsc = 0; 598 599 barrier(); 600 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); 601 if (!(m.status & MCI_STATUS_VAL)) 602 continue; 603 604 /* 605 * Uncorrected or signalled events are handled by the exception 606 * handler when it is enabled, so don't process those here. 607 * 608 * TBD do the same check for MCI_STATUS_EN here? 609 */ 610 if (!(flags & MCP_UC) && 611 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) 612 continue; 613 614 mce_read_aux(&m, i); 615 616 if (!(flags & MCP_TIMESTAMP)) 617 m.tsc = 0; 618 /* 619 * Don't get the IP here because it's unlikely to 620 * have anything to do with the actual error location. 621 */ 622 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) 623 mce_log(&m); 624 625 /* 626 * Clear state for this bank. 627 */ 628 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); 629 } 630 631 /* 632 * Don't clear MCG_STATUS here because it's only defined for 633 * exceptions. 634 */ 635 636 sync_core(); 637} 638EXPORT_SYMBOL_GPL(machine_check_poll); 639 640/* 641 * Do a quick check if any of the events requires a panic. 642 * This decides if we keep the events around or clear them. 643 */ 644static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp) 645{ 646 int i, ret = 0; 647 648 for (i = 0; i < banks; i++) { 649 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); 650 if (m->status & MCI_STATUS_VAL) 651 __set_bit(i, validp); 652 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) 653 ret = 1; 654 } 655 return ret; 656} 657 658/* 659 * Variable to establish order between CPUs while scanning. 660 * Each CPU spins initially until executing is equal its number. 661 */ 662static atomic_t mce_executing; 663 664/* 665 * Defines order of CPUs on entry. First CPU becomes Monarch. 666 */ 667static atomic_t mce_callin; 668 669/* 670 * Check if a timeout waiting for other CPUs happened. 671 */ 672static int mce_timed_out(u64 *t) 673{ 674 /* 675 * The others already did panic for some reason. 676 * Bail out like in a timeout. 677 * rmb() to tell the compiler that system_state 678 * might have been modified by someone else. 679 */ 680 rmb(); 681 if (atomic_read(&mce_paniced)) 682 wait_for_panic(); 683 if (!monarch_timeout) 684 goto out; 685 if ((s64)*t < SPINUNIT) { 686 /* CHECKME: Make panic default for 1 too? */ 687 if (tolerant < 1) 688 mce_panic("Timeout synchronizing machine check over CPUs", 689 NULL, NULL); 690 cpu_missing = 1; 691 return 1; 692 } 693 *t -= SPINUNIT; 694out: 695 touch_nmi_watchdog(); 696 return 0; 697} 698 699/* 700 * The Monarch's reign. The Monarch is the CPU who entered 701 * the machine check handler first. It waits for the others to 702 * raise the exception too and then grades them. When any 703 * error is fatal panic. Only then let the others continue. 704 * 705 * The other CPUs entering the MCE handler will be controlled by the 706 * Monarch. They are called Subjects. 707 * 708 * This way we prevent any potential data corruption in a unrecoverable case 709 * and also makes sure always all CPU's errors are examined. 710 * 711 * Also this detects the case of a machine check event coming from outer 712 * space (not detected by any CPUs) In this case some external agent wants 713 * us to shut down, so panic too. 714 * 715 * The other CPUs might still decide to panic if the handler happens 716 * in a unrecoverable place, but in this case the system is in a semi-stable 717 * state and won't corrupt anything by itself. It's ok to let the others 718 * continue for a bit first. 719 * 720 * All the spin loops have timeouts; when a timeout happens a CPU 721 * typically elects itself to be Monarch. 722 */ 723static void mce_reign(void) 724{ 725 int cpu; 726 struct mce *m = NULL; 727 int global_worst = 0; 728 char *msg = NULL; 729 char *nmsg = NULL; 730 731 /* 732 * This CPU is the Monarch and the other CPUs have run 733 * through their handlers. 734 * Grade the severity of the errors of all the CPUs. 735 */ 736 for_each_possible_cpu(cpu) { 737 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, 738 &nmsg); 739 if (severity > global_worst) { 740 msg = nmsg; 741 global_worst = severity; 742 m = &per_cpu(mces_seen, cpu); 743 } 744 } 745 746 /* 747 * Cannot recover? Panic here then. 748 * This dumps all the mces in the log buffer and stops the 749 * other CPUs. 750 */ 751 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) 752 mce_panic("Fatal Machine check", m, msg); 753 754 /* 755 * For UC somewhere we let the CPU who detects it handle it. 756 * Also must let continue the others, otherwise the handling 757 * CPU could deadlock on a lock. 758 */ 759 760 /* 761 * No machine check event found. Must be some external 762 * source or one CPU is hung. Panic. 763 */ 764 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) 765 mce_panic("Machine check from unknown source", NULL, NULL); 766 767 /* 768 * Now clear all the mces_seen so that they don't reappear on 769 * the next mce. 770 */ 771 for_each_possible_cpu(cpu) 772 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); 773} 774 775static atomic_t global_nwo; 776 777/* 778 * Start of Monarch synchronization. This waits until all CPUs have 779 * entered the exception handler and then determines if any of them 780 * saw a fatal event that requires panic. Then it executes them 781 * in the entry order. 782 * TBD double check parallel CPU hotunplug 783 */ 784static int mce_start(int *no_way_out) 785{ 786 int order; 787 int cpus = num_online_cpus(); 788 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; 789 790 if (!timeout) 791 return -1; 792 793 atomic_add(*no_way_out, &global_nwo); 794 /* 795 * global_nwo should be updated before mce_callin 796 */ 797 smp_wmb(); 798 order = atomic_inc_return(&mce_callin); 799 800 /* 801 * Wait for everyone. 802 */ 803 while (atomic_read(&mce_callin) != cpus) { 804 if (mce_timed_out(&timeout)) { 805 atomic_set(&global_nwo, 0); 806 return -1; 807 } 808 ndelay(SPINUNIT); 809 } 810 811 /* 812 * mce_callin should be read before global_nwo 813 */ 814 smp_rmb(); 815 816 if (order == 1) { 817 /* 818 * Monarch: Starts executing now, the others wait. 819 */ 820 atomic_set(&mce_executing, 1); 821 } else { 822 /* 823 * Subject: Now start the scanning loop one by one in 824 * the original callin order. 825 * This way when there are any shared banks it will be 826 * only seen by one CPU before cleared, avoiding duplicates. 827 */ 828 while (atomic_read(&mce_executing) < order) { 829 if (mce_timed_out(&timeout)) { 830 atomic_set(&global_nwo, 0); 831 return -1; 832 } 833 ndelay(SPINUNIT); 834 } 835 } 836 837 /* 838 * Cache the global no_way_out state. 839 */ 840 *no_way_out = atomic_read(&global_nwo); 841 842 return order; 843} 844 845/* 846 * Synchronize between CPUs after main scanning loop. 847 * This invokes the bulk of the Monarch processing. 848 */ 849static int mce_end(int order) 850{ 851 int ret = -1; 852 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; 853 854 if (!timeout) 855 goto reset; 856 if (order < 0) 857 goto reset; 858 859 /* 860 * Allow others to run. 861 */ 862 atomic_inc(&mce_executing); 863 864 if (order == 1) { 865 /* CHECKME: Can this race with a parallel hotplug? */ 866 int cpus = num_online_cpus(); 867 868 /* 869 * Monarch: Wait for everyone to go through their scanning 870 * loops. 871 */ 872 while (atomic_read(&mce_executing) <= cpus) { 873 if (mce_timed_out(&timeout)) 874 goto reset; 875 ndelay(SPINUNIT); 876 } 877 878 mce_reign(); 879 barrier(); 880 ret = 0; 881 } else { 882 /* 883 * Subject: Wait for Monarch to finish. 884 */ 885 while (atomic_read(&mce_executing) != 0) { 886 if (mce_timed_out(&timeout)) 887 goto reset; 888 ndelay(SPINUNIT); 889 } 890 891 /* 892 * Don't reset anything. That's done by the Monarch. 893 */ 894 return 0; 895 } 896 897 /* 898 * Reset all global state. 899 */ 900reset: 901 atomic_set(&global_nwo, 0); 902 atomic_set(&mce_callin, 0); 903 barrier(); 904 905 /* 906 * Let others run again. 907 */ 908 atomic_set(&mce_executing, 0); 909 return ret; 910} 911 912/* 913 * Check if the address reported by the CPU is in a format we can parse. 914 * It would be possible to add code for most other cases, but all would 915 * be somewhat complicated (e.g. segment offset would require an instruction 916 * parser). So only support physical addresses up to page granuality for now. 917 */ 918static int mce_usable_address(struct mce *m) 919{ 920 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) 921 return 0; 922 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) 923 return 0; 924 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) 925 return 0; 926 return 1; 927} 928 929static void mce_clear_state(unsigned long *toclear) 930{ 931 int i; 932 933 for (i = 0; i < banks; i++) { 934 if (test_bit(i, toclear)) 935 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); 936 } 937} 938 939/* 940 * Need to save faulting physical address associated with a process 941 * in the machine check handler some place where we can grab it back 942 * later in mce_notify_process() 943 */ 944#define MCE_INFO_MAX 16 945 946struct mce_info { 947 atomic_t inuse; 948 struct task_struct *t; 949 __u64 paddr; 950} mce_info[MCE_INFO_MAX]; 951 952static void mce_save_info(__u64 addr) 953{ 954 struct mce_info *mi; 955 956 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { 957 if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { 958 mi->t = current; 959 mi->paddr = addr; 960 return; 961 } 962 } 963 964 mce_panic("Too many concurrent recoverable errors", NULL, NULL); 965} 966 967static struct mce_info *mce_find_info(void) 968{ 969 struct mce_info *mi; 970 971 for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) 972 if (atomic_read(&mi->inuse) && mi->t == current) 973 return mi; 974 return NULL; 975} 976 977static void mce_clear_info(struct mce_info *mi) 978{ 979 atomic_set(&mi->inuse, 0); 980} 981 982/* 983 * The actual machine check handler. This only handles real 984 * exceptions when something got corrupted coming in through int 18. 985 * 986 * This is executed in NMI context not subject to normal locking rules. This 987 * implies that most kernel services cannot be safely used. Don't even 988 * think about putting a printk in there! 989 * 990 * On Intel systems this is entered on all CPUs in parallel through 991 * MCE broadcast. However some CPUs might be broken beyond repair, 992 * so be always careful when synchronizing with others. 993 */ 994void do_machine_check(struct pt_regs *regs, long error_code) 995{ 996 struct mce m, *final; 997 int i; 998 int worst = 0; 999 int severity; 1000 /* 1001 * Establish sequential order between the CPUs entering the machine 1002 * check handler. 1003 */ 1004 int order; 1005 /* 1006 * If no_way_out gets set, there is no safe way to recover from this 1007 * MCE. If tolerant is cranked up, we'll try anyway. 1008 */ 1009 int no_way_out = 0; 1010 /* 1011 * If kill_it gets set, there might be a way to recover from this 1012 * error. 1013 */ 1014 int kill_it = 0; 1015 DECLARE_BITMAP(toclear, MAX_NR_BANKS); 1016 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); 1017 char *msg = "Unknown"; 1018 1019 atomic_inc(&mce_entry); 1020 1021 percpu_inc(mce_exception_count); 1022 1023 if (!banks) 1024 goto out; 1025 1026 mce_gather_info(&m, regs); 1027 1028 final = &__get_cpu_var(mces_seen); 1029 *final = m; 1030 1031 memset(valid_banks, 0, sizeof(valid_banks)); 1032 no_way_out = mce_no_way_out(&m, &msg, valid_banks); 1033 1034 barrier(); 1035 1036 /* 1037 * When no restart IP might need to kill or panic. 1038 * Assume the worst for now, but if we find the 1039 * severity is MCE_AR_SEVERITY we have other options. 1040 */ 1041 if (!(m.mcgstatus & MCG_STATUS_RIPV)) 1042 kill_it = 1; 1043 1044 /* 1045 * Go through all the banks in exclusion of the other CPUs. 1046 * This way we don't report duplicated events on shared banks 1047 * because the first one to see it will clear it. 1048 */ 1049 order = mce_start(&no_way_out); 1050 for (i = 0; i < banks; i++) { 1051 __clear_bit(i, toclear); 1052 if (!test_bit(i, valid_banks)) 1053 continue; 1054 if (!mce_banks[i].ctl) 1055 continue; 1056 1057 m.misc = 0; 1058 m.addr = 0; 1059 m.bank = i; 1060 1061 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); 1062 if ((m.status & MCI_STATUS_VAL) == 0) 1063 continue; 1064 1065 /* 1066 * Non uncorrected or non signaled errors are handled by 1067 * machine_check_poll. Leave them alone, unless this panics. 1068 */ 1069 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && 1070 !no_way_out) 1071 continue; 1072 1073 /* 1074 * Set taint even when machine check was not enabled. 1075 */ 1076 add_taint(TAINT_MACHINE_CHECK); 1077 1078 severity = mce_severity(&m, tolerant, NULL); 1079 1080 /* 1081 * When machine check was for corrected handler don't touch, 1082 * unless we're panicing. 1083 */ 1084 if (severity == MCE_KEEP_SEVERITY && !no_way_out) 1085 continue; 1086 __set_bit(i, toclear); 1087 if (severity == MCE_NO_SEVERITY) { 1088 /* 1089 * Machine check event was not enabled. Clear, but 1090 * ignore. 1091 */ 1092 continue; 1093 } 1094 1095 mce_read_aux(&m, i); 1096 1097 /* 1098 * Action optional error. Queue address for later processing. 1099 * When the ring overflows we just ignore the AO error. 1100 * RED-PEN add some logging mechanism when 1101 * usable_address or mce_add_ring fails. 1102 * RED-PEN don't ignore overflow for tolerant == 0 1103 */ 1104 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) 1105 mce_ring_add(m.addr >> PAGE_SHIFT); 1106 1107 mce_log(&m); 1108 1109 if (severity > worst) { 1110 *final = m; 1111 worst = severity; 1112 } 1113 } 1114 1115 /* mce_clear_state will clear *final, save locally for use later */ 1116 m = *final; 1117 1118 if (!no_way_out) 1119 mce_clear_state(toclear); 1120 1121 /* 1122 * Do most of the synchronization with other CPUs. 1123 * When there's any problem use only local no_way_out state. 1124 */ 1125 if (mce_end(order) < 0) 1126 no_way_out = worst >= MCE_PANIC_SEVERITY; 1127 1128 /* 1129 * At insane "tolerant" levels we take no action. Otherwise 1130 * we only die if we have no other choice. For less serious 1131 * issues we try to recover, or limit damage to the current 1132 * process. 1133 */ 1134 if (tolerant < 3) { 1135 if (no_way_out) 1136 mce_panic("Fatal machine check on current CPU", &m, msg); 1137 if (worst == MCE_AR_SEVERITY) { 1138 /* schedule action before return to userland */ 1139 mce_save_info(m.addr); 1140 set_thread_flag(TIF_MCE_NOTIFY); 1141 } else if (kill_it) { 1142 force_sig(SIGBUS, current); 1143 } 1144 } 1145 1146 if (worst > 0) 1147 mce_report_event(regs); 1148 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); 1149out: 1150 atomic_dec(&mce_entry); 1151 sync_core(); 1152} 1153EXPORT_SYMBOL_GPL(do_machine_check); 1154 1155#ifndef CONFIG_MEMORY_FAILURE 1156int memory_failure(unsigned long pfn, int vector, int flags) 1157{ 1158 /* mce_severity() should not hand us an ACTION_REQUIRED error */ 1159 BUG_ON(flags & MF_ACTION_REQUIRED); 1160 printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n" 1161 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn); 1162 1163 return 0; 1164} 1165#endif 1166 1167/* 1168 * Called in process context that interrupted by MCE and marked with 1169 * TIF_MCE_NOTIFY, just before returning to erroneous userland. 1170 * This code is allowed to sleep. 1171 * Attempt possible recovery such as calling the high level VM handler to 1172 * process any corrupted pages, and kill/signal current process if required. 1173 * Action required errors are handled here. 1174 */ 1175void mce_notify_process(void) 1176{ 1177 unsigned long pfn; 1178 struct mce_info *mi = mce_find_info(); 1179 1180 if (!mi) 1181 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); 1182 pfn = mi->paddr >> PAGE_SHIFT; 1183 1184 clear_thread_flag(TIF_MCE_NOTIFY); 1185 1186 pr_err("Uncorrected hardware memory error in user-access at %llx", 1187 mi->paddr); 1188 if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0) { 1189 pr_err("Memory error not recovered"); 1190 force_sig(SIGBUS, current); 1191 } 1192 mce_clear_info(mi); 1193} 1194 1195/* 1196 * Action optional processing happens here (picking up 1197 * from the list of faulting pages that do_machine_check() 1198 * placed into the "ring"). 1199 */ 1200static void mce_process_work(struct work_struct *dummy) 1201{ 1202 unsigned long pfn; 1203 1204 while (mce_ring_get(&pfn)) 1205 memory_failure(pfn, MCE_VECTOR, 0); 1206} 1207 1208#ifdef CONFIG_X86_MCE_INTEL 1209/*** 1210 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog 1211 * @cpu: The CPU on which the event occurred. 1212 * @status: Event status information 1213 * 1214 * This function should be called by the thermal interrupt after the 1215 * event has been processed and the decision was made to log the event 1216 * further. 1217 * 1218 * The status parameter will be saved to the 'status' field of 'struct mce' 1219 * and historically has been the register value of the 1220 * MSR_IA32_THERMAL_STATUS (Intel) msr. 1221 */ 1222void mce_log_therm_throt_event(__u64 status) 1223{ 1224 struct mce m; 1225 1226 mce_setup(&m); 1227 m.bank = MCE_THERMAL_BANK; 1228 m.status = status; 1229 mce_log(&m); 1230} 1231#endif /* CONFIG_X86_MCE_INTEL */ 1232 1233/* 1234 * Periodic polling timer for "silent" machine check errors. If the 1235 * poller finds an MCE, poll 2x faster. When the poller finds no more 1236 * errors, poll 2x slower (up to check_interval seconds). 1237 */ 1238static int check_interval = 5 * 60; /* 5 minutes */ 1239 1240static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ 1241static DEFINE_PER_CPU(struct timer_list, mce_timer); 1242 1243static void mce_start_timer(unsigned long data) 1244{ 1245 struct timer_list *t = &per_cpu(mce_timer, data); 1246 int *n; 1247 1248 WARN_ON(smp_processor_id() != data); 1249 1250 if (mce_available(__this_cpu_ptr(&cpu_info))) { 1251 machine_check_poll(MCP_TIMESTAMP, 1252 &__get_cpu_var(mce_poll_banks)); 1253 } 1254 1255 /* 1256 * Alert userspace if needed. If we logged an MCE, reduce the 1257 * polling interval, otherwise increase the polling interval. 1258 */ 1259 n = &__get_cpu_var(mce_next_interval); 1260 if (mce_notify_irq()) 1261 *n = max(*n/2, HZ/100); 1262 else 1263 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); 1264 1265 t->expires = jiffies + *n; 1266 add_timer_on(t, smp_processor_id()); 1267} 1268 1269/* Must not be called in IRQ context where del_timer_sync() can deadlock */ 1270static void mce_timer_delete_all(void) 1271{ 1272 int cpu; 1273 1274 for_each_online_cpu(cpu) 1275 del_timer_sync(&per_cpu(mce_timer, cpu)); 1276} 1277 1278static void mce_do_trigger(struct work_struct *work) 1279{ 1280 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); 1281} 1282 1283static DECLARE_WORK(mce_trigger_work, mce_do_trigger); 1284 1285/* 1286 * Notify the user(s) about new machine check events. 1287 * Can be called from interrupt context, but not from machine check/NMI 1288 * context. 1289 */ 1290int mce_notify_irq(void) 1291{ 1292 /* Not more than two messages every minute */ 1293 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); 1294 1295 if (test_and_clear_bit(0, &mce_need_notify)) { 1296 /* wake processes polling /dev/mcelog */ 1297 wake_up_interruptible(&mce_chrdev_wait); 1298 1299 /* 1300 * There is no risk of missing notifications because 1301 * work_pending is always cleared before the function is 1302 * executed. 1303 */ 1304 if (mce_helper[0] && !work_pending(&mce_trigger_work)) 1305 schedule_work(&mce_trigger_work); 1306 1307 if (__ratelimit(&ratelimit)) 1308 pr_info(HW_ERR "Machine check events logged\n"); 1309 1310 return 1; 1311 } 1312 return 0; 1313} 1314EXPORT_SYMBOL_GPL(mce_notify_irq); 1315 1316static int __cpuinit __mcheck_cpu_mce_banks_init(void) 1317{ 1318 int i; 1319 1320 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); 1321 if (!mce_banks) 1322 return -ENOMEM; 1323 for (i = 0; i < banks; i++) { 1324 struct mce_bank *b = &mce_banks[i]; 1325 1326 b->ctl = -1ULL; 1327 b->init = 1; 1328 } 1329 return 0; 1330} 1331 1332/* 1333 * Initialize Machine Checks for a CPU. 1334 */ 1335static int __cpuinit __mcheck_cpu_cap_init(void) 1336{ 1337 unsigned b; 1338 u64 cap; 1339 1340 rdmsrl(MSR_IA32_MCG_CAP, cap); 1341 1342 b = cap & MCG_BANKCNT_MASK; 1343 if (!banks) 1344 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); 1345 1346 if (b > MAX_NR_BANKS) { 1347 printk(KERN_WARNING 1348 "MCE: Using only %u machine check banks out of %u\n", 1349 MAX_NR_BANKS, b); 1350 b = MAX_NR_BANKS; 1351 } 1352 1353 /* Don't support asymmetric configurations today */ 1354 WARN_ON(banks != 0 && b != banks); 1355 banks = b; 1356 if (!mce_banks) { 1357 int err = __mcheck_cpu_mce_banks_init(); 1358 1359 if (err) 1360 return err; 1361 } 1362 1363 /* Use accurate RIP reporting if available. */ 1364 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) 1365 rip_msr = MSR_IA32_MCG_EIP; 1366 1367 if (cap & MCG_SER_P) 1368 mce_ser = 1; 1369 1370 return 0; 1371} 1372 1373static void __mcheck_cpu_init_generic(void) 1374{ 1375 mce_banks_t all_banks; 1376 u64 cap; 1377 int i; 1378 1379 /* 1380 * Log the machine checks left over from the previous reset. 1381 */ 1382 bitmap_fill(all_banks, MAX_NR_BANKS); 1383 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); 1384 1385 set_in_cr4(X86_CR4_MCE); 1386 1387 rdmsrl(MSR_IA32_MCG_CAP, cap); 1388 if (cap & MCG_CTL_P) 1389 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); 1390 1391 for (i = 0; i < banks; i++) { 1392 struct mce_bank *b = &mce_banks[i]; 1393 1394 if (!b->init) 1395 continue; 1396 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); 1397 wrmsrl(MSR_IA32_MCx_STATUS(i), 0); 1398 } 1399} 1400 1401/* Add per CPU specific workarounds here */ 1402static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) 1403{ 1404 if (c->x86_vendor == X86_VENDOR_UNKNOWN) { 1405 pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); 1406 return -EOPNOTSUPP; 1407 } 1408 1409 /* This should be disabled by the BIOS, but isn't always */ 1410 if (c->x86_vendor == X86_VENDOR_AMD) { 1411 if (c->x86 == 15 && banks > 4) { 1412 /* 1413 * disable GART TBL walk error reporting, which 1414 * trips off incorrectly with the IOMMU & 3ware 1415 * & Cerberus: 1416 */ 1417 clear_bit(10, (unsigned long *)&mce_banks[4].ctl); 1418 } 1419 if (c->x86 <= 17 && mce_bootlog < 0) { 1420 /* 1421 * Lots of broken BIOS around that don't clear them 1422 * by default and leave crap in there. Don't log: 1423 */ 1424 mce_bootlog = 0; 1425 } 1426 /* 1427 * Various K7s with broken bank 0 around. Always disable 1428 * by default. 1429 */ 1430 if (c->x86 == 6 && banks > 0) 1431 mce_banks[0].ctl = 0; 1432 } 1433 1434 if (c->x86_vendor == X86_VENDOR_INTEL) { 1435 /* 1436 * SDM documents that on family 6 bank 0 should not be written 1437 * because it aliases to another special BIOS controlled 1438 * register. 1439 * But it's not aliased anymore on model 0x1a+ 1440 * Don't ignore bank 0 completely because there could be a 1441 * valid event later, merely don't write CTL0. 1442 */ 1443 1444 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) 1445 mce_banks[0].init = 0; 1446 1447 /* 1448 * All newer Intel systems support MCE broadcasting. Enable 1449 * synchronization with a one second timeout. 1450 */ 1451 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && 1452 monarch_timeout < 0) 1453 monarch_timeout = USEC_PER_SEC; 1454 1455 /* 1456 * There are also broken BIOSes on some Pentium M and 1457 * earlier systems: 1458 */ 1459 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) 1460 mce_bootlog = 0; 1461 } 1462 if (monarch_timeout < 0) 1463 monarch_timeout = 0; 1464 if (mce_bootlog != 0) 1465 mce_panic_timeout = 30; 1466 1467 return 0; 1468} 1469 1470static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) 1471{ 1472 if (c->x86 != 5) 1473 return 0; 1474 1475 switch (c->x86_vendor) { 1476 case X86_VENDOR_INTEL: 1477 intel_p5_mcheck_init(c); 1478 return 1; 1479 break; 1480 case X86_VENDOR_CENTAUR: 1481 winchip_mcheck_init(c); 1482 return 1; 1483 break; 1484 } 1485 1486 return 0; 1487} 1488 1489static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) 1490{ 1491 switch (c->x86_vendor) { 1492 case X86_VENDOR_INTEL: 1493 mce_intel_feature_init(c); 1494 break; 1495 case X86_VENDOR_AMD: 1496 mce_amd_feature_init(c); 1497 break; 1498 default: 1499 break; 1500 } 1501} 1502 1503static void __mcheck_cpu_init_timer(void) 1504{ 1505 struct timer_list *t = &__get_cpu_var(mce_timer); 1506 int *n = &__get_cpu_var(mce_next_interval); 1507 1508 setup_timer(t, mce_start_timer, smp_processor_id()); 1509 1510 if (mce_ignore_ce) 1511 return; 1512 1513 *n = check_interval * HZ; 1514 if (!*n) 1515 return; 1516 t->expires = round_jiffies(jiffies + *n); 1517 add_timer_on(t, smp_processor_id()); 1518} 1519 1520/* Handle unconfigured int18 (should never happen) */ 1521static void unexpected_machine_check(struct pt_regs *regs, long error_code) 1522{ 1523 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", 1524 smp_processor_id()); 1525} 1526 1527/* Call the installed machine check handler for this CPU setup. */ 1528void (*machine_check_vector)(struct pt_regs *, long error_code) = 1529 unexpected_machine_check; 1530 1531/* 1532 * Called for each booted CPU to set up machine checks. 1533 * Must be called with preempt off: 1534 */ 1535void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c) 1536{ 1537 if (mce_disabled) 1538 return; 1539 1540 if (__mcheck_cpu_ancient_init(c)) 1541 return; 1542 1543 if (!mce_available(c)) 1544 return; 1545 1546 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { 1547 mce_disabled = 1; 1548 return; 1549 } 1550 1551 machine_check_vector = do_machine_check; 1552 1553 __mcheck_cpu_init_generic(); 1554 __mcheck_cpu_init_vendor(c); 1555 __mcheck_cpu_init_timer(); 1556 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); 1557 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); 1558} 1559 1560/* 1561 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. 1562 */ 1563 1564static DEFINE_SPINLOCK(mce_chrdev_state_lock); 1565static int mce_chrdev_open_count; /* #times opened */ 1566static int mce_chrdev_open_exclu; /* already open exclusive? */ 1567 1568static int mce_chrdev_open(struct inode *inode, struct file *file) 1569{ 1570 spin_lock(&mce_chrdev_state_lock); 1571 1572 if (mce_chrdev_open_exclu || 1573 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { 1574 spin_unlock(&mce_chrdev_state_lock); 1575 1576 return -EBUSY; 1577 } 1578 1579 if (file->f_flags & O_EXCL) 1580 mce_chrdev_open_exclu = 1; 1581 mce_chrdev_open_count++; 1582 1583 spin_unlock(&mce_chrdev_state_lock); 1584 1585 return nonseekable_open(inode, file); 1586} 1587 1588static int mce_chrdev_release(struct inode *inode, struct file *file) 1589{ 1590 spin_lock(&mce_chrdev_state_lock); 1591 1592 mce_chrdev_open_count--; 1593 mce_chrdev_open_exclu = 0; 1594 1595 spin_unlock(&mce_chrdev_state_lock); 1596 1597 return 0; 1598} 1599 1600static void collect_tscs(void *data) 1601{ 1602 unsigned long *cpu_tsc = (unsigned long *)data; 1603 1604 rdtscll(cpu_tsc[smp_processor_id()]); 1605} 1606 1607static int mce_apei_read_done; 1608 1609/* Collect MCE record of previous boot in persistent storage via APEI ERST. */ 1610static int __mce_read_apei(char __user **ubuf, size_t usize) 1611{ 1612 int rc; 1613 u64 record_id; 1614 struct mce m; 1615 1616 if (usize < sizeof(struct mce)) 1617 return -EINVAL; 1618 1619 rc = apei_read_mce(&m, &record_id); 1620 /* Error or no more MCE record */ 1621 if (rc <= 0) { 1622 mce_apei_read_done = 1; 1623 /* 1624 * When ERST is disabled, mce_chrdev_read() should return 1625 * "no record" instead of "no device." 1626 */ 1627 if (rc == -ENODEV) 1628 return 0; 1629 return rc; 1630 } 1631 rc = -EFAULT; 1632 if (copy_to_user(*ubuf, &m, sizeof(struct mce))) 1633 return rc; 1634 /* 1635 * In fact, we should have cleared the record after that has 1636 * been flushed to the disk or sent to network in 1637 * /sbin/mcelog, but we have no interface to support that now, 1638 * so just clear it to avoid duplication. 1639 */ 1640 rc = apei_clear_mce(record_id); 1641 if (rc) { 1642 mce_apei_read_done = 1; 1643 return rc; 1644 } 1645 *ubuf += sizeof(struct mce); 1646 1647 return 0; 1648} 1649 1650static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, 1651 size_t usize, loff_t *off) 1652{ 1653 char __user *buf = ubuf; 1654 unsigned long *cpu_tsc; 1655 unsigned prev, next; 1656 int i, err; 1657 1658 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); 1659 if (!cpu_tsc) 1660 return -ENOMEM; 1661 1662 mutex_lock(&mce_chrdev_read_mutex); 1663 1664 if (!mce_apei_read_done) { 1665 err = __mce_read_apei(&buf, usize); 1666 if (err || buf != ubuf) 1667 goto out; 1668 } 1669 1670 next = rcu_dereference_check_mce(mcelog.next); 1671 1672 /* Only supports full reads right now */ 1673 err = -EINVAL; 1674 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) 1675 goto out; 1676 1677 err = 0; 1678 prev = 0; 1679 do { 1680 for (i = prev; i < next; i++) { 1681 unsigned long start = jiffies; 1682 struct mce *m = &mcelog.entry[i]; 1683 1684 while (!m->finished) { 1685 if (time_after_eq(jiffies, start + 2)) { 1686 memset(m, 0, sizeof(*m)); 1687 goto timeout; 1688 } 1689 cpu_relax(); 1690 } 1691 smp_rmb(); 1692 err |= copy_to_user(buf, m, sizeof(*m)); 1693 buf += sizeof(*m); 1694timeout: 1695 ; 1696 } 1697 1698 memset(mcelog.entry + prev, 0, 1699 (next - prev) * sizeof(struct mce)); 1700 prev = next; 1701 next = cmpxchg(&mcelog.next, prev, 0); 1702 } while (next != prev); 1703 1704 synchronize_sched(); 1705 1706 /* 1707 * Collect entries that were still getting written before the 1708 * synchronize. 1709 */ 1710 on_each_cpu(collect_tscs, cpu_tsc, 1); 1711 1712 for (i = next; i < MCE_LOG_LEN; i++) { 1713 struct mce *m = &mcelog.entry[i]; 1714 1715 if (m->finished && m->tsc < cpu_tsc[m->cpu]) { 1716 err |= copy_to_user(buf, m, sizeof(*m)); 1717 smp_rmb(); 1718 buf += sizeof(*m); 1719 memset(m, 0, sizeof(*m)); 1720 } 1721 } 1722 1723 if (err) 1724 err = -EFAULT; 1725 1726out: 1727 mutex_unlock(&mce_chrdev_read_mutex); 1728 kfree(cpu_tsc); 1729 1730 return err ? err : buf - ubuf; 1731} 1732 1733static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) 1734{ 1735 poll_wait(file, &mce_chrdev_wait, wait); 1736 if (rcu_access_index(mcelog.next)) 1737 return POLLIN | POLLRDNORM; 1738 if (!mce_apei_read_done && apei_check_mce()) 1739 return POLLIN | POLLRDNORM; 1740 return 0; 1741} 1742 1743static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, 1744 unsigned long arg) 1745{ 1746 int __user *p = (int __user *)arg; 1747 1748 if (!capable(CAP_SYS_ADMIN)) 1749 return -EPERM; 1750 1751 switch (cmd) { 1752 case MCE_GET_RECORD_LEN: 1753 return put_user(sizeof(struct mce), p); 1754 case MCE_GET_LOG_LEN: 1755 return put_user(MCE_LOG_LEN, p); 1756 case MCE_GETCLEAR_FLAGS: { 1757 unsigned flags; 1758 1759 do { 1760 flags = mcelog.flags; 1761 } while (cmpxchg(&mcelog.flags, flags, 0) != flags); 1762 1763 return put_user(flags, p); 1764 } 1765 default: 1766 return -ENOTTY; 1767 } 1768} 1769 1770static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, 1771 size_t usize, loff_t *off); 1772 1773void register_mce_write_callback(ssize_t (*fn)(struct file *filp, 1774 const char __user *ubuf, 1775 size_t usize, loff_t *off)) 1776{ 1777 mce_write = fn; 1778} 1779EXPORT_SYMBOL_GPL(register_mce_write_callback); 1780 1781ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, 1782 size_t usize, loff_t *off) 1783{ 1784 if (mce_write) 1785 return mce_write(filp, ubuf, usize, off); 1786 else 1787 return -EINVAL; 1788} 1789 1790static const struct file_operations mce_chrdev_ops = { 1791 .open = mce_chrdev_open, 1792 .release = mce_chrdev_release, 1793 .read = mce_chrdev_read, 1794 .write = mce_chrdev_write, 1795 .poll = mce_chrdev_poll, 1796 .unlocked_ioctl = mce_chrdev_ioctl, 1797 .llseek = no_llseek, 1798}; 1799 1800static struct miscdevice mce_chrdev_device = { 1801 MISC_MCELOG_MINOR, 1802 "mcelog", 1803 &mce_chrdev_ops, 1804}; 1805 1806/* 1807 * mce=off Disables machine check 1808 * mce=no_cmci Disables CMCI 1809 * mce=dont_log_ce Clears corrected events silently, no log created for CEs. 1810 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. 1811 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) 1812 * monarchtimeout is how long to wait for other CPUs on machine 1813 * check, or 0 to not wait 1814 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. 1815 * mce=nobootlog Don't log MCEs from before booting. 1816 */ 1817static int __init mcheck_enable(char *str) 1818{ 1819 if (*str == 0) { 1820 enable_p5_mce(); 1821 return 1; 1822 } 1823 if (*str == '=') 1824 str++; 1825 if (!strcmp(str, "off")) 1826 mce_disabled = 1; 1827 else if (!strcmp(str, "no_cmci")) 1828 mce_cmci_disabled = 1; 1829 else if (!strcmp(str, "dont_log_ce")) 1830 mce_dont_log_ce = 1; 1831 else if (!strcmp(str, "ignore_ce")) 1832 mce_ignore_ce = 1; 1833 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) 1834 mce_bootlog = (str[0] == 'b'); 1835 else if (isdigit(str[0])) { 1836 get_option(&str, &tolerant); 1837 if (*str == ',') { 1838 ++str; 1839 get_option(&str, &monarch_timeout); 1840 } 1841 } else { 1842 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", 1843 str); 1844 return 0; 1845 } 1846 return 1; 1847} 1848__setup("mce", mcheck_enable); 1849 1850int __init mcheck_init(void) 1851{ 1852 mcheck_intel_therm_init(); 1853 1854 return 0; 1855} 1856 1857/* 1858 * mce_syscore: PM support 1859 */ 1860 1861/* 1862 * Disable machine checks on suspend and shutdown. We can't really handle 1863 * them later. 1864 */ 1865static int mce_disable_error_reporting(void) 1866{ 1867 int i; 1868 1869 for (i = 0; i < banks; i++) { 1870 struct mce_bank *b = &mce_banks[i]; 1871 1872 if (b->init) 1873 wrmsrl(MSR_IA32_MCx_CTL(i), 0); 1874 } 1875 return 0; 1876} 1877 1878static int mce_syscore_suspend(void) 1879{ 1880 return mce_disable_error_reporting(); 1881} 1882 1883static void mce_syscore_shutdown(void) 1884{ 1885 mce_disable_error_reporting(); 1886} 1887 1888/* 1889 * On resume clear all MCE state. Don't want to see leftovers from the BIOS. 1890 * Only one CPU is active at this time, the others get re-added later using 1891 * CPU hotplug: 1892 */ 1893static void mce_syscore_resume(void) 1894{ 1895 __mcheck_cpu_init_generic(); 1896 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); 1897} 1898 1899static struct syscore_ops mce_syscore_ops = { 1900 .suspend = mce_syscore_suspend, 1901 .shutdown = mce_syscore_shutdown, 1902 .resume = mce_syscore_resume, 1903}; 1904 1905/* 1906 * mce_device: Sysfs support 1907 */ 1908 1909static void mce_cpu_restart(void *data) 1910{ 1911 if (!mce_available(__this_cpu_ptr(&cpu_info))) 1912 return; 1913 __mcheck_cpu_init_generic(); 1914 __mcheck_cpu_init_timer(); 1915} 1916 1917/* Reinit MCEs after user configuration changes */ 1918static void mce_restart(void) 1919{ 1920 mce_timer_delete_all(); 1921 on_each_cpu(mce_cpu_restart, NULL, 1); 1922} 1923 1924/* Toggle features for corrected errors */ 1925static void mce_disable_cmci(void *data) 1926{ 1927 if (!mce_available(__this_cpu_ptr(&cpu_info))) 1928 return; 1929 cmci_clear(); 1930} 1931 1932static void mce_enable_ce(void *all) 1933{ 1934 if (!mce_available(__this_cpu_ptr(&cpu_info))) 1935 return; 1936 cmci_reenable(); 1937 cmci_recheck(); 1938 if (all) 1939 __mcheck_cpu_init_timer(); 1940} 1941 1942static struct bus_type mce_subsys = { 1943 .name = "machinecheck", 1944 .dev_name = "machinecheck", 1945}; 1946 1947DEFINE_PER_CPU(struct device *, mce_device); 1948 1949__cpuinitdata 1950void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); 1951 1952static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) 1953{ 1954 return container_of(attr, struct mce_bank, attr); 1955} 1956 1957static ssize_t show_bank(struct device *s, struct device_attribute *attr, 1958 char *buf) 1959{ 1960 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); 1961} 1962 1963static ssize_t set_bank(struct device *s, struct device_attribute *attr, 1964 const char *buf, size_t size) 1965{ 1966 u64 new; 1967 1968 if (strict_strtoull(buf, 0, &new) < 0) 1969 return -EINVAL; 1970 1971 attr_to_bank(attr)->ctl = new; 1972 mce_restart(); 1973 1974 return size; 1975} 1976 1977static ssize_t 1978show_trigger(struct device *s, struct device_attribute *attr, char *buf) 1979{ 1980 strcpy(buf, mce_helper); 1981 strcat(buf, "\n"); 1982 return strlen(mce_helper) + 1; 1983} 1984 1985static ssize_t set_trigger(struct device *s, struct device_attribute *attr, 1986 const char *buf, size_t siz) 1987{ 1988 char *p; 1989 1990 strncpy(mce_helper, buf, sizeof(mce_helper)); 1991 mce_helper[sizeof(mce_helper)-1] = 0; 1992 p = strchr(mce_helper, '\n'); 1993 1994 if (p) 1995 *p = 0; 1996 1997 return strlen(mce_helper) + !!p; 1998} 1999 2000static ssize_t set_ignore_ce(struct device *s, 2001 struct device_attribute *attr, 2002 const char *buf, size_t size) 2003{ 2004 u64 new; 2005 2006 if (strict_strtoull(buf, 0, &new) < 0) 2007 return -EINVAL; 2008 2009 if (mce_ignore_ce ^ !!new) { 2010 if (new) { 2011 /* disable ce features */ 2012 mce_timer_delete_all(); 2013 on_each_cpu(mce_disable_cmci, NULL, 1); 2014 mce_ignore_ce = 1; 2015 } else { 2016 /* enable ce features */ 2017 mce_ignore_ce = 0; 2018 on_each_cpu(mce_enable_ce, (void *)1, 1); 2019 } 2020 } 2021 return size; 2022} 2023 2024static ssize_t set_cmci_disabled(struct device *s, 2025 struct device_attribute *attr, 2026 const char *buf, size_t size) 2027{ 2028 u64 new; 2029 2030 if (strict_strtoull(buf, 0, &new) < 0) 2031 return -EINVAL; 2032 2033 if (mce_cmci_disabled ^ !!new) { 2034 if (new) { 2035 /* disable cmci */ 2036 on_each_cpu(mce_disable_cmci, NULL, 1); 2037 mce_cmci_disabled = 1; 2038 } else { 2039 /* enable cmci */ 2040 mce_cmci_disabled = 0; 2041 on_each_cpu(mce_enable_ce, NULL, 1); 2042 } 2043 } 2044 return size; 2045} 2046 2047static ssize_t store_int_with_restart(struct device *s, 2048 struct device_attribute *attr, 2049 const char *buf, size_t size) 2050{ 2051 ssize_t ret = device_store_int(s, attr, buf, size); 2052 mce_restart(); 2053 return ret; 2054} 2055 2056static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); 2057static DEVICE_INT_ATTR(tolerant, 0644, tolerant); 2058static DEVICE_INT_ATTR(monarch_timeout, 0644, monarch_timeout); 2059static DEVICE_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); 2060 2061static struct dev_ext_attribute dev_attr_check_interval = { 2062 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), 2063 &check_interval 2064}; 2065 2066static struct dev_ext_attribute dev_attr_ignore_ce = { 2067 __ATTR(ignore_ce, 0644, device_show_int, set_ignore_ce), 2068 &mce_ignore_ce 2069}; 2070 2071static struct dev_ext_attribute dev_attr_cmci_disabled = { 2072 __ATTR(cmci_disabled, 0644, device_show_int, set_cmci_disabled), 2073 &mce_cmci_disabled 2074}; 2075 2076static struct device_attribute *mce_device_attrs[] = { 2077 &dev_attr_tolerant.attr, 2078 &dev_attr_check_interval.attr, 2079 &dev_attr_trigger, 2080 &dev_attr_monarch_timeout.attr, 2081 &dev_attr_dont_log_ce.attr, 2082 &dev_attr_ignore_ce.attr, 2083 &dev_attr_cmci_disabled.attr, 2084 NULL 2085}; 2086 2087static cpumask_var_t mce_device_initialized; 2088 2089static void mce_device_release(struct device *dev) 2090{ 2091 kfree(dev); 2092} 2093 2094/* Per cpu device init. All of the cpus still share the same ctrl bank: */ 2095static __cpuinit int mce_device_create(unsigned int cpu) 2096{ 2097 struct device *dev; 2098 int err; 2099 int i, j; 2100 2101 if (!mce_available(&boot_cpu_data)) 2102 return -EIO; 2103 2104 dev = kzalloc(sizeof *dev, GFP_KERNEL); 2105 if (!dev) 2106 return -ENOMEM; 2107 dev->id = cpu; 2108 dev->bus = &mce_subsys; 2109 dev->release = &mce_device_release; 2110 2111 err = device_register(dev); 2112 if (err) 2113 return err; 2114 2115 for (i = 0; mce_device_attrs[i]; i++) { 2116 err = device_create_file(dev, mce_device_attrs[i]); 2117 if (err) 2118 goto error; 2119 } 2120 for (j = 0; j < banks; j++) { 2121 err = device_create_file(dev, &mce_banks[j].attr); 2122 if (err) 2123 goto error2; 2124 } 2125 cpumask_set_cpu(cpu, mce_device_initialized); 2126 per_cpu(mce_device, cpu) = dev; 2127 2128 return 0; 2129error2: 2130 while (--j >= 0) 2131 device_remove_file(dev, &mce_banks[j].attr); 2132error: 2133 while (--i >= 0) 2134 device_remove_file(dev, mce_device_attrs[i]); 2135 2136 device_unregister(dev); 2137 2138 return err; 2139} 2140 2141static __cpuinit void mce_device_remove(unsigned int cpu) 2142{ 2143 struct device *dev = per_cpu(mce_device, cpu); 2144 int i; 2145 2146 if (!cpumask_test_cpu(cpu, mce_device_initialized)) 2147 return; 2148 2149 for (i = 0; mce_device_attrs[i]; i++) 2150 device_remove_file(dev, mce_device_attrs[i]); 2151 2152 for (i = 0; i < banks; i++) 2153 device_remove_file(dev, &mce_banks[i].attr); 2154 2155 device_unregister(dev); 2156 cpumask_clear_cpu(cpu, mce_device_initialized); 2157 per_cpu(mce_device, cpu) = NULL; 2158} 2159 2160/* Make sure there are no machine checks on offlined CPUs. */ 2161static void __cpuinit mce_disable_cpu(void *h) 2162{ 2163 unsigned long action = *(unsigned long *)h; 2164 int i; 2165 2166 if (!mce_available(__this_cpu_ptr(&cpu_info))) 2167 return; 2168 2169 if (!(action & CPU_TASKS_FROZEN)) 2170 cmci_clear(); 2171 for (i = 0; i < banks; i++) { 2172 struct mce_bank *b = &mce_banks[i]; 2173 2174 if (b->init) 2175 wrmsrl(MSR_IA32_MCx_CTL(i), 0); 2176 } 2177} 2178 2179static void __cpuinit mce_reenable_cpu(void *h) 2180{ 2181 unsigned long action = *(unsigned long *)h; 2182 int i; 2183 2184 if (!mce_available(__this_cpu_ptr(&cpu_info))) 2185 return; 2186 2187 if (!(action & CPU_TASKS_FROZEN)) 2188 cmci_reenable(); 2189 for (i = 0; i < banks; i++) { 2190 struct mce_bank *b = &mce_banks[i]; 2191 2192 if (b->init) 2193 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); 2194 } 2195} 2196 2197/* Get notified when a cpu comes on/off. Be hotplug friendly. */ 2198static int __cpuinit 2199mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) 2200{ 2201 unsigned int cpu = (unsigned long)hcpu; 2202 struct timer_list *t = &per_cpu(mce_timer, cpu); 2203 2204 switch (action) { 2205 case CPU_ONLINE: 2206 case CPU_ONLINE_FROZEN: 2207 mce_device_create(cpu); 2208 if (threshold_cpu_callback) 2209 threshold_cpu_callback(action, cpu); 2210 break; 2211 case CPU_DEAD: 2212 case CPU_DEAD_FROZEN: 2213 if (threshold_cpu_callback) 2214 threshold_cpu_callback(action, cpu); 2215 mce_device_remove(cpu); 2216 break; 2217 case CPU_DOWN_PREPARE: 2218 case CPU_DOWN_PREPARE_FROZEN: 2219 del_timer_sync(t); 2220 smp_call_function_single(cpu, mce_disable_cpu, &action, 1); 2221 break; 2222 case CPU_DOWN_FAILED: 2223 case CPU_DOWN_FAILED_FROZEN: 2224 if (!mce_ignore_ce && check_interval) { 2225 t->expires = round_jiffies(jiffies + 2226 __get_cpu_var(mce_next_interval)); 2227 add_timer_on(t, cpu); 2228 } 2229 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); 2230 break; 2231 case CPU_POST_DEAD: 2232 /* intentionally ignoring frozen here */ 2233 cmci_rediscover(cpu); 2234 break; 2235 } 2236 return NOTIFY_OK; 2237} 2238 2239static struct notifier_block mce_cpu_notifier __cpuinitdata = { 2240 .notifier_call = mce_cpu_callback, 2241}; 2242 2243static __init void mce_init_banks(void) 2244{ 2245 int i; 2246 2247 for (i = 0; i < banks; i++) { 2248 struct mce_bank *b = &mce_banks[i]; 2249 struct device_attribute *a = &b->attr; 2250 2251 sysfs_attr_init(&a->attr); 2252 a->attr.name = b->attrname; 2253 snprintf(b->attrname, ATTR_LEN, "bank%d", i); 2254 2255 a->attr.mode = 0644; 2256 a->show = show_bank; 2257 a->store = set_bank; 2258 } 2259} 2260 2261static __init int mcheck_init_device(void) 2262{ 2263 int err; 2264 int i = 0; 2265 2266 if (!mce_available(&boot_cpu_data)) 2267 return -EIO; 2268 2269 zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); 2270 2271 mce_init_banks(); 2272 2273 err = subsys_system_register(&mce_subsys, NULL); 2274 if (err) 2275 return err; 2276 2277 for_each_online_cpu(i) { 2278 err = mce_device_create(i); 2279 if (err) 2280 return err; 2281 } 2282 2283 register_syscore_ops(&mce_syscore_ops); 2284 register_hotcpu_notifier(&mce_cpu_notifier); 2285 2286 /* register character device /dev/mcelog */ 2287 misc_register(&mce_chrdev_device); 2288 2289 return err; 2290} 2291device_initcall(mcheck_init_device); 2292 2293/* 2294 * Old style boot options parsing. Only for compatibility. 2295 */ 2296static int __init mcheck_disable(char *str) 2297{ 2298 mce_disabled = 1; 2299 return 1; 2300} 2301__setup("nomce", mcheck_disable); 2302 2303#ifdef CONFIG_DEBUG_FS 2304struct dentry *mce_get_debugfs_dir(void) 2305{ 2306 static struct dentry *dmce; 2307 2308 if (!dmce) 2309 dmce = debugfs_create_dir("mce", NULL); 2310 2311 return dmce; 2312} 2313 2314static void mce_reset(void) 2315{ 2316 cpu_missing = 0; 2317 atomic_set(&mce_fake_paniced, 0); 2318 atomic_set(&mce_executing, 0); 2319 atomic_set(&mce_callin, 0); 2320 atomic_set(&global_nwo, 0); 2321} 2322 2323static int fake_panic_get(void *data, u64 *val) 2324{ 2325 *val = fake_panic; 2326 return 0; 2327} 2328 2329static int fake_panic_set(void *data, u64 val) 2330{ 2331 mce_reset(); 2332 fake_panic = val; 2333 return 0; 2334} 2335 2336DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, 2337 fake_panic_set, "%llu\n"); 2338 2339static int __init mcheck_debugfs_init(void) 2340{ 2341 struct dentry *dmce, *ffake_panic; 2342 2343 dmce = mce_get_debugfs_dir(); 2344 if (!dmce) 2345 return -ENOMEM; 2346 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, 2347 &fake_panic_fops); 2348 if (!ffake_panic) 2349 return -ENOMEM; 2350 2351 return 0; 2352} 2353late_initcall(mcheck_debugfs_init); 2354#endif 2355