devicetree.c revision 9079b35364e75ce6b968a179f861d2f819f33e61 
1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
5#include <linux/io.h>
6#include <linux/interrupt.h>
7#include <linux/list.h>
8#include <linux/of.h>
9#include <linux/of_fdt.h>
10#include <linux/of_address.h>
11#include <linux/of_platform.h>
12#include <linux/of_irq.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/of_pci.h>
16
17#include <asm/hpet.h>
18#include <asm/irq_controller.h>
19#include <asm/apic.h>
20#include <asm/pci_x86.h>
21
22__initdata u64 initial_dtb;
23char __initdata cmd_line[COMMAND_LINE_SIZE];
24static LIST_HEAD(irq_domains);
25static DEFINE_RAW_SPINLOCK(big_irq_lock);
26
27int __initdata of_ioapic;
28
29void add_interrupt_host(struct irq_domain *ih)
30{
31	unsigned long flags;
32
33	raw_spin_lock_irqsave(&big_irq_lock, flags);
34	list_add(&ih->l, &irq_domains);
35	raw_spin_unlock_irqrestore(&big_irq_lock, flags);
36}
37
38static struct irq_domain *get_ih_from_node(struct device_node *controller)
39{
40	struct irq_domain *ih, *found = NULL;
41	unsigned long flags;
42
43	raw_spin_lock_irqsave(&big_irq_lock, flags);
44	list_for_each_entry(ih, &irq_domains, l) {
45		if (ih->controller ==  controller) {
46			found = ih;
47			break;
48		}
49	}
50	raw_spin_unlock_irqrestore(&big_irq_lock, flags);
51	return found;
52}
53
54unsigned int irq_create_of_mapping(struct device_node *controller,
55				   const u32 *intspec, unsigned int intsize)
56{
57	struct irq_domain *ih;
58	u32 virq, type;
59	int ret;
60
61	ih = get_ih_from_node(controller);
62	if (!ih)
63		return 0;
64	ret = ih->xlate(ih, intspec, intsize, &virq, &type);
65	if (ret)
66		return ret;
67	if (type == IRQ_TYPE_NONE)
68		return virq;
69	/* set the mask if it is different from current */
70	if (type == (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK))
71		set_irq_type(virq, type);
72	return virq;
73}
74EXPORT_SYMBOL_GPL(irq_create_of_mapping);
75
76unsigned long pci_address_to_pio(phys_addr_t address)
77{
78	/*
79	 * The ioport address can be directly used by inX / outX
80	 */
81	BUG_ON(address >= (1 << 16));
82	return (unsigned long)address;
83}
84EXPORT_SYMBOL_GPL(pci_address_to_pio);
85
86void __init early_init_dt_scan_chosen_arch(unsigned long node)
87{
88	BUG();
89}
90
91void __init early_init_dt_add_memory_arch(u64 base, u64 size)
92{
93	BUG();
94}
95
96void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
97{
98	return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
99}
100
101void __init add_dtb(u64 data)
102{
103	initial_dtb = data + offsetof(struct setup_data, data);
104}
105
106/*
107 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
108 */
109static struct of_device_id __initdata ce4100_ids[] = {
110	{ .compatible = "intel,ce4100-cp", },
111	{ .compatible = "isa", },
112	{ .compatible = "pci", },
113	{},
114};
115
116static int __init add_bus_probe(void)
117{
118	if (!initial_boot_params)
119		return 0;
120
121	return of_platform_bus_probe(NULL, ce4100_ids, NULL);
122}
123module_init(add_bus_probe);
124
125#ifdef CONFIG_PCI
126static int x86_of_pci_irq_enable(struct pci_dev *dev)
127{
128	struct of_irq oirq;
129	u32 virq;
130	int ret;
131	u8 pin;
132
133	ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
134	if (ret)
135		return ret;
136	if (!pin)
137		return 0;
138
139	ret = of_irq_map_pci(dev, &oirq);
140	if (ret)
141		return ret;
142
143	virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
144			oirq.size);
145	if (virq == 0)
146		return -EINVAL;
147	dev->irq = virq;
148	return 0;
149}
150
151static void x86_of_pci_irq_disable(struct pci_dev *dev)
152{
153}
154
155void __cpuinit x86_of_pci_init(void)
156{
157	struct device_node *np;
158
159	pcibios_enable_irq = x86_of_pci_irq_enable;
160	pcibios_disable_irq = x86_of_pci_irq_disable;
161
162	for_each_node_by_type(np, "pci") {
163		const void *prop;
164		struct pci_bus *bus;
165		unsigned int bus_min;
166		struct device_node *child;
167
168		prop = of_get_property(np, "bus-range", NULL);
169		if (!prop)
170			continue;
171		bus_min = be32_to_cpup(prop);
172
173		bus = pci_find_bus(0, bus_min);
174		if (!bus) {
175			printk(KERN_ERR "Can't find a node for bus %s.\n",
176					np->full_name);
177			continue;
178		}
179
180		if (bus->self)
181			bus->self->dev.of_node = np;
182		else
183			bus->dev.of_node = np;
184
185		for_each_child_of_node(np, child) {
186			struct pci_dev *dev;
187			u32 devfn;
188
189			prop = of_get_property(child, "reg", NULL);
190			if (!prop)
191				continue;
192
193			devfn = (be32_to_cpup(prop) >> 8) & 0xff;
194			dev = pci_get_slot(bus, devfn);
195			if (!dev)
196				continue;
197			dev->dev.of_node = child;
198			pci_dev_put(dev);
199		}
200	}
201}
202#endif
203
204static void __init dtb_setup_hpet(void)
205{
206	struct device_node *dn;
207	struct resource r;
208	int ret;
209
210	dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
211	if (!dn)
212		return;
213	ret = of_address_to_resource(dn, 0, &r);
214	if (ret) {
215		WARN_ON(1);
216		return;
217	}
218	hpet_address = r.start;
219}
220
221static void __init dtb_lapic_setup(void)
222{
223#ifdef CONFIG_X86_LOCAL_APIC
224	if (apic_force_enable())
225		return;
226
227	smp_found_config = 1;
228	pic_mode = 1;
229	/* Required for ioapic registration */
230	set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
231	if (boot_cpu_physical_apicid == -1U)
232		boot_cpu_physical_apicid = read_apic_id();
233
234	generic_processor_info(boot_cpu_physical_apicid,
235			GET_APIC_VERSION(apic_read(APIC_LVR)));
236#endif
237}
238
239#ifdef CONFIG_X86_IO_APIC
240static unsigned int ioapic_id;
241
242static void __init dtb_add_ioapic(struct device_node *dn)
243{
244	struct resource r;
245	int ret;
246
247	ret = of_address_to_resource(dn, 0, &r);
248	if (ret) {
249		printk(KERN_ERR "Can't obtain address from node %s.\n",
250				dn->full_name);
251		return;
252	}
253	mp_register_ioapic(++ioapic_id, r.start, gsi_top);
254}
255
256static void __init dtb_ioapic_setup(void)
257{
258	struct device_node *dn;
259
260	if (!smp_found_config)
261		return;
262
263	for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
264		dtb_add_ioapic(dn);
265
266	if (nr_ioapics) {
267		of_ioapic = 1;
268		return;
269	}
270	printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
271	smp_found_config = 0;
272}
273#else
274static void __init dtb_ioapic_setup(void) {}
275#endif
276
277static void __init dtb_apic_setup(void)
278{
279	dtb_lapic_setup();
280	dtb_ioapic_setup();
281}
282
283void __init x86_dtb_find_config(void)
284{
285	if (initial_dtb)
286		smp_found_config = 1;
287	else
288		printk(KERN_ERR "Missing device tree!.\n");
289}
290
291void __init x86_dtb_get_config(unsigned int unused)
292{
293	u32 size, map_len;
294	void *new_dtb;
295
296	if (!initial_dtb)
297		return;
298
299	map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
300			(u64)sizeof(struct boot_param_header));
301
302	initial_boot_params = early_memremap(initial_dtb, map_len);
303	size = be32_to_cpu(initial_boot_params->totalsize);
304	if (map_len < size) {
305		early_iounmap(initial_boot_params, map_len);
306		initial_boot_params = early_memremap(initial_dtb, size);
307		map_len = size;
308	}
309
310	new_dtb = alloc_bootmem(size);
311	memcpy(new_dtb, initial_boot_params, size);
312	early_iounmap(initial_boot_params, map_len);
313
314	initial_boot_params = new_dtb;
315
316	/* root level address cells */
317	of_scan_flat_dt(early_init_dt_scan_root, NULL);
318
319	unflatten_device_tree();
320	dtb_setup_hpet();
321	dtb_apic_setup();
322}
323