1669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/* 2669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * pata_amd.c - AMD PATA for new ATA layer 3669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * (C) 2005-2006 Red Hat Inc 4669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 5669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Based on pata-sil680. Errata information is taken from data sheets 6669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are 7669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * claimed by sata-nv.c. 8669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 9669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * TODO: 10669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Variable system clock when/if it makes sense 11669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Power management on ports 12669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 13669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 1425985edcedea6396277003854657b5f3cb31a628Lucas De Marchi * Documentation publicly available. 15669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 16669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 17669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <linux/kernel.h> 18669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <linux/module.h> 19669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <linux/pci.h> 20669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <linux/blkdev.h> 21669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <linux/delay.h> 22669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <scsi/scsi_host.h> 23669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#include <linux/libata.h> 24669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 25669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik#define DRV_NAME "pata_amd" 26c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox#define DRV_VERSION "0.4.1" 27669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 28669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 29669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * timing_setup - shared timing computation and load 30669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @ap: ATA port being set up 31669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @adev: drive being configured 32669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @offset: port offset 33669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @speed: target speed 34669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @clock: clock multiplier (number of times 33MHz for this part) 35669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 36669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Perform the actual timing set up for Nvidia or AMD PATA devices. 37669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * The actual devices vary so they all call into this helper function 38669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * providing the clock multipler and offset (because AMD and Nvidia put 39669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * the ports at different locations). 40669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 41669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 42669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock) 43669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 44669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik static const unsigned char amd_cyc2udma[] = { 45669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 46669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }; 47669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 48669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 49669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik struct ata_device *peer = ata_dev_pair(adev); 50669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik int dn = ap->port_no * 2 + adev->devno; 51669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik struct ata_timing at, apeer; 52669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik int T, UT; 53669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik const int amd_clock = 33333; /* KHz. */ 54669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik u8 t; 55669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 56669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik T = 1000000000 / amd_clock; 57d9c74fbead08de13e3965e1c6ffe289f24f45479Harvey Harrison UT = T; 58d9c74fbead08de13e3965e1c6ffe289f24f45479Harvey Harrison if (clock >= 2) 59d9c74fbead08de13e3965e1c6ffe289f24f45479Harvey Harrison UT = T / 2; 60669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 61669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik if (ata_timing_compute(adev, speed, &at, T, UT) < 0) { 62a44fec1fce5d5d14cc3ac4545b8da346394de666Joe Perches dev_err(&pdev->dev, "unknown mode %d\n", speed); 63669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik return; 64669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik } 65669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 66669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik if (peer) { 67669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* This may be over conservative */ 68669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik if (peer->dma_mode) { 69669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT); 70669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 71669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik } 72669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT); 73669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 74669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik } 75669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 76669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; 77669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; 78669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 79669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* 80669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Now do the setup work 81669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 82669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 83669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* Configure the address set up timing */ 84669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik pci_read_config_byte(pdev, offset + 0x0C, &t); 8507633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); 86669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik pci_write_config_byte(pdev, offset + 0x0C , t); 87669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 88669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* Configure the 8bit I/O timing */ 89669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), 9007633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1)); 91669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 92669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* Drive timing */ 93669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), 9407633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1)); 95669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 96669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik switch (clock) { 97669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik case 1: 9807633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03; 99669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik break; 100669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 101669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik case 2: 10207633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03; 103669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik break; 104669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 105669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik case 3: 10607633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03; 107669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik break; 108669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 109669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik case 4: 11007633b5d0723ce2ec31262e1096dcf61311bf078Harvey Harrison t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03; 111669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik break; 112669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 113669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik default: 114669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik return; 115669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik } 116669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 117669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* UDMA timing */ 118943547abdfe9b4e27e36a25987909619908dffbfBartlomiej Zolnierkiewicz if (at.udma) 119943547abdfe9b4e27e36a25987909619908dffbfBartlomiej Zolnierkiewicz pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); 120669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 121669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 122669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 123cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo * amd_pre_reset - perform reset handling 124cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo * @link: ATA link 125d4b2bab4f26345ea1803feb23ea92fbe3f6b77bcTejun Heo * @deadline: deadline jiffies for the operation 126669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 127eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox * Reset sequence checking enable bits to see which ports are 128eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox * active. 129669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 130669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 131cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int amd_pre_reset(struct ata_link *link, unsigned long deadline) 132669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 133669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik static const struct pci_bits amd_enable_bits[] = { 134669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { 0x40, 1, 0x02, 0x02 }, 135669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { 0x40, 1, 0x01, 0x01 } 136669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }; 137669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 138cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 139669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 14085cd7251b9112e3dabeac9fd3b175601ca607241Jeff Garzik 141c961922b73dab429a759f560952fd4c3f60bd6b3Alan Cox if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) 142c961922b73dab429a759f560952fd4c3f60bd6b3Alan Cox return -ENOENT; 143669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 1449363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_prereset(link, deadline); 145669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 146669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 147c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox/** 148c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * amd_cable_detect - report cable type 149c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * @ap: port 150c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * 151c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * AMD controller/BIOS setups record the cable type in word 0x42 152c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox */ 153c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 154eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Coxstatic int amd_cable_detect(struct ata_port *ap) 155669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 156eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox static const u32 bitmask[2] = {0x03, 0x0C}; 157669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 158eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox u8 ata66; 159669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 160eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox pci_read_config_byte(pdev, 0x42, &ata66); 161eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox if (ata66 & bitmask[ap->port_no]) 162eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox return ATA_CBL_PATA80; 163eb4a2c7f03db06dda0370591c958fa5a62ff2ec3Alan Cox return ATA_CBL_PATA40; 164669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 165669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 166669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 167c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * amd_fifo_setup - set the PIO FIFO for ATA/ATAPI 168c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * @ap: ATA interface 169c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * @adev: ATA device 170c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * 171c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * Set the PCI fifo for this device according to the devices present 172c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * on the bus at this point in time. We need to turn the post write buffer 173c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * off for ATAPI devices as we may need to issue a word sized write to the 174c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox * device as the final I/O 175c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox */ 176c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 177c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Coxstatic void amd_fifo_setup(struct ata_port *ap) 178c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox{ 179c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox struct ata_device *adev; 180c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox struct pci_dev *pdev = to_pci_dev(ap->host->dev); 181c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox static const u8 fifobit[2] = { 0xC0, 0x30}; 182c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox u8 fifo = fifobit[ap->port_no]; 183c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox u8 r; 184c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 185c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 186c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox ata_for_each_dev(adev, &ap->link, ENABLED) { 187c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox if (adev->class == ATA_DEV_ATAPI) 188c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox fifo = 0; 189c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox } 190c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */ 191c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox fifo = 0; 192c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 193c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox /* On the later chips the read prefetch bits become no-op bits */ 194c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox pci_read_config_byte(pdev, 0x41, &r); 195c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox r &= ~fifobit[ap->port_no]; 196c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox r |= fifo; 197c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox pci_write_config_byte(pdev, 0x41, r); 198c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox} 199c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 200c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox/** 201669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * amd33_set_piomode - set initial PIO mode data 202669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @ap: ATA interface 203669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @adev: ATA device 204669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 205669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Program the AMD registers for PIO mode. 206669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 207669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 208669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev) 209669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 210c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox amd_fifo_setup(ap); 211669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->pio_mode, 1); 212669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 213669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 214669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev) 215669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 216c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox amd_fifo_setup(ap); 217669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->pio_mode, 2); 218669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 219669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 220669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev) 221669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 222c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox amd_fifo_setup(ap); 223669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->pio_mode, 3); 224669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 225669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 226669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev) 227669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 228c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox amd_fifo_setup(ap); 229669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->pio_mode, 4); 230669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 231669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 232669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 233669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * amd33_set_dmamode - set initial DMA mode data 234669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @ap: ATA interface 235669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @adev: ATA device 236669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 237669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Program the MWDMA/UDMA modes for the AMD and Nvidia 238669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * chipset. 239669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 240669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 241669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev) 242669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 243669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->dma_mode, 1); 244669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 245669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 246669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev) 247669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 248669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->dma_mode, 2); 249669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 250669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 251669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 252669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 253669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->dma_mode, 3); 254669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 255669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 256669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 257669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 258669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x40, adev->dma_mode, 4); 259669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 260669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 261ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo/* Both host-side and drive-side detection results are worthless on NV 262ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * PATAs. Ignore them and just follow what BIOS configured. Both the 263ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * current configuration in PCI config reg and ACPI GTM result are 264ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * cached during driver attach and are consulted to select transfer 265ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * mode. 266ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo */ 267ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heostatic unsigned long nv_mode_filter(struct ata_device *dev, 268ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo unsigned long xfer_mask) 269ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo{ 270ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo static const unsigned int udma_mask_map[] = 271ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0, 272ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 }; 273ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo struct ata_port *ap = dev->link->ap; 274ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo char acpi_str[32] = ""; 275ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo u32 saved_udma, udma; 276ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo const struct ata_acpi_gtm *gtm; 277ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo unsigned long bios_limit = 0, acpi_limit = 0, limit; 278ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 279ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* find out what BIOS configured */ 280ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo udma = saved_udma = (unsigned long)ap->host->private_data; 281ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 282ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (ap->port_no == 0) 283ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo udma >>= 16; 284ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (dev->devno == 0) 285ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo udma >>= 8; 286ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 287ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if ((udma & 0xc0) == 0xc0) 288ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]); 289ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 290ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* consult ACPI GTM too */ 291ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo gtm = ata_acpi_init_gtm(ap); 292ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (gtm) { 293ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo acpi_limit = ata_acpi_gtm_xfermask(dev, gtm); 294ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 295ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)", 296ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags); 297ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo } 298ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 299ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* be optimistic, EH can take care of things if something goes wrong */ 300ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo limit = bios_limit | acpi_limit; 301ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 302ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* If PIO or DMA isn't configured at all, don't limit. Let EH 303ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * handle it. 304ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo */ 305ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (!(limit & ATA_MASK_PIO)) 306ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo limit |= ATA_MASK_PIO; 307ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA))) 308ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA; 30990950a2504b66d626a73f55ca949a2e79ff4b7c4Robert Hancock /* PIO4, MWDMA2, UDMA2 should always be supported regardless of 31090950a2504b66d626a73f55ca949a2e79ff4b7c4Robert Hancock cable detection result */ 31190950a2504b66d626a73f55ca949a2e79ff4b7c4Robert Hancock limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2); 312ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 313a9a79dfec239568bdbf778242f8fcd10bcc5b9e2Joe Perches ata_port_dbg(ap, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, " 314ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n", 315ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo xfer_mask, limit, xfer_mask & limit, bios_limit, 316ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo saved_udma, acpi_limit, acpi_str); 317ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 318ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo return xfer_mask & limit; 319ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo} 320669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 321669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 322669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * nv_probe_init - cable detection 323cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo * @lin: ATA link 324669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 325669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Perform cable detection. The BIOS stores this in PCI config 326669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * space for us. 327669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 328669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 329cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heostatic int nv_pre_reset(struct ata_link *link, unsigned long deadline) 330d4b2bab4f26345ea1803feb23ea92fbe3f6b77bcTejun Heo{ 33176ff3c6e3b389a5a7692811dd456e0ff58340cacAlan Cox static const struct pci_bits nv_enable_bits[] = { 33276ff3c6e3b389a5a7692811dd456e0ff58340cacAlan Cox { 0x50, 1, 0x02, 0x02 }, 33376ff3c6e3b389a5a7692811dd456e0ff58340cacAlan Cox { 0x50, 1, 0x01, 0x01 } 33476ff3c6e3b389a5a7692811dd456e0ff58340cacAlan Cox }; 335669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 336cc0680a580b5be81a1ca321b58f8e9b80b5c1052Tejun Heo struct ata_port *ap = link->ap; 337669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik struct pci_dev *pdev = to_pci_dev(ap->host->dev); 338669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 339c961922b73dab429a759f560952fd4c3f60bd6b3Alan Cox if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no])) 340c961922b73dab429a759f560952fd4c3f60bd6b3Alan Cox return -ENOENT; 34176ff3c6e3b389a5a7692811dd456e0ff58340cacAlan Cox 3429363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo return ata_sff_prereset(link, deadline); 343669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 344669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 345669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 346669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * nv100_set_piomode - set initial PIO mode data 347669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @ap: ATA interface 348669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @adev: ATA device 349669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 350669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Program the AMD registers for PIO mode. 351669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 352669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 353669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev) 354669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 355669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x50, adev->pio_mode, 3); 356669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 357669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 358669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev) 359669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 360669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x50, adev->pio_mode, 4); 361669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 362669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 363669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik/** 364669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * nv100_set_dmamode - set initial DMA mode data 365669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @ap: ATA interface 366669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * @adev: ATA device 367669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * 368669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * Program the MWDMA/UDMA modes for the AMD and Nvidia 369669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik * chipset. 370669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik */ 371669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 372669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 373669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 374669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x50, adev->dma_mode, 3); 375669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 376669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 377669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 378669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 379669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik timing_setup(ap, adev, 0x50, adev->dma_mode, 4); 380669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 381669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 382ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heostatic void nv_host_stop(struct ata_host *host) 383ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo{ 384ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo u32 udma = (unsigned long)host->private_data; 385ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 386ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* restore PCI config register 0x60 */ 387ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma); 388ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo} 389ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 390669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct scsi_host_template amd_sht = { 39168d1d07b510bb57a504588adc2bd2758adea0965Tejun Heo ATA_BMDMA_SHT(DRV_NAME), 392669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 393669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 394029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic const struct ata_port_operations amd_base_port_ops = { 395871af1210f13966ab911ed2166e4ab2ce775b99dAlan Cox .inherits = &ata_bmdma32_port_ops, 396887125e3740283be25564bfc6fb5d24974b651abTejun Heo .prereset = amd_pre_reset, 397029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo}; 398029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo 399669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct ata_port_operations amd33_port_ops = { 400029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &amd_base_port_ops, 401029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .cable_detect = ata_cable_40wire, 402669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_piomode = amd33_set_piomode, 403669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_dmamode = amd33_set_dmamode, 404669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 405669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 406669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct ata_port_operations amd66_port_ops = { 407029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &amd_base_port_ops, 408029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .cable_detect = ata_cable_unknown, 409669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_piomode = amd66_set_piomode, 410669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_dmamode = amd66_set_dmamode, 411669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 412669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 413669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct ata_port_operations amd100_port_ops = { 414029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &amd_base_port_ops, 415029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .cable_detect = ata_cable_unknown, 416669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_piomode = amd100_set_piomode, 417669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_dmamode = amd100_set_dmamode, 418669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 419669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 420669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct ata_port_operations amd133_port_ops = { 421029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &amd_base_port_ops, 422029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .cable_detect = amd_cable_detect, 423669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_piomode = amd133_set_piomode, 424669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_dmamode = amd133_set_dmamode, 425029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo}; 426669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 427029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heostatic const struct ata_port_operations nv_base_port_ops = { 428029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &ata_bmdma_port_ops, 429029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .cable_detect = ata_cable_ignore, 430029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .mode_filter = nv_mode_filter, 431887125e3740283be25564bfc6fb5d24974b651abTejun Heo .prereset = nv_pre_reset, 432029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .host_stop = nv_host_stop, 433669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 434669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 435669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct ata_port_operations nv100_port_ops = { 436029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &nv_base_port_ops, 437669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_piomode = nv100_set_piomode, 438669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_dmamode = nv100_set_dmamode, 439669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 440669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 441669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct ata_port_operations nv133_port_ops = { 442029cfd6b74fc5c517865fad78cf4a3ea8d9b664aTejun Heo .inherits = &nv_base_port_ops, 443669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_piomode = nv133_set_piomode, 444669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .set_dmamode = nv133_set_dmamode, 445669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 446669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 447c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Coxstatic void amd_clear_fifo(struct pci_dev *pdev) 448c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox{ 449c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox u8 fifo; 450c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox /* Disable the FIFO, the FIFO logic will re-enable it as 451c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox appropriate */ 452c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox pci_read_config_byte(pdev, 0x41, &fifo); 453c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox fifo &= 0x0F; 454c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox pci_write_config_byte(pdev, 0x41, fifo); 455c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox} 456c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox 457669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 458669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik{ 4591626aeb881236c8cb022b5e4ca594146a951d669Tejun Heo static const struct ata_port_info info[10] = { 46014bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø { /* 0: AMD 7401 - no swdma */ 4611d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 46214bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 46314bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 46414bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA2, 465669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd33_port_ops 466669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 467669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { /* 1: Early AMD7409 - no swdma */ 4681d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 46914bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 47014bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 47114bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA4, 472669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd66_port_ops 473669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 47414bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø { /* 2: AMD 7409 */ 4751d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 47614bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 47714bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 47814bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA4, 479669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd66_port_ops 480669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 481669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { /* 3: AMD 7411 */ 4821d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 48314bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 48414bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 48514bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA5, 486669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd100_port_ops 487669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 488669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { /* 4: AMD 7441 */ 4891d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 49014bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 49114bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 49214bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA5, 493669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd100_port_ops 494669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 49514bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø { /* 5: AMD 8111 - no swdma */ 4961d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 49714bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 49814bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 49914bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA6, 500669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd133_port_ops 501669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 50214bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø { /* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */ 5031d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 50414bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 50514bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 50614bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA5, 507669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd133_port_ops 508669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 509669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { /* 7: Nvidia Nforce */ 5101d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 51114bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 51214bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 51314bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA5, 514669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &nv100_port_ops 515669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 51614bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø { /* 8: Nvidia Nforce2 and later - no swdma */ 5171d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 51814bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 51914bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 52014bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA6, 521669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &nv133_port_ops 522669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }, 523669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik { /* 9: AMD CS5536 (Geode companion) */ 5241d2808fd3d2d5d2c0483796a0f443d1cb3f11367Jeff Garzik .flags = ATA_FLAG_SLAVE_POSS, 52514bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .pio_mask = ATA_PIO4, 52614bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .mwdma_mask = ATA_MWDMA2, 52714bdef982caeda19afe34010482867c18217c641Erik Inge Bolsø .udma_mask = ATA_UDMA5, 528669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .port_ops = &amd100_port_ops 529669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik } 530669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik }; 531887125e3740283be25564bfc6fb5d24974b651abTejun Heo const struct ata_port_info *ppi[] = { NULL, NULL }; 532669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik int type = id->driver_data; 533887125e3740283be25564bfc6fb5d24974b651abTejun Heo void *hpriv = NULL; 534669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik u8 fifo; 535f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo int rc; 536669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 53706296a1e684bcd40b9a28d5d8030809e4295528bJoe Perches ata_print_version_once(&pdev->dev, DRV_VERSION); 538669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 539f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo rc = pcim_enable_device(pdev); 540f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo if (rc) 541f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo return rc; 542f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo 543669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik pci_read_config_byte(pdev, 0x41, &fifo); 544669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 545669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* Check for AMD7409 without swdma errata and if found adjust type */ 54644c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok if (type == 1 && pdev->revision > 0x7) 547669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik type = 2; 548669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 549ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* Serenade ? */ 550ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD && 551ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) 552ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo type = 6; /* UDMA 100 only */ 553ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 554ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* 555ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * Okay, type is determined now. Apply type-specific workarounds. 556ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo */ 557887125e3740283be25564bfc6fb5d24974b651abTejun Heo ppi[0] = &info[type]; 558ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo 559ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (type < 3) 5609363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_pci_bmdma_clear_simplex(pdev); 561c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox if (pdev->vendor == PCI_VENDOR_ID_AMD) 562c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox amd_clear_fifo(pdev); 563ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo /* Cable detection on Nvidia chips doesn't work too well, 564ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo * cache BIOS programmed UDMA mode. 565ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo */ 566ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo if (type == 7 || type == 8) { 567ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo u32 udma; 568669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 569ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo pci_read_config_dword(pdev, 0x60, &udma); 570887125e3740283be25564bfc6fb5d24974b651abTejun Heo hpriv = (void *)(unsigned long)udma; 571ce54d1616302117fa98513ae916bb3333e1c02eaTejun Heo } 572669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 573669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik /* And fire it up */ 5741c5afdf7a629d2e77de8dd043b97a33dcd7e6dfaTejun Heo return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0); 575669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik} 576669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 57758eb8cd565af4a104395e3c10443951c1f73dafeBartlomiej Zolnierkiewicz#ifdef CONFIG_PM_SLEEP 578c304193a005b5262671c1389b1cae96d7afc952aAlan Coxstatic int amd_reinit_one(struct pci_dev *pdev) 579c304193a005b5262671c1389b1cae96d7afc952aAlan Cox{ 5800a86e1c857134efe2cdb31d74bc7ea21721db494Jingoo Han struct ata_host *host = pci_get_drvdata(pdev); 581f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo int rc; 582f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo 583f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo rc = ata_pci_device_do_resume(pdev); 584f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo if (rc) 585f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo return rc; 586f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo 587c304193a005b5262671c1389b1cae96d7afc952aAlan Cox if (pdev->vendor == PCI_VENDOR_ID_AMD) { 588c48052cc36e02fff6a9bb3cf83c4206b9127611fAlan Cox amd_clear_fifo(pdev); 589c304193a005b5262671c1389b1cae96d7afc952aAlan Cox if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 || 590c304193a005b5262671c1389b1cae96d7afc952aAlan Cox pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401) 5919363c3825ea9ad76561eb48a395349dd29211ed6Tejun Heo ata_pci_bmdma_clear_simplex(pdev); 592c304193a005b5262671c1389b1cae96d7afc952aAlan Cox } 593f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo ata_host_resume(host); 594f08048e94564d009b19038cfbdd800aa83e79c7fTejun Heo return 0; 595c304193a005b5262671c1389b1cae96d7afc952aAlan Cox} 596438ac6d5e3f8106a6bd1a5682c508d660294a85dTejun Heo#endif 597c304193a005b5262671c1389b1cae96d7afc952aAlan Cox 598669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic const struct pci_device_id amd[] = { 5992d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, 6002d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, 6012d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 }, 6022d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 }, 6032d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 }, 6042d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 }, 6052d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 }, 6062d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 }, 6072d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 }, 6082d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 }, 6092d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 }, 6102d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 }, 6112d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 }, 6122d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 }, 6132d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 }, 61405e2867a7bcc76de37e103a97ed48ba6872db797Peer Chen { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 }, 61505e2867a7bcc76de37e103a97ed48ba6872db797Peer Chen { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 }, 6169f7897554eeca34ec23dd877cc27402bd327a1cePeer Chen { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 }, 6179f7897554eeca34ec23dd877cc27402bd327a1cePeer Chen { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 }, 6182d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 }, 6192d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik 6202d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik { }, 621669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 622669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 623669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzikstatic struct pci_driver amd_pci_driver = { 6242d2744fc8be620a2dc469cf48349e3e704119f1bJeff Garzik .name = DRV_NAME, 625669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .id_table = amd, 626669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik .probe = amd_init_one, 627c304193a005b5262671c1389b1cae96d7afc952aAlan Cox .remove = ata_pci_remove_one, 62858eb8cd565af4a104395e3c10443951c1f73dafeBartlomiej Zolnierkiewicz#ifdef CONFIG_PM_SLEEP 629c304193a005b5262671c1389b1cae96d7afc952aAlan Cox .suspend = ata_pci_device_suspend, 630c304193a005b5262671c1389b1cae96d7afc952aAlan Cox .resume = amd_reinit_one, 631438ac6d5e3f8106a6bd1a5682c508d660294a85dTejun Heo#endif 632669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik}; 633669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 6342fc75da0c59634b81223af497c4a037822f6e457Axel Linmodule_pci_driver(amd_pci_driver); 635669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff Garzik 636669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff GarzikMODULE_AUTHOR("Alan Cox"); 637c9544bcb4c7df07555e4b22d297c5705738da09dAlan CoxMODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE"); 638669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff GarzikMODULE_LICENSE("GPL"); 639669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff GarzikMODULE_DEVICE_TABLE(pci, amd); 640669a5db411d85a14f86cd92bc16bf7ab5b8aa235Jeff GarzikMODULE_VERSION(DRV_VERSION); 641