pata_amd.c revision 887125e3740283be25564bfc6fb5d24974b651ab
1/* 2 * pata_amd.c - AMD PATA for new ATA layer 3 * (C) 2005-2006 Red Hat Inc 4 * Alan Cox <alan@redhat.com> 5 * 6 * Based on pata-sil680. Errata information is taken from data sheets 7 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are 8 * claimed by sata-nv.c. 9 * 10 * TODO: 11 * Variable system clock when/if it makes sense 12 * Power management on ports 13 * 14 * 15 * Documentation publically available. 16 */ 17 18#include <linux/kernel.h> 19#include <linux/module.h> 20#include <linux/pci.h> 21#include <linux/init.h> 22#include <linux/blkdev.h> 23#include <linux/delay.h> 24#include <scsi/scsi_host.h> 25#include <linux/libata.h> 26 27#define DRV_NAME "pata_amd" 28#define DRV_VERSION "0.3.10" 29 30/** 31 * timing_setup - shared timing computation and load 32 * @ap: ATA port being set up 33 * @adev: drive being configured 34 * @offset: port offset 35 * @speed: target speed 36 * @clock: clock multiplier (number of times 33MHz for this part) 37 * 38 * Perform the actual timing set up for Nvidia or AMD PATA devices. 39 * The actual devices vary so they all call into this helper function 40 * providing the clock multipler and offset (because AMD and Nvidia put 41 * the ports at different locations). 42 */ 43 44static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock) 45{ 46 static const unsigned char amd_cyc2udma[] = { 47 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 48 }; 49 50 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 51 struct ata_device *peer = ata_dev_pair(adev); 52 int dn = ap->port_no * 2 + adev->devno; 53 struct ata_timing at, apeer; 54 int T, UT; 55 const int amd_clock = 33333; /* KHz. */ 56 u8 t; 57 58 T = 1000000000 / amd_clock; 59 UT = T / min_t(int, max_t(int, clock, 1), 2); 60 61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) { 62 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed); 63 return; 64 } 65 66 if (peer) { 67 /* This may be over conservative */ 68 if (peer->dma_mode) { 69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT); 70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 71 } 72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT); 73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT); 74 } 75 76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; 77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; 78 79 /* 80 * Now do the setup work 81 */ 82 83 /* Configure the address set up timing */ 84 pci_read_config_byte(pdev, offset + 0x0C, &t); 85 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(at.setup, 1, 4) - 1) << ((3 - dn) << 1)); 86 pci_write_config_byte(pdev, offset + 0x0C , t); 87 88 /* Configure the 8bit I/O timing */ 89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)), 90 ((FIT(at.act8b, 1, 16) - 1) << 4) | (FIT(at.rec8b, 1, 16) - 1)); 91 92 /* Drive timing */ 93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn), 94 ((FIT(at.active, 1, 16) - 1) << 4) | (FIT(at.recover, 1, 16) - 1)); 95 96 switch (clock) { 97 case 1: 98 t = at.udma ? (0xc0 | (FIT(at.udma, 2, 5) - 2)) : 0x03; 99 break; 100 101 case 2: 102 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 2, 10)]) : 0x03; 103 break; 104 105 case 3: 106 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 10)]) : 0x03; 107 break; 108 109 case 4: 110 t = at.udma ? (0xc0 | amd_cyc2udma[FIT(at.udma, 1, 15)]) : 0x03; 111 break; 112 113 default: 114 return; 115 } 116 117 /* UDMA timing */ 118 if (at.udma) 119 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t); 120} 121 122/** 123 * amd_pre_reset - perform reset handling 124 * @link: ATA link 125 * @deadline: deadline jiffies for the operation 126 * 127 * Reset sequence checking enable bits to see which ports are 128 * active. 129 */ 130 131static int amd_pre_reset(struct ata_link *link, unsigned long deadline) 132{ 133 static const struct pci_bits amd_enable_bits[] = { 134 { 0x40, 1, 0x02, 0x02 }, 135 { 0x40, 1, 0x01, 0x01 } 136 }; 137 138 struct ata_port *ap = link->ap; 139 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 140 141 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no])) 142 return -ENOENT; 143 144 return ata_std_prereset(link, deadline); 145} 146 147static int amd_cable_detect(struct ata_port *ap) 148{ 149 static const u32 bitmask[2] = {0x03, 0x0C}; 150 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 151 u8 ata66; 152 153 pci_read_config_byte(pdev, 0x42, &ata66); 154 if (ata66 & bitmask[ap->port_no]) 155 return ATA_CBL_PATA80; 156 return ATA_CBL_PATA40; 157} 158 159/** 160 * amd33_set_piomode - set initial PIO mode data 161 * @ap: ATA interface 162 * @adev: ATA device 163 * 164 * Program the AMD registers for PIO mode. 165 */ 166 167static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev) 168{ 169 timing_setup(ap, adev, 0x40, adev->pio_mode, 1); 170} 171 172static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev) 173{ 174 timing_setup(ap, adev, 0x40, adev->pio_mode, 2); 175} 176 177static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev) 178{ 179 timing_setup(ap, adev, 0x40, adev->pio_mode, 3); 180} 181 182static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev) 183{ 184 timing_setup(ap, adev, 0x40, adev->pio_mode, 4); 185} 186 187/** 188 * amd33_set_dmamode - set initial DMA mode data 189 * @ap: ATA interface 190 * @adev: ATA device 191 * 192 * Program the MWDMA/UDMA modes for the AMD and Nvidia 193 * chipset. 194 */ 195 196static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev) 197{ 198 timing_setup(ap, adev, 0x40, adev->dma_mode, 1); 199} 200 201static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev) 202{ 203 timing_setup(ap, adev, 0x40, adev->dma_mode, 2); 204} 205 206static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 207{ 208 timing_setup(ap, adev, 0x40, adev->dma_mode, 3); 209} 210 211static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 212{ 213 timing_setup(ap, adev, 0x40, adev->dma_mode, 4); 214} 215 216/* Both host-side and drive-side detection results are worthless on NV 217 * PATAs. Ignore them and just follow what BIOS configured. Both the 218 * current configuration in PCI config reg and ACPI GTM result are 219 * cached during driver attach and are consulted to select transfer 220 * mode. 221 */ 222static unsigned long nv_mode_filter(struct ata_device *dev, 223 unsigned long xfer_mask) 224{ 225 static const unsigned int udma_mask_map[] = 226 { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0, 227 ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 }; 228 struct ata_port *ap = dev->link->ap; 229 char acpi_str[32] = ""; 230 u32 saved_udma, udma; 231 const struct ata_acpi_gtm *gtm; 232 unsigned long bios_limit = 0, acpi_limit = 0, limit; 233 234 /* find out what BIOS configured */ 235 udma = saved_udma = (unsigned long)ap->host->private_data; 236 237 if (ap->port_no == 0) 238 udma >>= 16; 239 if (dev->devno == 0) 240 udma >>= 8; 241 242 if ((udma & 0xc0) == 0xc0) 243 bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]); 244 245 /* consult ACPI GTM too */ 246 gtm = ata_acpi_init_gtm(ap); 247 if (gtm) { 248 acpi_limit = ata_acpi_gtm_xfermask(dev, gtm); 249 250 snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)", 251 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags); 252 } 253 254 /* be optimistic, EH can take care of things if something goes wrong */ 255 limit = bios_limit | acpi_limit; 256 257 /* If PIO or DMA isn't configured at all, don't limit. Let EH 258 * handle it. 259 */ 260 if (!(limit & ATA_MASK_PIO)) 261 limit |= ATA_MASK_PIO; 262 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA))) 263 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA; 264 265 ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, " 266 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n", 267 xfer_mask, limit, xfer_mask & limit, bios_limit, 268 saved_udma, acpi_limit, acpi_str); 269 270 return xfer_mask & limit; 271} 272 273/** 274 * nv_probe_init - cable detection 275 * @lin: ATA link 276 * 277 * Perform cable detection. The BIOS stores this in PCI config 278 * space for us. 279 */ 280 281static int nv_pre_reset(struct ata_link *link, unsigned long deadline) 282{ 283 static const struct pci_bits nv_enable_bits[] = { 284 { 0x50, 1, 0x02, 0x02 }, 285 { 0x50, 1, 0x01, 0x01 } 286 }; 287 288 struct ata_port *ap = link->ap; 289 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 290 291 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no])) 292 return -ENOENT; 293 294 return ata_std_prereset(link, deadline); 295} 296 297/** 298 * nv100_set_piomode - set initial PIO mode data 299 * @ap: ATA interface 300 * @adev: ATA device 301 * 302 * Program the AMD registers for PIO mode. 303 */ 304 305static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev) 306{ 307 timing_setup(ap, adev, 0x50, adev->pio_mode, 3); 308} 309 310static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev) 311{ 312 timing_setup(ap, adev, 0x50, adev->pio_mode, 4); 313} 314 315/** 316 * nv100_set_dmamode - set initial DMA mode data 317 * @ap: ATA interface 318 * @adev: ATA device 319 * 320 * Program the MWDMA/UDMA modes for the AMD and Nvidia 321 * chipset. 322 */ 323 324static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev) 325{ 326 timing_setup(ap, adev, 0x50, adev->dma_mode, 3); 327} 328 329static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev) 330{ 331 timing_setup(ap, adev, 0x50, adev->dma_mode, 4); 332} 333 334static void nv_host_stop(struct ata_host *host) 335{ 336 u32 udma = (unsigned long)host->private_data; 337 338 /* restore PCI config register 0x60 */ 339 pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma); 340} 341 342static struct scsi_host_template amd_sht = { 343 ATA_BMDMA_SHT(DRV_NAME), 344}; 345 346static const struct ata_port_operations amd_base_port_ops = { 347 .inherits = &ata_bmdma_port_ops, 348 .prereset = amd_pre_reset, 349}; 350 351static struct ata_port_operations amd33_port_ops = { 352 .inherits = &amd_base_port_ops, 353 .cable_detect = ata_cable_40wire, 354 .set_piomode = amd33_set_piomode, 355 .set_dmamode = amd33_set_dmamode, 356}; 357 358static struct ata_port_operations amd66_port_ops = { 359 .inherits = &amd_base_port_ops, 360 .cable_detect = ata_cable_unknown, 361 .set_piomode = amd66_set_piomode, 362 .set_dmamode = amd66_set_dmamode, 363}; 364 365static struct ata_port_operations amd100_port_ops = { 366 .inherits = &amd_base_port_ops, 367 .cable_detect = ata_cable_unknown, 368 .set_piomode = amd100_set_piomode, 369 .set_dmamode = amd100_set_dmamode, 370}; 371 372static struct ata_port_operations amd133_port_ops = { 373 .inherits = &amd_base_port_ops, 374 .cable_detect = amd_cable_detect, 375 .set_piomode = amd133_set_piomode, 376 .set_dmamode = amd133_set_dmamode, 377}; 378 379static const struct ata_port_operations nv_base_port_ops = { 380 .inherits = &ata_bmdma_port_ops, 381 .cable_detect = ata_cable_ignore, 382 .mode_filter = nv_mode_filter, 383 .prereset = nv_pre_reset, 384 .host_stop = nv_host_stop, 385}; 386 387static struct ata_port_operations nv100_port_ops = { 388 .inherits = &nv_base_port_ops, 389 .set_piomode = nv100_set_piomode, 390 .set_dmamode = nv100_set_dmamode, 391}; 392 393static struct ata_port_operations nv133_port_ops = { 394 .inherits = &nv_base_port_ops, 395 .set_piomode = nv133_set_piomode, 396 .set_dmamode = nv133_set_dmamode, 397}; 398 399static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 400{ 401 static const struct ata_port_info info[10] = { 402 { /* 0: AMD 7401 */ 403 .flags = ATA_FLAG_SLAVE_POSS, 404 .pio_mask = 0x1f, 405 .mwdma_mask = 0x07, /* No SWDMA */ 406 .udma_mask = 0x07, /* UDMA 33 */ 407 .port_ops = &amd33_port_ops 408 }, 409 { /* 1: Early AMD7409 - no swdma */ 410 .flags = ATA_FLAG_SLAVE_POSS, 411 .pio_mask = 0x1f, 412 .mwdma_mask = 0x07, 413 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 414 .port_ops = &amd66_port_ops 415 }, 416 { /* 2: AMD 7409, no swdma errata */ 417 .flags = ATA_FLAG_SLAVE_POSS, 418 .pio_mask = 0x1f, 419 .mwdma_mask = 0x07, 420 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 421 .port_ops = &amd66_port_ops 422 }, 423 { /* 3: AMD 7411 */ 424 .flags = ATA_FLAG_SLAVE_POSS, 425 .pio_mask = 0x1f, 426 .mwdma_mask = 0x07, 427 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 428 .port_ops = &amd100_port_ops 429 }, 430 { /* 4: AMD 7441 */ 431 .flags = ATA_FLAG_SLAVE_POSS, 432 .pio_mask = 0x1f, 433 .mwdma_mask = 0x07, 434 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 435 .port_ops = &amd100_port_ops 436 }, 437 { /* 5: AMD 8111*/ 438 .flags = ATA_FLAG_SLAVE_POSS, 439 .pio_mask = 0x1f, 440 .mwdma_mask = 0x07, 441 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */ 442 .port_ops = &amd133_port_ops 443 }, 444 { /* 6: AMD 8111 UDMA 100 (Serenade) */ 445 .flags = ATA_FLAG_SLAVE_POSS, 446 .pio_mask = 0x1f, 447 .mwdma_mask = 0x07, 448 .udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */ 449 .port_ops = &amd133_port_ops 450 }, 451 { /* 7: Nvidia Nforce */ 452 .flags = ATA_FLAG_SLAVE_POSS, 453 .pio_mask = 0x1f, 454 .mwdma_mask = 0x07, 455 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 456 .port_ops = &nv100_port_ops 457 }, 458 { /* 8: Nvidia Nforce2 and later */ 459 .flags = ATA_FLAG_SLAVE_POSS, 460 .pio_mask = 0x1f, 461 .mwdma_mask = 0x07, 462 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */ 463 .port_ops = &nv133_port_ops 464 }, 465 { /* 9: AMD CS5536 (Geode companion) */ 466 .flags = ATA_FLAG_SLAVE_POSS, 467 .pio_mask = 0x1f, 468 .mwdma_mask = 0x07, 469 .udma_mask = ATA_UDMA5, /* UDMA 100 */ 470 .port_ops = &amd100_port_ops 471 } 472 }; 473 const struct ata_port_info *ppi[] = { NULL, NULL }; 474 static int printed_version; 475 int type = id->driver_data; 476 void *hpriv = NULL; 477 u8 fifo; 478 int rc; 479 480 if (!printed_version++) 481 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 482 483 rc = pcim_enable_device(pdev); 484 if (rc) 485 return rc; 486 487 pci_read_config_byte(pdev, 0x41, &fifo); 488 489 /* Check for AMD7409 without swdma errata and if found adjust type */ 490 if (type == 1 && pdev->revision > 0x7) 491 type = 2; 492 493 /* Serenade ? */ 494 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD && 495 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) 496 type = 6; /* UDMA 100 only */ 497 498 /* 499 * Okay, type is determined now. Apply type-specific workarounds. 500 */ 501 ppi[0] = &info[type]; 502 503 if (type < 3) 504 ata_pci_clear_simplex(pdev); 505 506 /* Check for AMD7411 */ 507 if (type == 3) 508 /* FIFO is broken */ 509 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 510 else 511 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 512 513 /* Cable detection on Nvidia chips doesn't work too well, 514 * cache BIOS programmed UDMA mode. 515 */ 516 if (type == 7 || type == 8) { 517 u32 udma; 518 519 pci_read_config_dword(pdev, 0x60, &udma); 520 hpriv = (void *)(unsigned long)udma; 521 } 522 523 /* And fire it up */ 524 return ata_pci_init_one(pdev, ppi, &amd_sht, hpriv); 525} 526 527#ifdef CONFIG_PM 528static int amd_reinit_one(struct pci_dev *pdev) 529{ 530 struct ata_host *host = dev_get_drvdata(&pdev->dev); 531 int rc; 532 533 rc = ata_pci_device_do_resume(pdev); 534 if (rc) 535 return rc; 536 537 if (pdev->vendor == PCI_VENDOR_ID_AMD) { 538 u8 fifo; 539 pci_read_config_byte(pdev, 0x41, &fifo); 540 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) 541 /* FIFO is broken */ 542 pci_write_config_byte(pdev, 0x41, fifo & 0x0F); 543 else 544 pci_write_config_byte(pdev, 0x41, fifo | 0xF0); 545 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 || 546 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401) 547 ata_pci_clear_simplex(pdev); 548 } 549 550 ata_host_resume(host); 551 return 0; 552} 553#endif 554 555static const struct pci_device_id amd[] = { 556 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, 557 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, 558 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 }, 559 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 }, 560 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 }, 561 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 }, 562 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 }, 563 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 }, 564 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 }, 565 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 }, 566 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 }, 567 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 }, 568 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 }, 569 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 }, 570 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 }, 571 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 }, 572 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 }, 573 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 }, 574 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 }, 575 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 }, 576 577 { }, 578}; 579 580static struct pci_driver amd_pci_driver = { 581 .name = DRV_NAME, 582 .id_table = amd, 583 .probe = amd_init_one, 584 .remove = ata_pci_remove_one, 585#ifdef CONFIG_PM 586 .suspend = ata_pci_device_suspend, 587 .resume = amd_reinit_one, 588#endif 589}; 590 591static int __init amd_init(void) 592{ 593 return pci_register_driver(&amd_pci_driver); 594} 595 596static void __exit amd_exit(void) 597{ 598 pci_unregister_driver(&amd_pci_driver); 599} 600 601MODULE_AUTHOR("Alan Cox"); 602MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE"); 603MODULE_LICENSE("GPL"); 604MODULE_DEVICE_TABLE(pci, amd); 605MODULE_VERSION(DRV_VERSION); 606 607module_init(amd_init); 608module_exit(amd_exit); 609