pata_hpt366.c revision 3ee89f177e3cef0b5b024bcb6df683a3fa7d795f 
1/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
7 *
8 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003		Red Hat Inc
11 *
12 *
13 * TODO
14 *	Maybe PLL mode
15 *	Look into engine reset on timeout errors. Should not be
16 *		required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME	"pata_hpt366"
30#define DRV_VERSION	"0.6.2"
31
32struct hpt_clock {
33	u8	xfer_speed;
34	u32	timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 *        DMA. cycles = value + 1
41 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 *        DMA. cycles = value + 1
43 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 *        register access.
45 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
46 *        register access.
47 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 *        during task file register access.
49 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 *        xfer.
51 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 *        register access.
53 * 28     UDMA enable
54 * 29     DMA enable
55 * 30     PIO_MST enable. if set, the chip is in bus master mode during
56 *        PIO.
57 * 31     FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61	{	XFER_UDMA_4,	0x900fd943	},
62	{	XFER_UDMA_3,	0x900ad943	},
63	{	XFER_UDMA_2,	0x900bd943	},
64	{	XFER_UDMA_1,	0x9008d943	},
65	{	XFER_UDMA_0,	0x9008d943	},
66
67	{	XFER_MW_DMA_2,	0xa008d943	},
68	{	XFER_MW_DMA_1,	0xa010d955	},
69	{	XFER_MW_DMA_0,	0xa010d9fc	},
70
71	{	XFER_PIO_4,	0xc008d963	},
72	{	XFER_PIO_3,	0xc010d974	},
73	{	XFER_PIO_2,	0xc010d997	},
74	{	XFER_PIO_1,	0xc010d9c7	},
75	{	XFER_PIO_0,	0xc018d9d9	},
76	{	0,		0x0120d9d9	}
77};
78
79static const struct hpt_clock hpt366_33[] = {
80	{	XFER_UDMA_4,	0x90c9a731	},
81	{	XFER_UDMA_3,	0x90cfa731	},
82	{	XFER_UDMA_2,	0x90caa731	},
83	{	XFER_UDMA_1,	0x90cba731	},
84	{	XFER_UDMA_0,	0x90c8a731	},
85
86	{	XFER_MW_DMA_2,	0xa0c8a731	},
87	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
88	{	XFER_MW_DMA_0,	0xa0c8a797	},
89
90	{	XFER_PIO_4,	0xc0c8a731	},
91	{	XFER_PIO_3,	0xc0c8a742	},
92	{	XFER_PIO_2,	0xc0d0a753	},
93	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
94	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
95	{	0,		0x0120a7a7	}
96};
97
98static const struct hpt_clock hpt366_25[] = {
99	{	XFER_UDMA_4,	0x90c98521	},
100	{	XFER_UDMA_3,	0x90cf8521	},
101	{	XFER_UDMA_2,	0x90cf8521	},
102	{	XFER_UDMA_1,	0x90cb8521	},
103	{	XFER_UDMA_0,	0x90cb8521	},
104
105	{	XFER_MW_DMA_2,	0xa0ca8521	},
106	{	XFER_MW_DMA_1,	0xa0ca8532	},
107	{	XFER_MW_DMA_0,	0xa0ca8575	},
108
109	{	XFER_PIO_4,	0xc0ca8521	},
110	{	XFER_PIO_3,	0xc0ca8532	},
111	{	XFER_PIO_2,	0xc0ca8542	},
112	{	XFER_PIO_1,	0xc0d08572	},
113	{	XFER_PIO_0,	0xc0d08585	},
114	{	0,		0x01208585	}
115};
116
117static const char *bad_ata33[] = {
118	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121	"Maxtor 90510D4",
122	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125	NULL
126};
127
128static const char *bad_ata66_4[] = {
129	"IBM-DTLA-307075",
130	"IBM-DTLA-307060",
131	"IBM-DTLA-307045",
132	"IBM-DTLA-307030",
133	"IBM-DTLA-307020",
134	"IBM-DTLA-307015",
135	"IBM-DTLA-305040",
136	"IBM-DTLA-305030",
137	"IBM-DTLA-305020",
138	"IC35L010AVER07-0",
139	"IC35L020AVER07-0",
140	"IC35L030AVER07-0",
141	"IC35L040AVER07-0",
142	"IC35L060AVER07-0",
143	"WDC AC310200R",
144	NULL
145};
146
147static const char *bad_ata66_3[] = {
148	"WDC AC310200R",
149	NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
154	unsigned char model_num[ATA_ID_PROD_LEN + 1];
155	int i = 0;
156
157	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
158
159	while (list[i] != NULL) {
160		if (!strcmp(list[i], model_num)) {
161			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
162				modestr, list[i]);
163			return 1;
164		}
165		i++;
166	}
167	return 0;
168}
169
170/**
171 *	hpt366_filter	-	mode selection filter
172 *	@adev: ATA device
173 *
174 *	Block UDMA on devices that cause trouble with this controller.
175 */
176
177static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
178{
179	if (adev->class == ATA_DEV_ATA) {
180		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
181			mask &= ~ATA_MASK_UDMA;
182		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
183			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
184		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
185			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
186	} else if (adev->class == ATA_DEV_ATAPI)
187		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
188
189	return ata_bmdma_mode_filter(adev, mask);
190}
191
192/**
193 *	hpt36x_find_mode	-	reset the hpt36x bus
194 *	@ap: ATA port
195 *	@speed: transfer mode
196 *
197 *	Return the 32bit register programming information for this channel
198 *	that matches the speed provided.
199 */
200
201static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
202{
203	struct hpt_clock *clocks = ap->host->private_data;
204
205	while(clocks->xfer_speed) {
206		if (clocks->xfer_speed == speed)
207			return clocks->timing;
208		clocks++;
209	}
210	BUG();
211	return 0xffffffffU;	/* silence compiler warning */
212}
213
214static int hpt36x_cable_detect(struct ata_port *ap)
215{
216	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
217	u8 ata66;
218
219	/*
220	 * Each channel of pata_hpt366 occupies separate PCI function
221	 * as the primary channel and bit1 indicates the cable type.
222	 */
223	pci_read_config_byte(pdev, 0x5A, &ata66);
224	if (ata66 & 2)
225		return ATA_CBL_PATA40;
226	return ATA_CBL_PATA80;
227}
228
229/**
230 *	hpt366_set_piomode		-	PIO setup
231 *	@ap: ATA interface
232 *	@adev: device on the interface
233 *
234 *	Perform PIO mode setup.
235 */
236
237static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
238{
239	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
240	u32 addr1, addr2;
241	u32 reg;
242	u32 mode;
243	u8 fast;
244
245	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
246	addr2 = 0x51 + 4 * ap->port_no;
247
248	/* Fast interrupt prediction disable, hold off interrupt disable */
249	pci_read_config_byte(pdev, addr2, &fast);
250	if (fast & 0x80) {
251		fast &= ~0x80;
252		pci_write_config_byte(pdev, addr2, fast);
253	}
254
255	pci_read_config_dword(pdev, addr1, &reg);
256	mode = hpt36x_find_mode(ap, adev->pio_mode);
257	mode &= ~0x8000000;	/* No FIFO in PIO */
258	mode &= ~0x30070000;	/* Leave config bits alone */
259	reg &= 0x30070000;	/* Strip timing bits */
260	pci_write_config_dword(pdev, addr1, reg | mode);
261}
262
263/**
264 *	hpt366_set_dmamode		-	DMA timing setup
265 *	@ap: ATA interface
266 *	@adev: Device being configured
267 *
268 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
269 *	PIO, load the mode number and then set MWDMA or UDMA flag.
270 */
271
272static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
273{
274	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
275	u32 addr1, addr2;
276	u32 reg;
277	u32 mode;
278	u8 fast;
279
280	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
281	addr2 = 0x51 + 4 * ap->port_no;
282
283	/* Fast interrupt prediction disable, hold off interrupt disable */
284	pci_read_config_byte(pdev, addr2, &fast);
285	if (fast & 0x80) {
286		fast &= ~0x80;
287		pci_write_config_byte(pdev, addr2, fast);
288	}
289
290	pci_read_config_dword(pdev, addr1, &reg);
291	mode = hpt36x_find_mode(ap, adev->dma_mode);
292	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
293	mode &= ~0xC0000000;	/* Leave config bits alone */
294	reg &= 0xC0000000;	/* Strip timing bits */
295	pci_write_config_dword(pdev, addr1, reg | mode);
296}
297
298static struct scsi_host_template hpt36x_sht = {
299	ATA_BMDMA_SHT(DRV_NAME),
300};
301
302/*
303 *	Configuration for HPT366/68
304 */
305
306static struct ata_port_operations hpt366_port_ops = {
307	.inherits	= &ata_bmdma_port_ops,
308	.cable_detect	= hpt36x_cable_detect,
309	.mode_filter	= hpt366_filter,
310	.set_piomode	= hpt366_set_piomode,
311	.set_dmamode	= hpt366_set_dmamode,
312};
313
314/**
315 *	hpt36x_init_chipset	-	common chip setup
316 *	@dev: PCI device
317 *
318 *	Perform the chip setup work that must be done at both init and
319 *	resume time
320 */
321
322static void hpt36x_init_chipset(struct pci_dev *dev)
323{
324	u8 drive_fast;
325	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
326	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
327	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
328	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
329
330	pci_read_config_byte(dev, 0x51, &drive_fast);
331	if (drive_fast & 0x80)
332		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
333}
334
335/**
336 *	hpt36x_init_one		-	Initialise an HPT366/368
337 *	@dev: PCI device
338 *	@id: Entry in match table
339 *
340 *	Initialise an HPT36x device. There are some interesting complications
341 *	here. Firstly the chip may report 366 and be one of several variants.
342 *	Secondly all the timings depend on the clock for the chip which we must
343 *	detect and look up
344 *
345 *	This is the known chip mappings. It may be missing a couple of later
346 *	releases.
347 *
348 *	Chip version		PCI		Rev	Notes
349 *	HPT366			4 (HPT366)	0	UDMA66
350 *	HPT366			4 (HPT366)	1	UDMA66
351 *	HPT368			4 (HPT366)	2	UDMA66
352 *	HPT37x/30x		4 (HPT366)	3+	Other driver
353 *
354 */
355
356static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
357{
358	static const struct ata_port_info info_hpt366 = {
359		.flags = ATA_FLAG_SLAVE_POSS,
360		.pio_mask = 0x1f,
361		.mwdma_mask = 0x07,
362		.udma_mask = ATA_UDMA4,
363		.port_ops = &hpt366_port_ops
364	};
365	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
366
367	void *hpriv = NULL;
368	u32 class_rev;
369	u32 reg1;
370	int rc;
371
372	rc = pcim_enable_device(dev);
373	if (rc)
374		return rc;
375
376	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
377	class_rev &= 0xFF;
378
379	/* May be a later chip in disguise. Check */
380	/* Newer chips are not in the HPT36x driver. Ignore them */
381	if (class_rev > 2)
382			return -ENODEV;
383
384	hpt36x_init_chipset(dev);
385
386	pci_read_config_dword(dev, 0x40,  &reg1);
387
388	/* PCI clocking determines the ATA timing values to use */
389	/* info_hpt366 is safe against re-entry so we can scribble on it */
390	switch((reg1 & 0x700) >> 8) {
391		case 9:
392			hpriv = &hpt366_40;
393			break;
394		case 5:
395			hpriv = &hpt366_25;
396			break;
397		default:
398			hpriv = &hpt366_33;
399			break;
400	}
401	/* Now kick off ATA set up */
402	return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
403}
404
405#ifdef CONFIG_PM
406static int hpt36x_reinit_one(struct pci_dev *dev)
407{
408	struct ata_host *host = dev_get_drvdata(&dev->dev);
409	int rc;
410
411	rc = ata_pci_device_do_resume(dev);
412	if (rc)
413		return rc;
414	hpt36x_init_chipset(dev);
415	ata_host_resume(host);
416	return 0;
417}
418#endif
419
420static const struct pci_device_id hpt36x[] = {
421	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
422	{ },
423};
424
425static struct pci_driver hpt36x_pci_driver = {
426	.name 		= DRV_NAME,
427	.id_table	= hpt36x,
428	.probe 		= hpt36x_init_one,
429	.remove		= ata_pci_remove_one,
430#ifdef CONFIG_PM
431	.suspend	= ata_pci_device_suspend,
432	.resume		= hpt36x_reinit_one,
433#endif
434};
435
436static int __init hpt36x_init(void)
437{
438	return pci_register_driver(&hpt36x_pci_driver);
439}
440
441static void __exit hpt36x_exit(void)
442{
443	pci_unregister_driver(&hpt36x_pci_driver);
444}
445
446MODULE_AUTHOR("Alan Cox");
447MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
448MODULE_LICENSE("GPL");
449MODULE_DEVICE_TABLE(pci, hpt36x);
450MODULE_VERSION(DRV_VERSION);
451
452module_init(hpt36x_init);
453module_exit(hpt36x_exit);
454