pata_hpt366.c revision bda3028813bd07f34f30288a492fbf6f7b8712dd 
1/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
7 *
8 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003		Red Hat Inc
11 *
12 *
13 * TODO
14 *	Maybe PLL mode
15 *	Look into engine reset on timeout errors. Should not be
16 *		required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME	"pata_hpt366"
30#define DRV_VERSION	"0.5"
31
32struct hpt_clock {
33	u8	xfer_speed;
34	u32	timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 *        DMA. cycles = value + 1
41 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 *        DMA. cycles = value + 1
43 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 *        register access.
45 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
46 *        register access.
47 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 *        during task file register access.
49 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 *        xfer.
51 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 *        register access.
53 * 28     UDMA enable
54 * 29     DMA enable
55 * 30     PIO_MST enable. if set, the chip is in bus master mode during
56 *        PIO.
57 * 31     FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61	{	XFER_UDMA_4,	0x900fd943	},
62	{	XFER_UDMA_3,	0x900ad943	},
63	{	XFER_UDMA_2,	0x900bd943	},
64	{	XFER_UDMA_1,	0x9008d943	},
65	{	XFER_UDMA_0,	0x9008d943	},
66
67	{	XFER_MW_DMA_2,	0xa008d943	},
68	{	XFER_MW_DMA_1,	0xa010d955	},
69	{	XFER_MW_DMA_0,	0xa010d9fc	},
70
71	{	XFER_PIO_4,	0xc008d963	},
72	{	XFER_PIO_3,	0xc010d974	},
73	{	XFER_PIO_2,	0xc010d997	},
74	{	XFER_PIO_1,	0xc010d9c7	},
75	{	XFER_PIO_0,	0xc018d9d9	},
76	{	0,		0x0120d9d9	}
77};
78
79static const struct hpt_clock hpt366_33[] = {
80	{	XFER_UDMA_4,	0x90c9a731	},
81	{	XFER_UDMA_3,	0x90cfa731	},
82	{	XFER_UDMA_2,	0x90caa731	},
83	{	XFER_UDMA_1,	0x90cba731	},
84	{	XFER_UDMA_0,	0x90c8a731	},
85
86	{	XFER_MW_DMA_2,	0xa0c8a731	},
87	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
88	{	XFER_MW_DMA_0,	0xa0c8a797	},
89
90	{	XFER_PIO_4,	0xc0c8a731	},
91	{	XFER_PIO_3,	0xc0c8a742	},
92	{	XFER_PIO_2,	0xc0d0a753	},
93	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
94	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
95	{	0,		0x0120a7a7	}
96};
97
98static const struct hpt_clock hpt366_25[] = {
99	{	XFER_UDMA_4,	0x90c98521	},
100	{	XFER_UDMA_3,	0x90cf8521	},
101	{	XFER_UDMA_2,	0x90cf8521	},
102	{	XFER_UDMA_1,	0x90cb8521	},
103	{	XFER_UDMA_0,	0x90cb8521	},
104
105	{	XFER_MW_DMA_2,	0xa0ca8521	},
106	{	XFER_MW_DMA_1,	0xa0ca8532	},
107	{	XFER_MW_DMA_0,	0xa0ca8575	},
108
109	{	XFER_PIO_4,	0xc0ca8521	},
110	{	XFER_PIO_3,	0xc0ca8532	},
111	{	XFER_PIO_2,	0xc0ca8542	},
112	{	XFER_PIO_1,	0xc0d08572	},
113	{	XFER_PIO_0,	0xc0d08585	},
114	{	0,		0x01208585	}
115};
116
117static const char *bad_ata33[] = {
118	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121	"Maxtor 90510D4",
122	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125	NULL
126};
127
128static const char *bad_ata66_4[] = {
129	"IBM-DTLA-307075",
130	"IBM-DTLA-307060",
131	"IBM-DTLA-307045",
132	"IBM-DTLA-307030",
133	"IBM-DTLA-307020",
134	"IBM-DTLA-307015",
135	"IBM-DTLA-305040",
136	"IBM-DTLA-305030",
137	"IBM-DTLA-305020",
138	"IC35L010AVER07-0",
139	"IC35L020AVER07-0",
140	"IC35L030AVER07-0",
141	"IC35L040AVER07-0",
142	"IC35L060AVER07-0",
143	"WDC AC310200R",
144	NULL
145};
146
147static const char *bad_ata66_3[] = {
148	"WDC AC310200R",
149	NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
154	unsigned char model_num[40];
155	char *s;
156	unsigned int len;
157	int i = 0;
158
159	ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
160	s = &model_num[0];
161	len = strnlen(s, sizeof(model_num));
162
163	/* ATAPI specifies that empty space is blank-filled; remove blanks */
164	while ((len > 0) && (s[len - 1] == ' ')) {
165		len--;
166		s[len] = 0;
167	}
168
169	while(list[i] != NULL) {
170		if (!strncmp(list[i], s, len)) {
171			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
172				modestr, list[i]);
173			return 1;
174		}
175		i++;
176	}
177	return 0;
178}
179
180/**
181 *	hpt366_filter	-	mode selection filter
182 *	@ap: ATA interface
183 *	@adev: ATA device
184 *
185 *	Block UDMA on devices that cause trouble with this controller.
186 */
187
188static unsigned long hpt366_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
189{
190	if (adev->class == ATA_DEV_ATA) {
191		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
192			mask &= ~ATA_MASK_UDMA;
193		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
194			mask &= ~(0x07 << ATA_SHIFT_UDMA);
195		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
196			mask &= ~(0x0F << ATA_SHIFT_UDMA);
197	}
198	return ata_pci_default_filter(ap, adev, mask);
199}
200
201/**
202 *	hpt36x_find_mode	-	reset the hpt36x bus
203 *	@ap: ATA port
204 *	@speed: transfer mode
205 *
206 *	Return the 32bit register programming information for this channel
207 *	that matches the speed provided.
208 */
209
210static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
211{
212	struct hpt_clock *clocks = ap->host->private_data;
213
214	while(clocks->xfer_speed) {
215		if (clocks->xfer_speed == speed)
216			return clocks->timing;
217		clocks++;
218	}
219	BUG();
220	return 0xffffffffU;	/* silence compiler warning */
221}
222
223static int hpt36x_pre_reset(struct ata_port *ap)
224{
225	u8 ata66;
226	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
227
228	pci_read_config_byte(pdev, 0x5A, &ata66);
229	if (ata66 & (1 << ap->port_no))
230		ap->cbl = ATA_CBL_PATA40;
231	else
232		ap->cbl = ATA_CBL_PATA80;
233	return ata_std_prereset(ap);
234}
235
236/**
237 *	hpt36x_error_handler	-	reset the hpt36x bus
238 *	@ap: ATA port to reset
239 *
240 *	Perform the reset handling for the 366/368
241 */
242
243static void hpt36x_error_handler(struct ata_port *ap)
244{
245	ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
246}
247
248/**
249 *	hpt366_set_piomode		-	PIO setup
250 *	@ap: ATA interface
251 *	@adev: device on the interface
252 *
253 *	Perform PIO mode setup.
254 */
255
256static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
257{
258	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
259	u32 addr1, addr2;
260	u32 reg;
261	u32 mode;
262	u8 fast;
263
264	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
265	addr2 = 0x51 + 4 * ap->port_no;
266
267	/* Fast interrupt prediction disable, hold off interrupt disable */
268	pci_read_config_byte(pdev, addr2, &fast);
269	if (fast & 0x80) {
270		fast &= ~0x80;
271		pci_write_config_byte(pdev, addr2, fast);
272	}
273
274	pci_read_config_dword(pdev, addr1, &reg);
275	mode = hpt36x_find_mode(ap, adev->pio_mode);
276	mode &= ~0x8000000;	/* No FIFO in PIO */
277	mode &= ~0x30070000;	/* Leave config bits alone */
278	reg &= 0x30070000;	/* Strip timing bits */
279	pci_write_config_dword(pdev, addr1, reg | mode);
280}
281
282/**
283 *	hpt366_set_dmamode		-	DMA timing setup
284 *	@ap: ATA interface
285 *	@adev: Device being configured
286 *
287 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
288 *	PIO, load the mode number and then set MWDMA or UDMA flag.
289 */
290
291static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
292{
293	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
294	u32 addr1, addr2;
295	u32 reg;
296	u32 mode;
297	u8 fast;
298
299	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
300	addr2 = 0x51 + 4 * ap->port_no;
301
302	/* Fast interrupt prediction disable, hold off interrupt disable */
303	pci_read_config_byte(pdev, addr2, &fast);
304	if (fast & 0x80) {
305		fast &= ~0x80;
306		pci_write_config_byte(pdev, addr2, fast);
307	}
308
309	pci_read_config_dword(pdev, addr1, &reg);
310	mode = hpt36x_find_mode(ap, adev->dma_mode);
311	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
312	mode &= ~0xC0000000;	/* Leave config bits alone */
313	reg &= 0xC0000000;	/* Strip timing bits */
314	pci_write_config_dword(pdev, addr1, reg | mode);
315}
316
317static struct scsi_host_template hpt36x_sht = {
318	.module			= THIS_MODULE,
319	.name			= DRV_NAME,
320	.ioctl			= ata_scsi_ioctl,
321	.queuecommand		= ata_scsi_queuecmd,
322	.can_queue		= ATA_DEF_QUEUE,
323	.this_id		= ATA_SHT_THIS_ID,
324	.sg_tablesize		= LIBATA_MAX_PRD,
325	.max_sectors		= ATA_MAX_SECTORS,
326	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
327	.emulated		= ATA_SHT_EMULATED,
328	.use_clustering		= ATA_SHT_USE_CLUSTERING,
329	.proc_name		= DRV_NAME,
330	.dma_boundary		= ATA_DMA_BOUNDARY,
331	.slave_configure	= ata_scsi_slave_config,
332	.bios_param		= ata_std_bios_param,
333};
334
335/*
336 *	Configuration for HPT366/68
337 */
338
339static struct ata_port_operations hpt366_port_ops = {
340	.port_disable	= ata_port_disable,
341	.set_piomode	= hpt366_set_piomode,
342	.set_dmamode	= hpt366_set_dmamode,
343	.mode_filter	= hpt366_filter,
344
345	.tf_load	= ata_tf_load,
346	.tf_read	= ata_tf_read,
347	.check_status 	= ata_check_status,
348	.exec_command	= ata_exec_command,
349	.dev_select 	= ata_std_dev_select,
350
351	.freeze		= ata_bmdma_freeze,
352	.thaw		= ata_bmdma_thaw,
353	.error_handler	= hpt36x_error_handler,
354	.post_internal_cmd = ata_bmdma_post_internal_cmd,
355
356	.bmdma_setup 	= ata_bmdma_setup,
357	.bmdma_start 	= ata_bmdma_start,
358	.bmdma_stop	= ata_bmdma_stop,
359	.bmdma_status 	= ata_bmdma_status,
360
361	.qc_prep 	= ata_qc_prep,
362	.qc_issue	= ata_qc_issue_prot,
363
364	.data_xfer	= ata_pio_data_xfer,
365
366	.irq_handler	= ata_interrupt,
367	.irq_clear	= ata_bmdma_irq_clear,
368
369	.port_start	= ata_port_start,
370	.port_stop	= ata_port_stop,
371	.host_stop	= ata_host_stop
372};
373
374/**
375 *	hpt36x_init_one		-	Initialise an HPT366/368
376 *	@dev: PCI device
377 *	@id: Entry in match table
378 *
379 *	Initialise an HPT36x device. There are some interesting complications
380 *	here. Firstly the chip may report 366 and be one of several variants.
381 *	Secondly all the timings depend on the clock for the chip which we must
382 *	detect and look up
383 *
384 *	This is the known chip mappings. It may be missing a couple of later
385 *	releases.
386 *
387 *	Chip version		PCI		Rev	Notes
388 *	HPT366			4 (HPT366)	0	UDMA66
389 *	HPT366			4 (HPT366)	1	UDMA66
390 *	HPT368			4 (HPT366)	2	UDMA66
391 *	HPT37x/30x		4 (HPT366)	3+	Other driver
392 *
393 */
394
395static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
396{
397	static struct ata_port_info info_hpt366 = {
398		.sht = &hpt36x_sht,
399		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
400		.pio_mask = 0x1f,
401		.mwdma_mask = 0x07,
402		.udma_mask = 0x1f,
403		.port_ops = &hpt366_port_ops
404	};
405	struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
406
407	u32 class_rev;
408	u32 reg1;
409	u8 drive_fast;
410
411	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
412	class_rev &= 0xFF;
413
414	/* May be a later chip in disguise. Check */
415	/* Newer chips are not in the HPT36x driver. Ignore them */
416	if (class_rev > 2)
417			return -ENODEV;
418
419	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
420	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
421	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
422	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
423
424	pci_read_config_byte(dev, 0x51, &drive_fast);
425	if (drive_fast & 0x80)
426		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
427
428	pci_read_config_dword(dev, 0x40,  &reg1);
429
430	/* PCI clocking determines the ATA timing values to use */
431	/* info_hpt366 is safe against re-entry so we can scribble on it */
432	switch(reg1 & 0x700) {
433		case 5:
434			info_hpt366.private_data = &hpt366_40;
435			break;
436		case 9:
437			info_hpt366.private_data = &hpt366_25;
438			break;
439		default:
440			info_hpt366.private_data = &hpt366_33;
441			break;
442	}
443	/* Now kick off ATA set up */
444	return ata_pci_init_one(dev, port_info, 2);
445}
446
447static struct pci_device_id hpt36x[] = {
448	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
449	{ 0, },
450};
451
452static struct pci_driver hpt36x_pci_driver = {
453        .name 		= DRV_NAME,
454	.id_table	= hpt36x,
455	.probe 		= hpt36x_init_one,
456	.remove		= ata_pci_remove_one
457};
458
459static int __init hpt36x_init(void)
460{
461	return pci_register_driver(&hpt36x_pci_driver);
462}
463
464
465static void __exit hpt36x_exit(void)
466{
467	pci_unregister_driver(&hpt36x_pci_driver);
468}
469
470
471MODULE_AUTHOR("Alan Cox");
472MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
473MODULE_LICENSE("GPL");
474MODULE_DEVICE_TABLE(pci, hpt36x);
475MODULE_VERSION(DRV_VERSION);
476
477module_init(hpt36x_init);
478module_exit(hpt36x_exit);
479