pata_hpt366.c revision d4b2bab4f26345ea1803feb23ea92fbe3f6b77bc
1/* 2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers. 3 * 4 * This driver is heavily based upon: 5 * 6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 7 * 8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 9 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 10 * Portions Copyright (C) 2003 Red Hat Inc 11 * 12 * 13 * TODO 14 * Maybe PLL mode 15 * Look into engine reset on timeout errors. Should not be 16 * required. 17 */ 18 19 20#include <linux/kernel.h> 21#include <linux/module.h> 22#include <linux/pci.h> 23#include <linux/init.h> 24#include <linux/blkdev.h> 25#include <linux/delay.h> 26#include <scsi/scsi_host.h> 27#include <linux/libata.h> 28 29#define DRV_NAME "pata_hpt366" 30#define DRV_VERSION "0.6.1" 31 32struct hpt_clock { 33 u8 xfer_speed; 34 u32 timing; 35}; 36 37/* key for bus clock timings 38 * bit 39 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW 40 * DMA. cycles = value + 1 41 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW 42 * DMA. cycles = value + 1 43 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file 44 * register access. 45 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file 46 * register access. 47 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. 48 * during task file register access. 49 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA 50 * xfer. 51 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task 52 * register access. 53 * 28 UDMA enable 54 * 29 DMA enable 55 * 30 PIO_MST enable. if set, the chip is in bus master mode during 56 * PIO. 57 * 31 FIFO enable. 58 */ 59 60static const struct hpt_clock hpt366_40[] = { 61 { XFER_UDMA_4, 0x900fd943 }, 62 { XFER_UDMA_3, 0x900ad943 }, 63 { XFER_UDMA_2, 0x900bd943 }, 64 { XFER_UDMA_1, 0x9008d943 }, 65 { XFER_UDMA_0, 0x9008d943 }, 66 67 { XFER_MW_DMA_2, 0xa008d943 }, 68 { XFER_MW_DMA_1, 0xa010d955 }, 69 { XFER_MW_DMA_0, 0xa010d9fc }, 70 71 { XFER_PIO_4, 0xc008d963 }, 72 { XFER_PIO_3, 0xc010d974 }, 73 { XFER_PIO_2, 0xc010d997 }, 74 { XFER_PIO_1, 0xc010d9c7 }, 75 { XFER_PIO_0, 0xc018d9d9 }, 76 { 0, 0x0120d9d9 } 77}; 78 79static const struct hpt_clock hpt366_33[] = { 80 { XFER_UDMA_4, 0x90c9a731 }, 81 { XFER_UDMA_3, 0x90cfa731 }, 82 { XFER_UDMA_2, 0x90caa731 }, 83 { XFER_UDMA_1, 0x90cba731 }, 84 { XFER_UDMA_0, 0x90c8a731 }, 85 86 { XFER_MW_DMA_2, 0xa0c8a731 }, 87 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */ 88 { XFER_MW_DMA_0, 0xa0c8a797 }, 89 90 { XFER_PIO_4, 0xc0c8a731 }, 91 { XFER_PIO_3, 0xc0c8a742 }, 92 { XFER_PIO_2, 0xc0d0a753 }, 93 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */ 94 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */ 95 { 0, 0x0120a7a7 } 96}; 97 98static const struct hpt_clock hpt366_25[] = { 99 { XFER_UDMA_4, 0x90c98521 }, 100 { XFER_UDMA_3, 0x90cf8521 }, 101 { XFER_UDMA_2, 0x90cf8521 }, 102 { XFER_UDMA_1, 0x90cb8521 }, 103 { XFER_UDMA_0, 0x90cb8521 }, 104 105 { XFER_MW_DMA_2, 0xa0ca8521 }, 106 { XFER_MW_DMA_1, 0xa0ca8532 }, 107 { XFER_MW_DMA_0, 0xa0ca8575 }, 108 109 { XFER_PIO_4, 0xc0ca8521 }, 110 { XFER_PIO_3, 0xc0ca8532 }, 111 { XFER_PIO_2, 0xc0ca8542 }, 112 { XFER_PIO_1, 0xc0d08572 }, 113 { XFER_PIO_0, 0xc0d08585 }, 114 { 0, 0x01208585 } 115}; 116 117static const char *bad_ata33[] = { 118 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 119 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 120 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 121 "Maxtor 90510D4", 122 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 123 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 124 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 125 NULL 126}; 127 128static const char *bad_ata66_4[] = { 129 "IBM-DTLA-307075", 130 "IBM-DTLA-307060", 131 "IBM-DTLA-307045", 132 "IBM-DTLA-307030", 133 "IBM-DTLA-307020", 134 "IBM-DTLA-307015", 135 "IBM-DTLA-305040", 136 "IBM-DTLA-305030", 137 "IBM-DTLA-305020", 138 "IC35L010AVER07-0", 139 "IC35L020AVER07-0", 140 "IC35L030AVER07-0", 141 "IC35L040AVER07-0", 142 "IC35L060AVER07-0", 143 "WDC AC310200R", 144 NULL 145}; 146 147static const char *bad_ata66_3[] = { 148 "WDC AC310200R", 149 NULL 150}; 151 152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) 153{ 154 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 155 int i = 0; 156 157 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 158 159 while (list[i] != NULL) { 160 if (!strcmp(list[i], model_num)) { 161 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", 162 modestr, list[i]); 163 return 1; 164 } 165 i++; 166 } 167 return 0; 168} 169 170/** 171 * hpt366_filter - mode selection filter 172 * @adev: ATA device 173 * 174 * Block UDMA on devices that cause trouble with this controller. 175 */ 176 177static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask) 178{ 179 if (adev->class == ATA_DEV_ATA) { 180 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) 181 mask &= ~ATA_MASK_UDMA; 182 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3)) 183 mask &= ~(0x07 << ATA_SHIFT_UDMA); 184 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4)) 185 mask &= ~(0x0F << ATA_SHIFT_UDMA); 186 } 187 return ata_pci_default_filter(adev, mask); 188} 189 190/** 191 * hpt36x_find_mode - reset the hpt36x bus 192 * @ap: ATA port 193 * @speed: transfer mode 194 * 195 * Return the 32bit register programming information for this channel 196 * that matches the speed provided. 197 */ 198 199static u32 hpt36x_find_mode(struct ata_port *ap, int speed) 200{ 201 struct hpt_clock *clocks = ap->host->private_data; 202 203 while(clocks->xfer_speed) { 204 if (clocks->xfer_speed == speed) 205 return clocks->timing; 206 clocks++; 207 } 208 BUG(); 209 return 0xffffffffU; /* silence compiler warning */ 210} 211 212static int hpt36x_cable_detect(struct ata_port *ap) 213{ 214 u8 ata66; 215 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 216 217 pci_read_config_byte(pdev, 0x5A, &ata66); 218 if (ata66 & (1 << ap->port_no)) 219 return ATA_CBL_PATA40; 220 return ATA_CBL_PATA80; 221} 222 223static int hpt36x_pre_reset(struct ata_port *ap, unsigned long deadline) 224{ 225 static const struct pci_bits hpt36x_enable_bits[] = { 226 { 0x50, 1, 0x04, 0x04 }, 227 { 0x54, 1, 0x04, 0x04 } 228 }; 229 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 230 231 if (!pci_test_config_bits(pdev, &hpt36x_enable_bits[ap->port_no])) 232 return -ENOENT; 233 234 return ata_std_prereset(ap, deadline); 235} 236 237/** 238 * hpt36x_error_handler - reset the hpt36x bus 239 * @ap: ATA port to reset 240 * 241 * Perform the reset handling for the 366/368 242 */ 243 244static void hpt36x_error_handler(struct ata_port *ap) 245{ 246 ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 247} 248 249/** 250 * hpt366_set_piomode - PIO setup 251 * @ap: ATA interface 252 * @adev: device on the interface 253 * 254 * Perform PIO mode setup. 255 */ 256 257static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev) 258{ 259 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 260 u32 addr1, addr2; 261 u32 reg; 262 u32 mode; 263 u8 fast; 264 265 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 266 addr2 = 0x51 + 4 * ap->port_no; 267 268 /* Fast interrupt prediction disable, hold off interrupt disable */ 269 pci_read_config_byte(pdev, addr2, &fast); 270 if (fast & 0x80) { 271 fast &= ~0x80; 272 pci_write_config_byte(pdev, addr2, fast); 273 } 274 275 pci_read_config_dword(pdev, addr1, ®); 276 mode = hpt36x_find_mode(ap, adev->pio_mode); 277 mode &= ~0x8000000; /* No FIFO in PIO */ 278 mode &= ~0x30070000; /* Leave config bits alone */ 279 reg &= 0x30070000; /* Strip timing bits */ 280 pci_write_config_dword(pdev, addr1, reg | mode); 281} 282 283/** 284 * hpt366_set_dmamode - DMA timing setup 285 * @ap: ATA interface 286 * @adev: Device being configured 287 * 288 * Set up the channel for MWDMA or UDMA modes. Much the same as with 289 * PIO, load the mode number and then set MWDMA or UDMA flag. 290 */ 291 292static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev) 293{ 294 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 295 u32 addr1, addr2; 296 u32 reg; 297 u32 mode; 298 u8 fast; 299 300 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); 301 addr2 = 0x51 + 4 * ap->port_no; 302 303 /* Fast interrupt prediction disable, hold off interrupt disable */ 304 pci_read_config_byte(pdev, addr2, &fast); 305 if (fast & 0x80) { 306 fast &= ~0x80; 307 pci_write_config_byte(pdev, addr2, fast); 308 } 309 310 pci_read_config_dword(pdev, addr1, ®); 311 mode = hpt36x_find_mode(ap, adev->dma_mode); 312 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ 313 mode &= ~0xC0000000; /* Leave config bits alone */ 314 reg &= 0xC0000000; /* Strip timing bits */ 315 pci_write_config_dword(pdev, addr1, reg | mode); 316} 317 318static struct scsi_host_template hpt36x_sht = { 319 .module = THIS_MODULE, 320 .name = DRV_NAME, 321 .ioctl = ata_scsi_ioctl, 322 .queuecommand = ata_scsi_queuecmd, 323 .can_queue = ATA_DEF_QUEUE, 324 .this_id = ATA_SHT_THIS_ID, 325 .sg_tablesize = LIBATA_MAX_PRD, 326 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 327 .emulated = ATA_SHT_EMULATED, 328 .use_clustering = ATA_SHT_USE_CLUSTERING, 329 .proc_name = DRV_NAME, 330 .dma_boundary = ATA_DMA_BOUNDARY, 331 .slave_configure = ata_scsi_slave_config, 332 .slave_destroy = ata_scsi_slave_destroy, 333 .bios_param = ata_std_bios_param, 334#ifdef CONFIG_PM 335 .resume = ata_scsi_device_resume, 336 .suspend = ata_scsi_device_suspend, 337#endif 338}; 339 340/* 341 * Configuration for HPT366/68 342 */ 343 344static struct ata_port_operations hpt366_port_ops = { 345 .port_disable = ata_port_disable, 346 .set_piomode = hpt366_set_piomode, 347 .set_dmamode = hpt366_set_dmamode, 348 .mode_filter = hpt366_filter, 349 350 .tf_load = ata_tf_load, 351 .tf_read = ata_tf_read, 352 .check_status = ata_check_status, 353 .exec_command = ata_exec_command, 354 .dev_select = ata_std_dev_select, 355 356 .freeze = ata_bmdma_freeze, 357 .thaw = ata_bmdma_thaw, 358 .error_handler = hpt36x_error_handler, 359 .post_internal_cmd = ata_bmdma_post_internal_cmd, 360 .cable_detect = hpt36x_cable_detect, 361 362 .bmdma_setup = ata_bmdma_setup, 363 .bmdma_start = ata_bmdma_start, 364 .bmdma_stop = ata_bmdma_stop, 365 .bmdma_status = ata_bmdma_status, 366 367 .qc_prep = ata_qc_prep, 368 .qc_issue = ata_qc_issue_prot, 369 370 .data_xfer = ata_data_xfer, 371 372 .irq_handler = ata_interrupt, 373 .irq_clear = ata_bmdma_irq_clear, 374 .irq_on = ata_irq_on, 375 .irq_ack = ata_irq_ack, 376 377 .port_start = ata_port_start, 378}; 379 380/** 381 * hpt36x_init_chipset - common chip setup 382 * @dev: PCI device 383 * 384 * Perform the chip setup work that must be done at both init and 385 * resume time 386 */ 387 388static void hpt36x_init_chipset(struct pci_dev *dev) 389{ 390 u8 drive_fast; 391 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 392 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 393 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 394 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 395 396 pci_read_config_byte(dev, 0x51, &drive_fast); 397 if (drive_fast & 0x80) 398 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80); 399} 400 401/** 402 * hpt36x_init_one - Initialise an HPT366/368 403 * @dev: PCI device 404 * @id: Entry in match table 405 * 406 * Initialise an HPT36x device. There are some interesting complications 407 * here. Firstly the chip may report 366 and be one of several variants. 408 * Secondly all the timings depend on the clock for the chip which we must 409 * detect and look up 410 * 411 * This is the known chip mappings. It may be missing a couple of later 412 * releases. 413 * 414 * Chip version PCI Rev Notes 415 * HPT366 4 (HPT366) 0 UDMA66 416 * HPT366 4 (HPT366) 1 UDMA66 417 * HPT368 4 (HPT366) 2 UDMA66 418 * HPT37x/30x 4 (HPT366) 3+ Other driver 419 * 420 */ 421 422static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id) 423{ 424 static struct ata_port_info info_hpt366 = { 425 .sht = &hpt36x_sht, 426 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 427 .pio_mask = 0x1f, 428 .mwdma_mask = 0x07, 429 .udma_mask = 0x1f, 430 .port_ops = &hpt366_port_ops 431 }; 432 struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366}; 433 434 u32 class_rev; 435 u32 reg1; 436 437 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 438 class_rev &= 0xFF; 439 440 /* May be a later chip in disguise. Check */ 441 /* Newer chips are not in the HPT36x driver. Ignore them */ 442 if (class_rev > 2) 443 return -ENODEV; 444 445 hpt36x_init_chipset(dev); 446 447 pci_read_config_dword(dev, 0x40, ®1); 448 449 /* PCI clocking determines the ATA timing values to use */ 450 /* info_hpt366 is safe against re-entry so we can scribble on it */ 451 switch((reg1 & 0x700) >> 8) { 452 case 5: 453 info_hpt366.private_data = &hpt366_40; 454 break; 455 case 9: 456 info_hpt366.private_data = &hpt366_25; 457 break; 458 default: 459 info_hpt366.private_data = &hpt366_33; 460 break; 461 } 462 /* Now kick off ATA set up */ 463 return ata_pci_init_one(dev, port_info, 2); 464} 465 466#ifdef CONFIG_PM 467static int hpt36x_reinit_one(struct pci_dev *dev) 468{ 469 hpt36x_init_chipset(dev); 470 return ata_pci_device_resume(dev); 471} 472#endif 473 474static const struct pci_device_id hpt36x[] = { 475 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, 476 { }, 477}; 478 479static struct pci_driver hpt36x_pci_driver = { 480 .name = DRV_NAME, 481 .id_table = hpt36x, 482 .probe = hpt36x_init_one, 483 .remove = ata_pci_remove_one, 484#ifdef CONFIG_PM 485 .suspend = ata_pci_device_suspend, 486 .resume = hpt36x_reinit_one, 487#endif 488}; 489 490static int __init hpt36x_init(void) 491{ 492 return pci_register_driver(&hpt36x_pci_driver); 493} 494 495static void __exit hpt36x_exit(void) 496{ 497 pci_unregister_driver(&hpt36x_pci_driver); 498} 499 500MODULE_AUTHOR("Alan Cox"); 501MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368"); 502MODULE_LICENSE("GPL"); 503MODULE_DEVICE_TABLE(pci, hpt36x); 504MODULE_VERSION(DRV_VERSION); 505 506module_init(hpt36x_init); 507module_exit(hpt36x_exit); 508