pata_hpt366.c revision f08048e94564d009b19038cfbdd800aa83e79c7f 
1/*
2 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
7 *
8 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003		Red Hat Inc
11 *
12 *
13 * TODO
14 *	Maybe PLL mode
15 *	Look into engine reset on timeout errors. Should not be
16 *		required.
17 */
18
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <scsi/scsi_host.h>
27#include <linux/libata.h>
28
29#define DRV_NAME	"pata_hpt366"
30#define DRV_VERSION	"0.6.2"
31
32struct hpt_clock {
33	u8	xfer_speed;
34	u32	timing;
35};
36
37/* key for bus clock timings
38 * bit
39 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
40 *        DMA. cycles = value + 1
41 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
42 *        DMA. cycles = value + 1
43 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
44 *        register access.
45 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
46 *        register access.
47 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
48 *        during task file register access.
49 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
50 *        xfer.
51 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
52 *        register access.
53 * 28     UDMA enable
54 * 29     DMA enable
55 * 30     PIO_MST enable. if set, the chip is in bus master mode during
56 *        PIO.
57 * 31     FIFO enable.
58 */
59
60static const struct hpt_clock hpt366_40[] = {
61	{	XFER_UDMA_4,	0x900fd943	},
62	{	XFER_UDMA_3,	0x900ad943	},
63	{	XFER_UDMA_2,	0x900bd943	},
64	{	XFER_UDMA_1,	0x9008d943	},
65	{	XFER_UDMA_0,	0x9008d943	},
66
67	{	XFER_MW_DMA_2,	0xa008d943	},
68	{	XFER_MW_DMA_1,	0xa010d955	},
69	{	XFER_MW_DMA_0,	0xa010d9fc	},
70
71	{	XFER_PIO_4,	0xc008d963	},
72	{	XFER_PIO_3,	0xc010d974	},
73	{	XFER_PIO_2,	0xc010d997	},
74	{	XFER_PIO_1,	0xc010d9c7	},
75	{	XFER_PIO_0,	0xc018d9d9	},
76	{	0,		0x0120d9d9	}
77};
78
79static const struct hpt_clock hpt366_33[] = {
80	{	XFER_UDMA_4,	0x90c9a731	},
81	{	XFER_UDMA_3,	0x90cfa731	},
82	{	XFER_UDMA_2,	0x90caa731	},
83	{	XFER_UDMA_1,	0x90cba731	},
84	{	XFER_UDMA_0,	0x90c8a731	},
85
86	{	XFER_MW_DMA_2,	0xa0c8a731	},
87	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
88	{	XFER_MW_DMA_0,	0xa0c8a797	},
89
90	{	XFER_PIO_4,	0xc0c8a731	},
91	{	XFER_PIO_3,	0xc0c8a742	},
92	{	XFER_PIO_2,	0xc0d0a753	},
93	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
94	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
95	{	0,		0x0120a7a7	}
96};
97
98static const struct hpt_clock hpt366_25[] = {
99	{	XFER_UDMA_4,	0x90c98521	},
100	{	XFER_UDMA_3,	0x90cf8521	},
101	{	XFER_UDMA_2,	0x90cf8521	},
102	{	XFER_UDMA_1,	0x90cb8521	},
103	{	XFER_UDMA_0,	0x90cb8521	},
104
105	{	XFER_MW_DMA_2,	0xa0ca8521	},
106	{	XFER_MW_DMA_1,	0xa0ca8532	},
107	{	XFER_MW_DMA_0,	0xa0ca8575	},
108
109	{	XFER_PIO_4,	0xc0ca8521	},
110	{	XFER_PIO_3,	0xc0ca8532	},
111	{	XFER_PIO_2,	0xc0ca8542	},
112	{	XFER_PIO_1,	0xc0d08572	},
113	{	XFER_PIO_0,	0xc0d08585	},
114	{	0,		0x01208585	}
115};
116
117static const char *bad_ata33[] = {
118	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121	"Maxtor 90510D4",
122	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125	NULL
126};
127
128static const char *bad_ata66_4[] = {
129	"IBM-DTLA-307075",
130	"IBM-DTLA-307060",
131	"IBM-DTLA-307045",
132	"IBM-DTLA-307030",
133	"IBM-DTLA-307020",
134	"IBM-DTLA-307015",
135	"IBM-DTLA-305040",
136	"IBM-DTLA-305030",
137	"IBM-DTLA-305020",
138	"IC35L010AVER07-0",
139	"IC35L020AVER07-0",
140	"IC35L030AVER07-0",
141	"IC35L040AVER07-0",
142	"IC35L060AVER07-0",
143	"WDC AC310200R",
144	NULL
145};
146
147static const char *bad_ata66_3[] = {
148	"WDC AC310200R",
149	NULL
150};
151
152static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
153{
154	unsigned char model_num[ATA_ID_PROD_LEN + 1];
155	int i = 0;
156
157	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
158
159	while (list[i] != NULL) {
160		if (!strcmp(list[i], model_num)) {
161			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
162				modestr, list[i]);
163			return 1;
164		}
165		i++;
166	}
167	return 0;
168}
169
170/**
171 *	hpt366_filter	-	mode selection filter
172 *	@adev: ATA device
173 *
174 *	Block UDMA on devices that cause trouble with this controller.
175 */
176
177static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
178{
179	if (adev->class == ATA_DEV_ATA) {
180		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
181			mask &= ~ATA_MASK_UDMA;
182		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
183			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
184		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
185			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
186	}
187	return ata_pci_default_filter(adev, mask);
188}
189
190/**
191 *	hpt36x_find_mode	-	reset the hpt36x bus
192 *	@ap: ATA port
193 *	@speed: transfer mode
194 *
195 *	Return the 32bit register programming information for this channel
196 *	that matches the speed provided.
197 */
198
199static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
200{
201	struct hpt_clock *clocks = ap->host->private_data;
202
203	while(clocks->xfer_speed) {
204		if (clocks->xfer_speed == speed)
205			return clocks->timing;
206		clocks++;
207	}
208	BUG();
209	return 0xffffffffU;	/* silence compiler warning */
210}
211
212static int hpt36x_cable_detect(struct ata_port *ap)
213{
214	u8 ata66;
215	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
216
217	pci_read_config_byte(pdev, 0x5A, &ata66);
218	if (ata66 & (1 << ap->port_no))
219		return ATA_CBL_PATA40;
220	return ATA_CBL_PATA80;
221}
222
223/**
224 *	hpt366_set_piomode		-	PIO setup
225 *	@ap: ATA interface
226 *	@adev: device on the interface
227 *
228 *	Perform PIO mode setup.
229 */
230
231static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
232{
233	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
234	u32 addr1, addr2;
235	u32 reg;
236	u32 mode;
237	u8 fast;
238
239	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
240	addr2 = 0x51 + 4 * ap->port_no;
241
242	/* Fast interrupt prediction disable, hold off interrupt disable */
243	pci_read_config_byte(pdev, addr2, &fast);
244	if (fast & 0x80) {
245		fast &= ~0x80;
246		pci_write_config_byte(pdev, addr2, fast);
247	}
248
249	pci_read_config_dword(pdev, addr1, &reg);
250	mode = hpt36x_find_mode(ap, adev->pio_mode);
251	mode &= ~0x8000000;	/* No FIFO in PIO */
252	mode &= ~0x30070000;	/* Leave config bits alone */
253	reg &= 0x30070000;	/* Strip timing bits */
254	pci_write_config_dword(pdev, addr1, reg | mode);
255}
256
257/**
258 *	hpt366_set_dmamode		-	DMA timing setup
259 *	@ap: ATA interface
260 *	@adev: Device being configured
261 *
262 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
263 *	PIO, load the mode number and then set MWDMA or UDMA flag.
264 */
265
266static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
267{
268	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
269	u32 addr1, addr2;
270	u32 reg;
271	u32 mode;
272	u8 fast;
273
274	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
275	addr2 = 0x51 + 4 * ap->port_no;
276
277	/* Fast interrupt prediction disable, hold off interrupt disable */
278	pci_read_config_byte(pdev, addr2, &fast);
279	if (fast & 0x80) {
280		fast &= ~0x80;
281		pci_write_config_byte(pdev, addr2, fast);
282	}
283
284	pci_read_config_dword(pdev, addr1, &reg);
285	mode = hpt36x_find_mode(ap, adev->dma_mode);
286	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
287	mode &= ~0xC0000000;	/* Leave config bits alone */
288	reg &= 0xC0000000;	/* Strip timing bits */
289	pci_write_config_dword(pdev, addr1, reg | mode);
290}
291
292static struct scsi_host_template hpt36x_sht = {
293	.module			= THIS_MODULE,
294	.name			= DRV_NAME,
295	.ioctl			= ata_scsi_ioctl,
296	.queuecommand		= ata_scsi_queuecmd,
297	.can_queue		= ATA_DEF_QUEUE,
298	.this_id		= ATA_SHT_THIS_ID,
299	.sg_tablesize		= LIBATA_MAX_PRD,
300	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
301	.emulated		= ATA_SHT_EMULATED,
302	.use_clustering		= ATA_SHT_USE_CLUSTERING,
303	.proc_name		= DRV_NAME,
304	.dma_boundary		= ATA_DMA_BOUNDARY,
305	.slave_configure	= ata_scsi_slave_config,
306	.slave_destroy		= ata_scsi_slave_destroy,
307	.bios_param		= ata_std_bios_param,
308};
309
310/*
311 *	Configuration for HPT366/68
312 */
313
314static struct ata_port_operations hpt366_port_ops = {
315	.set_piomode	= hpt366_set_piomode,
316	.set_dmamode	= hpt366_set_dmamode,
317	.mode_filter	= hpt366_filter,
318
319	.tf_load	= ata_tf_load,
320	.tf_read	= ata_tf_read,
321	.check_status 	= ata_check_status,
322	.exec_command	= ata_exec_command,
323	.dev_select 	= ata_std_dev_select,
324
325	.freeze		= ata_bmdma_freeze,
326	.thaw		= ata_bmdma_thaw,
327	.error_handler	= ata_bmdma_error_handler,
328	.post_internal_cmd = ata_bmdma_post_internal_cmd,
329	.cable_detect	= hpt36x_cable_detect,
330
331	.bmdma_setup 	= ata_bmdma_setup,
332	.bmdma_start 	= ata_bmdma_start,
333	.bmdma_stop	= ata_bmdma_stop,
334	.bmdma_status 	= ata_bmdma_status,
335
336	.qc_prep 	= ata_qc_prep,
337	.qc_issue	= ata_qc_issue_prot,
338
339	.data_xfer	= ata_data_xfer,
340
341	.irq_handler	= ata_interrupt,
342	.irq_clear	= ata_bmdma_irq_clear,
343	.irq_on		= ata_irq_on,
344
345	.port_start	= ata_sff_port_start,
346};
347
348/**
349 *	hpt36x_init_chipset	-	common chip setup
350 *	@dev: PCI device
351 *
352 *	Perform the chip setup work that must be done at both init and
353 *	resume time
354 */
355
356static void hpt36x_init_chipset(struct pci_dev *dev)
357{
358	u8 drive_fast;
359	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
360	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
361	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
362	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
363
364	pci_read_config_byte(dev, 0x51, &drive_fast);
365	if (drive_fast & 0x80)
366		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
367}
368
369/**
370 *	hpt36x_init_one		-	Initialise an HPT366/368
371 *	@dev: PCI device
372 *	@id: Entry in match table
373 *
374 *	Initialise an HPT36x device. There are some interesting complications
375 *	here. Firstly the chip may report 366 and be one of several variants.
376 *	Secondly all the timings depend on the clock for the chip which we must
377 *	detect and look up
378 *
379 *	This is the known chip mappings. It may be missing a couple of later
380 *	releases.
381 *
382 *	Chip version		PCI		Rev	Notes
383 *	HPT366			4 (HPT366)	0	UDMA66
384 *	HPT366			4 (HPT366)	1	UDMA66
385 *	HPT368			4 (HPT366)	2	UDMA66
386 *	HPT37x/30x		4 (HPT366)	3+	Other driver
387 *
388 */
389
390static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
391{
392	static const struct ata_port_info info_hpt366 = {
393		.sht = &hpt36x_sht,
394		.flags = ATA_FLAG_SLAVE_POSS,
395		.pio_mask = 0x1f,
396		.mwdma_mask = 0x07,
397		.udma_mask = ATA_UDMA4,
398		.port_ops = &hpt366_port_ops
399	};
400	struct ata_port_info info = info_hpt366;
401	const struct ata_port_info *ppi[] = { &info, NULL };
402
403	u32 class_rev;
404	u32 reg1;
405	int rc;
406
407	rc = pcim_enable_device(dev);
408	if (rc)
409		return rc;
410
411	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
412	class_rev &= 0xFF;
413
414	/* May be a later chip in disguise. Check */
415	/* Newer chips are not in the HPT36x driver. Ignore them */
416	if (class_rev > 2)
417			return -ENODEV;
418
419	hpt36x_init_chipset(dev);
420
421	pci_read_config_dword(dev, 0x40,  &reg1);
422
423	/* PCI clocking determines the ATA timing values to use */
424	/* info_hpt366 is safe against re-entry so we can scribble on it */
425	switch((reg1 & 0x700) >> 8) {
426		case 5:
427			info.private_data = &hpt366_40;
428			break;
429		case 9:
430			info.private_data = &hpt366_25;
431			break;
432		default:
433			info.private_data = &hpt366_33;
434			break;
435	}
436	/* Now kick off ATA set up */
437	return ata_pci_init_one(dev, ppi);
438}
439
440#ifdef CONFIG_PM
441static int hpt36x_reinit_one(struct pci_dev *dev)
442{
443	struct ata_host *host = dev_get_drvdata(&dev->dev);
444	int rc;
445
446	rc = ata_pci_device_do_resume(dev);
447	if (rc)
448		return rc;
449	hpt36x_init_chipset(dev);
450	ata_host_resume(host);
451	return 0;
452}
453#endif
454
455static const struct pci_device_id hpt36x[] = {
456	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
457	{ },
458};
459
460static struct pci_driver hpt36x_pci_driver = {
461	.name 		= DRV_NAME,
462	.id_table	= hpt36x,
463	.probe 		= hpt36x_init_one,
464	.remove		= ata_pci_remove_one,
465#ifdef CONFIG_PM
466	.suspend	= ata_pci_device_suspend,
467	.resume		= hpt36x_reinit_one,
468#endif
469};
470
471static int __init hpt36x_init(void)
472{
473	return pci_register_driver(&hpt36x_pci_driver);
474}
475
476static void __exit hpt36x_exit(void)
477{
478	pci_unregister_driver(&hpt36x_pci_driver);
479}
480
481MODULE_AUTHOR("Alan Cox");
482MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
483MODULE_LICENSE("GPL");
484MODULE_DEVICE_TABLE(pci, hpt36x);
485MODULE_VERSION(DRV_VERSION);
486
487module_init(hpt36x_init);
488module_exit(hpt36x_exit);
489