pata_sil680.c revision 2fc75da0c59634b81223af497c4a037822f6e457
1/* 2 * pata_sil680.c - SIL680 PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * 5 * based upon 6 * 7 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 8 * 9 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 10 * Copyright (C) 2003 Red Hat <alan@redhat.com> 11 * 12 * May be copied or modified under the terms of the GNU General Public License 13 * 14 * Documentation publicly available. 15 * 16 * If you have strange problems with nVidia chipset systems please 17 * see the SI support documentation and update your system BIOS 18 * if necessary 19 * 20 * TODO 21 * If we know all our devices are LBA28 (or LBA28 sized) we could use 22 * the command fifo mode. 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/init.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <scsi/scsi_host.h> 32#include <linux/libata.h> 33 34#define DRV_NAME "pata_sil680" 35#define DRV_VERSION "0.4.9" 36 37#define SIL680_MMIO_BAR 5 38 39/** 40 * sil680_selreg - return register base 41 * @ap: ATA interface 42 * @r: config offset 43 * 44 * Turn a config register offset into the right address in PCI space 45 * to access the control register in question. 46 * 47 * Thankfully this is a configuration operation so isn't performance 48 * criticial. 49 */ 50 51static unsigned long sil680_selreg(struct ata_port *ap, int r) 52{ 53 unsigned long base = 0xA0 + r; 54 base += (ap->port_no << 4); 55 return base; 56} 57 58/** 59 * sil680_seldev - return register base 60 * @ap: ATA interface 61 * @r: config offset 62 * 63 * Turn a config register offset into the right address in PCI space 64 * to access the control register in question including accounting for 65 * the unit shift. 66 */ 67 68static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) 69{ 70 unsigned long base = 0xA0 + r; 71 base += (ap->port_no << 4); 72 base |= adev->devno ? 2 : 0; 73 return base; 74} 75 76 77/** 78 * sil680_cable_detect - cable detection 79 * @ap: ATA port 80 * 81 * Perform cable detection. The SIL680 stores this in PCI config 82 * space for us. 83 */ 84 85static int sil680_cable_detect(struct ata_port *ap) 86{ 87 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 88 unsigned long addr = sil680_selreg(ap, 0); 89 u8 ata66; 90 pci_read_config_byte(pdev, addr, &ata66); 91 if (ata66 & 1) 92 return ATA_CBL_PATA80; 93 else 94 return ATA_CBL_PATA40; 95} 96 97/** 98 * sil680_set_piomode - set PIO mode data 99 * @ap: ATA interface 100 * @adev: ATA device 101 * 102 * Program the SIL680 registers for PIO mode. Note that the task speed 103 * registers are shared between the devices so we must pick the lowest 104 * mode for command work. 105 */ 106 107static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) 108{ 109 static const u16 speed_p[5] = { 110 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 111 }; 112 static const u16 speed_t[5] = { 113 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 114 }; 115 116 unsigned long tfaddr = sil680_selreg(ap, 0x02); 117 unsigned long addr = sil680_seldev(ap, adev, 0x04); 118 unsigned long addr_mask = 0x80 + 4 * ap->port_no; 119 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 120 int pio = adev->pio_mode - XFER_PIO_0; 121 int lowest_pio = pio; 122 int port_shift = 4 * adev->devno; 123 u16 reg; 124 u8 mode; 125 126 struct ata_device *pair = ata_dev_pair(adev); 127 128 if (pair != NULL && adev->pio_mode > pair->pio_mode) 129 lowest_pio = pair->pio_mode - XFER_PIO_0; 130 131 pci_write_config_word(pdev, addr, speed_p[pio]); 132 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); 133 134 pci_read_config_word(pdev, tfaddr-2, ®); 135 pci_read_config_byte(pdev, addr_mask, &mode); 136 137 reg &= ~0x0200; /* Clear IORDY */ 138 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ 139 140 if (ata_pio_need_iordy(adev)) { 141 reg |= 0x0200; /* Enable IORDY */ 142 mode |= 1 << port_shift; 143 } 144 pci_write_config_word(pdev, tfaddr-2, reg); 145 pci_write_config_byte(pdev, addr_mask, mode); 146} 147 148/** 149 * sil680_set_dmamode - set DMA mode data 150 * @ap: ATA interface 151 * @adev: ATA device 152 * 153 * Program the MWDMA/UDMA modes for the sil680 chipset. 154 * 155 * The MWDMA mode values are pulled from a lookup table 156 * while the chipset uses mode number for UDMA. 157 */ 158 159static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) 160{ 161 static const u8 ultra_table[2][7] = { 162 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ 163 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ 164 }; 165 static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; 166 167 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 168 unsigned long ma = sil680_seldev(ap, adev, 0x08); 169 unsigned long ua = sil680_seldev(ap, adev, 0x0C); 170 unsigned long addr_mask = 0x80 + 4 * ap->port_no; 171 int port_shift = adev->devno * 4; 172 u8 scsc, mode; 173 u16 multi, ultra; 174 175 pci_read_config_byte(pdev, 0x8A, &scsc); 176 pci_read_config_byte(pdev, addr_mask, &mode); 177 pci_read_config_word(pdev, ma, &multi); 178 pci_read_config_word(pdev, ua, &ultra); 179 180 /* Mask timing bits */ 181 ultra &= ~0x3F; 182 mode &= ~(0x03 << port_shift); 183 184 /* Extract scsc */ 185 scsc = (scsc & 0x30) ? 1 : 0; 186 187 if (adev->dma_mode >= XFER_UDMA_0) { 188 multi = 0x10C1; 189 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; 190 mode |= (0x03 << port_shift); 191 } else { 192 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; 193 mode |= (0x02 << port_shift); 194 } 195 pci_write_config_byte(pdev, addr_mask, mode); 196 pci_write_config_word(pdev, ma, multi); 197 pci_write_config_word(pdev, ua, ultra); 198} 199 200/** 201 * sil680_sff_exec_command - issue ATA command to host controller 202 * @ap: port to which command is being issued 203 * @tf: ATA taskfile register set 204 * 205 * Issues ATA command, with proper synchronization with interrupt 206 * handler / other threads. Use our MMIO space for PCI posting to avoid 207 * a hideously slow cycle all the way to the device. 208 * 209 * LOCKING: 210 * spin_lock_irqsave(host lock) 211 */ 212static void sil680_sff_exec_command(struct ata_port *ap, 213 const struct ata_taskfile *tf) 214{ 215 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 216 iowrite8(tf->command, ap->ioaddr.command_addr); 217 ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 218} 219 220static bool sil680_sff_irq_check(struct ata_port *ap) 221{ 222 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 223 unsigned long addr = sil680_selreg(ap, 1); 224 u8 val; 225 226 pci_read_config_byte(pdev, addr, &val); 227 228 return val & 0x08; 229} 230 231static struct scsi_host_template sil680_sht = { 232 ATA_BMDMA_SHT(DRV_NAME), 233}; 234 235 236static struct ata_port_operations sil680_port_ops = { 237 .inherits = &ata_bmdma32_port_ops, 238 .sff_exec_command = sil680_sff_exec_command, 239 .sff_irq_check = sil680_sff_irq_check, 240 .cable_detect = sil680_cable_detect, 241 .set_piomode = sil680_set_piomode, 242 .set_dmamode = sil680_set_dmamode, 243}; 244 245/** 246 * sil680_init_chip - chip setup 247 * @pdev: PCI device 248 * 249 * Perform all the chip setup which must be done both when the device 250 * is powered up on boot and when we resume in case we resumed from RAM. 251 * Returns the final clock settings. 252 */ 253 254static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio) 255{ 256 u8 tmpbyte = 0; 257 258 /* FIXME: double check */ 259 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 260 pdev->revision ? 1 : 255); 261 262 pci_write_config_byte(pdev, 0x80, 0x00); 263 pci_write_config_byte(pdev, 0x84, 0x00); 264 265 pci_read_config_byte(pdev, 0x8A, &tmpbyte); 266 267 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 268 tmpbyte & 1, tmpbyte & 0x30); 269 270 *try_mmio = 0; 271#ifdef CONFIG_PPC 272 if (machine_is(cell)) 273 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5); 274#endif 275 276 switch (tmpbyte & 0x30) { 277 case 0x00: 278 /* 133 clock attempt to force it on */ 279 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); 280 break; 281 case 0x30: 282 /* if clocking is disabled */ 283 /* 133 clock attempt to force it on */ 284 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); 285 break; 286 case 0x10: 287 /* 133 already */ 288 break; 289 case 0x20: 290 /* BIOS set PCI x2 clocking */ 291 break; 292 } 293 294 pci_read_config_byte(pdev, 0x8A, &tmpbyte); 295 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 296 tmpbyte & 1, tmpbyte & 0x30); 297 298 pci_write_config_byte(pdev, 0xA1, 0x72); 299 pci_write_config_word(pdev, 0xA2, 0x328A); 300 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); 301 pci_write_config_dword(pdev, 0xA8, 0x43924392); 302 pci_write_config_dword(pdev, 0xAC, 0x40094009); 303 pci_write_config_byte(pdev, 0xB1, 0x72); 304 pci_write_config_word(pdev, 0xB2, 0x328A); 305 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); 306 pci_write_config_dword(pdev, 0xB8, 0x43924392); 307 pci_write_config_dword(pdev, 0xBC, 0x40094009); 308 309 switch (tmpbyte & 0x30) { 310 case 0x00: 311 printk(KERN_INFO "sil680: 100MHz clock.\n"); 312 break; 313 case 0x10: 314 printk(KERN_INFO "sil680: 133MHz clock.\n"); 315 break; 316 case 0x20: 317 printk(KERN_INFO "sil680: Using PCI clock.\n"); 318 break; 319 /* This last case is _NOT_ ok */ 320 case 0x30: 321 printk(KERN_ERR "sil680: Clock disabled ?\n"); 322 } 323 return tmpbyte & 0x30; 324} 325 326static int __devinit sil680_init_one(struct pci_dev *pdev, 327 const struct pci_device_id *id) 328{ 329 static const struct ata_port_info info = { 330 .flags = ATA_FLAG_SLAVE_POSS, 331 .pio_mask = ATA_PIO4, 332 .mwdma_mask = ATA_MWDMA2, 333 .udma_mask = ATA_UDMA6, 334 .port_ops = &sil680_port_ops 335 }; 336 static const struct ata_port_info info_slow = { 337 .flags = ATA_FLAG_SLAVE_POSS, 338 .pio_mask = ATA_PIO4, 339 .mwdma_mask = ATA_MWDMA2, 340 .udma_mask = ATA_UDMA5, 341 .port_ops = &sil680_port_ops 342 }; 343 const struct ata_port_info *ppi[] = { &info, NULL }; 344 struct ata_host *host; 345 void __iomem *mmio_base; 346 int rc, try_mmio; 347 348 ata_print_version_once(&pdev->dev, DRV_VERSION); 349 350 rc = pcim_enable_device(pdev); 351 if (rc) 352 return rc; 353 354 switch (sil680_init_chip(pdev, &try_mmio)) { 355 case 0: 356 ppi[0] = &info_slow; 357 break; 358 case 0x30: 359 return -ENODEV; 360 } 361 362 if (!try_mmio) 363 goto use_ioports; 364 365 /* Try to acquire MMIO resources and fallback to PIO if 366 * that fails 367 */ 368 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); 369 if (rc) 370 goto use_ioports; 371 372 /* Allocate host and set it up */ 373 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 374 if (!host) 375 return -ENOMEM; 376 host->iomap = pcim_iomap_table(pdev); 377 378 /* Setup DMA masks */ 379 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 380 if (rc) 381 return rc; 382 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 383 if (rc) 384 return rc; 385 pci_set_master(pdev); 386 387 /* Get MMIO base and initialize port addresses */ 388 mmio_base = host->iomap[SIL680_MMIO_BAR]; 389 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; 390 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; 391 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; 392 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; 393 ata_sff_std_ports(&host->ports[0]->ioaddr); 394 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; 395 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; 396 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; 397 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; 398 ata_sff_std_ports(&host->ports[1]->ioaddr); 399 400 /* Register & activate */ 401 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 402 IRQF_SHARED, &sil680_sht); 403 404use_ioports: 405 return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0); 406} 407 408#ifdef CONFIG_PM 409static int sil680_reinit_one(struct pci_dev *pdev) 410{ 411 struct ata_host *host = dev_get_drvdata(&pdev->dev); 412 int try_mmio, rc; 413 414 rc = ata_pci_device_do_resume(pdev); 415 if (rc) 416 return rc; 417 sil680_init_chip(pdev, &try_mmio); 418 ata_host_resume(host); 419 return 0; 420} 421#endif 422 423static const struct pci_device_id sil680[] = { 424 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, 425 426 { }, 427}; 428 429static struct pci_driver sil680_pci_driver = { 430 .name = DRV_NAME, 431 .id_table = sil680, 432 .probe = sil680_init_one, 433 .remove = ata_pci_remove_one, 434#ifdef CONFIG_PM 435 .suspend = ata_pci_device_suspend, 436 .resume = sil680_reinit_one, 437#endif 438}; 439 440module_pci_driver(sil680_pci_driver); 441 442MODULE_AUTHOR("Alan Cox"); 443MODULE_DESCRIPTION("low-level driver for SI680 PATA"); 444MODULE_LICENSE("GPL"); 445MODULE_DEVICE_TABLE(pci, sil680); 446MODULE_VERSION(DRV_VERSION); 447