pata_sil680.c revision f20b16ff7c19d1c369ee07470952aca093551ed0 
1/*
2 * pata_sil680.c 	- SIL680 PATA for new ATA layer
3 *			  (C) 2005 Red Hat Inc
4 *			  Alan Cox <alan@redhat.com>
5 *
6 * based upon
7 *
8 * linux/drivers/ide/pci/siimage.c		Version 1.07	Nov 30, 2003
9 *
10 * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003		Red Hat <alan@redhat.com>
12 *
13 *  May be copied or modified under the terms of the GNU General Public License
14 *
15 *  Documentation publically available.
16 *
17 *	If you have strange problems with nVidia chipset systems please
18 *	see the SI support documentation and update your system BIOS
19 *	if neccessary
20 *
21 * TODO
22 *	If we know all our devices are LBA28 (or LBA28 sized)  we could use
23 *	the command fifo mode.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34
35#define DRV_NAME "pata_sil680"
36#define DRV_VERSION "0.4.1"
37
38/**
39 *	sil680_selreg		-	return register base
40 *	@hwif: interface
41 *	@r: config offset
42 *
43 *	Turn a config register offset into the right address in either
44 *	PCI space or MMIO space to access the control register in question
45 *	Thankfully this is a configuration operation so isnt performance
46 *	criticial.
47 */
48
49static unsigned long sil680_selreg(struct ata_port *ap, int r)
50{
51	unsigned long base = 0xA0 + r;
52	base += (ap->port_no << 4);
53	return base;
54}
55
56/**
57 *	sil680_seldev		-	return register base
58 *	@hwif: interface
59 *	@r: config offset
60 *
61 *	Turn a config register offset into the right address in either
62 *	PCI space or MMIO space to access the control register in question
63 *	including accounting for the unit shift.
64 */
65
66static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
67{
68	unsigned long base = 0xA0 + r;
69	base += (ap->port_no << 4);
70	base |= adev->devno ? 2 : 0;
71	return base;
72}
73
74
75/**
76 *	sil680_cable_detect	-	cable detection
77 *	@ap: ATA port
78 *
79 *	Perform cable detection. The SIL680 stores this in PCI config
80 *	space for us.
81 */
82
83static int sil680_cable_detect(struct ata_port *ap) {
84	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85	unsigned long addr = sil680_selreg(ap, 0);
86	u8 ata66;
87	pci_read_config_byte(pdev, addr, &ata66);
88	if (ata66 & 1)
89		return ATA_CBL_PATA80;
90	else
91		return ATA_CBL_PATA40;
92}
93
94static int sil680_pre_reset(struct ata_port *ap)
95{
96	ap->cbl = sil680_cable_detect(ap);
97	return ata_std_prereset(ap);
98}
99
100/**
101 *	sil680_bus_reset	-	reset the SIL680 bus
102 *	@ap: ATA port to reset
103 *
104 *	Perform the SIL680 housekeeping when doing an ATA bus reset
105 */
106
107static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
108{
109	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
110	unsigned long addr = sil680_selreg(ap, 0);
111	u8 reset;
112
113	pci_read_config_byte(pdev, addr, &reset);
114	pci_write_config_byte(pdev, addr, reset | 0x03);
115	udelay(25);
116	pci_write_config_byte(pdev, addr, reset);
117	return ata_std_softreset(ap, classes);
118}
119
120static void sil680_error_handler(struct ata_port *ap)
121{
122	ata_bmdma_drive_eh(ap, sil680_pre_reset, sil680_bus_reset, NULL, ata_std_postreset);
123}
124
125/**
126 *	sil680_set_piomode	-	set initial PIO mode data
127 *	@ap: ATA interface
128 *	@adev: ATA device
129 *
130 *	Program the SIL680 registers for PIO mode. Note that the task speed
131 *	registers are shared between the devices so we must pick the lowest
132 *	mode for command work.
133 */
134
135static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
136{
137	static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
138	static u16 speed_t[5] = { 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 };
139
140	unsigned long tfaddr = sil680_selreg(ap, 0x02);
141	unsigned long addr = sil680_seldev(ap, adev, 0x04);
142	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
143	int pio = adev->pio_mode - XFER_PIO_0;
144	int lowest_pio = pio;
145	u16 reg;
146
147	struct ata_device *pair = ata_dev_pair(adev);
148
149	if (pair != NULL && adev->pio_mode > pair->pio_mode)
150		lowest_pio = pair->pio_mode - XFER_PIO_0;
151
152	pci_write_config_word(pdev, addr, speed_p[pio]);
153	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
154
155	pci_read_config_word(pdev, tfaddr-2, &reg);
156	reg &= ~0x0200;			/* Clear IORDY */
157	if (ata_pio_need_iordy(adev))
158		reg |= 0x0200;		/* Enable IORDY */
159	pci_write_config_word(pdev, tfaddr-2, reg);
160}
161
162/**
163 *	sil680_set_dmamode	-	set initial DMA mode data
164 *	@ap: ATA interface
165 *	@adev: ATA device
166 *
167 *	Program the MWDMA/UDMA modes for the sil680 k
168 *	chipset. The MWDMA mode values are pulled from a lookup table
169 *	while the chipset uses mode number for UDMA.
170 */
171
172static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
173{
174	static u8 ultra_table[2][7] = {
175		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */
176		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */
177	};
178	static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
179
180	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
181	unsigned long ma = sil680_seldev(ap, adev, 0x08);
182	unsigned long ua = sil680_seldev(ap, adev, 0x0C);
183	unsigned long addr_mask = 0x80 + 4 * ap->port_no;
184	int port_shift = adev->devno * 4;
185	u8 scsc, mode;
186	u16 multi, ultra;
187
188	pci_read_config_byte(pdev, 0x8A, &scsc);
189	pci_read_config_byte(pdev, addr_mask, &mode);
190	pci_read_config_word(pdev, ma, &multi);
191	pci_read_config_word(pdev, ua, &ultra);
192
193	/* Mask timing bits */
194	ultra &= ~0x3F;
195	mode &= ~(0x03 << port_shift);
196
197	/* Extract scsc */
198	scsc = (scsc & 0x30) ? 1: 0;
199
200	if (adev->dma_mode >= XFER_UDMA_0) {
201		multi = 0x10C1;
202		ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
203		mode |= (0x03 << port_shift);
204	} else {
205		multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
206		mode |= (0x02 << port_shift);
207	}
208	pci_write_config_byte(pdev, addr_mask, mode);
209	pci_write_config_word(pdev, ma, multi);
210	pci_write_config_word(pdev, ua, ultra);
211}
212
213static struct scsi_host_template sil680_sht = {
214	.module			= THIS_MODULE,
215	.name			= DRV_NAME,
216	.ioctl			= ata_scsi_ioctl,
217	.queuecommand		= ata_scsi_queuecmd,
218	.can_queue		= ATA_DEF_QUEUE,
219	.this_id		= ATA_SHT_THIS_ID,
220	.sg_tablesize		= LIBATA_MAX_PRD,
221	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
222	.emulated		= ATA_SHT_EMULATED,
223	.use_clustering		= ATA_SHT_USE_CLUSTERING,
224	.proc_name		= DRV_NAME,
225	.dma_boundary		= ATA_DMA_BOUNDARY,
226	.slave_configure	= ata_scsi_slave_config,
227	.slave_destroy		= ata_scsi_slave_destroy,
228	.bios_param		= ata_std_bios_param,
229};
230
231static struct ata_port_operations sil680_port_ops = {
232	.port_disable	= ata_port_disable,
233	.set_piomode	= sil680_set_piomode,
234	.set_dmamode	= sil680_set_dmamode,
235	.mode_filter	= ata_pci_default_filter,
236	.tf_load	= ata_tf_load,
237	.tf_read	= ata_tf_read,
238	.check_status 	= ata_check_status,
239	.exec_command	= ata_exec_command,
240	.dev_select 	= ata_std_dev_select,
241
242	.freeze		= ata_bmdma_freeze,
243	.thaw		= ata_bmdma_thaw,
244	.error_handler	= sil680_error_handler,
245	.post_internal_cmd = ata_bmdma_post_internal_cmd,
246
247	.bmdma_setup 	= ata_bmdma_setup,
248	.bmdma_start 	= ata_bmdma_start,
249	.bmdma_stop	= ata_bmdma_stop,
250	.bmdma_status 	= ata_bmdma_status,
251
252	.qc_prep 	= ata_qc_prep,
253	.qc_issue	= ata_qc_issue_prot,
254
255	.data_xfer	= ata_pio_data_xfer,
256
257	.irq_handler	= ata_interrupt,
258	.irq_clear	= ata_bmdma_irq_clear,
259
260	.port_start	= ata_port_start,
261	.port_stop	= ata_port_stop,
262	.host_stop	= ata_host_stop
263};
264
265/**
266 *	sil680_init_chip		-	chip setup
267 *	@pdev: PCI device
268 *
269 *	Perform all the chip setup which must be done both when the device
270 *	is powered up on boot and when we resume in case we resumed from RAM.
271 *	Returns the final clock settings.
272 */
273
274static u8 sil680_init_chip(struct pci_dev *pdev)
275{
276	u32 class_rev	= 0;
277	u8 tmpbyte	= 0;
278
279        pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
280        class_rev &= 0xff;
281        /* FIXME: double check */
282	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
283
284	pci_write_config_byte(pdev, 0x80, 0x00);
285	pci_write_config_byte(pdev, 0x84, 0x00);
286
287	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
288
289	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
290			tmpbyte & 1, tmpbyte & 0x30);
291
292	switch(tmpbyte & 0x30) {
293		case 0x00:
294			/* 133 clock attempt to force it on */
295			pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
296			break;
297		case 0x30:
298			/* if clocking is disabled */
299			/* 133 clock attempt to force it on */
300			pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
301			break;
302		case 0x10:
303			/* 133 already */
304			break;
305		case 0x20:
306			/* BIOS set PCI x2 clocking */
307			break;
308	}
309
310	pci_read_config_byte(pdev,   0x8A, &tmpbyte);
311	printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
312			tmpbyte & 1, tmpbyte & 0x30);
313
314	pci_write_config_byte(pdev,  0xA1, 0x72);
315	pci_write_config_word(pdev,  0xA2, 0x328A);
316	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
317	pci_write_config_dword(pdev, 0xA8, 0x43924392);
318	pci_write_config_dword(pdev, 0xAC, 0x40094009);
319	pci_write_config_byte(pdev,  0xB1, 0x72);
320	pci_write_config_word(pdev,  0xB2, 0x328A);
321	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
322	pci_write_config_dword(pdev, 0xB8, 0x43924392);
323	pci_write_config_dword(pdev, 0xBC, 0x40094009);
324
325	switch(tmpbyte & 0x30) {
326		case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
327		case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
328		case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
329		/* This last case is _NOT_ ok */
330		case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
331	}
332	return tmpbyte & 0x30;
333}
334
335static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
336{
337	static struct ata_port_info info = {
338		.sht = &sil680_sht,
339		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
340		.pio_mask = 0x1f,
341		.mwdma_mask = 0x07,
342		.udma_mask = 0x7f,
343		.port_ops = &sil680_port_ops
344	};
345	static struct ata_port_info info_slow = {
346		.sht = &sil680_sht,
347		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
348		.pio_mask = 0x1f,
349		.mwdma_mask = 0x07,
350		.udma_mask = 0x3f,
351		.port_ops = &sil680_port_ops
352	};
353	static struct ata_port_info *port_info[2] = {&info, &info};
354	static int printed_version;
355
356	if (!printed_version++)
357		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
358
359	switch(sil680_init_chip(pdev))
360	{
361		case 0:
362			port_info[0] = port_info[1] = &info_slow;
363			break;
364		case 0x30:
365			return -ENODEV;
366	}
367	return ata_pci_init_one(pdev, port_info, 2);
368}
369
370static int sil680_reinit_one(struct pci_dev *pdev)
371{
372	sil680_init_chip(pdev);
373	return ata_pci_device_resume(pdev);
374}
375
376static const struct pci_device_id sil680[] = {
377	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
378
379	{ },
380};
381
382static struct pci_driver sil680_pci_driver = {
383	.name 		= DRV_NAME,
384	.id_table	= sil680,
385	.probe 		= sil680_init_one,
386	.remove		= ata_pci_remove_one,
387	.suspend	= ata_pci_device_suspend,
388	.resume		= sil680_reinit_one,
389};
390
391static int __init sil680_init(void)
392{
393	return pci_register_driver(&sil680_pci_driver);
394}
395
396static void __exit sil680_exit(void)
397{
398	pci_unregister_driver(&sil680_pci_driver);
399}
400
401MODULE_AUTHOR("Alan Cox");
402MODULE_DESCRIPTION("low-level driver for SI680 PATA");
403MODULE_LICENSE("GPL");
404MODULE_DEVICE_TABLE(pci, sil680);
405MODULE_VERSION(DRV_VERSION);
406
407module_init(sil680_init);
408module_exit(sil680_exit);
409