idt77252.c revision 4305b541357ddbd205aa145dc378926b7cb12283
1/******************************************************************* 2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $" 3 * 4 * $Author: ecd $ 5 * $Date: 2001/11/11 08:13:54 $ 6 * 7 * Copyright (c) 2000 ATecoM GmbH 8 * 9 * The author may be reached at ecd@atecom.com. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 *******************************************************************/ 32static char const rcsid[] = 33"$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"; 34 35 36#include <linux/module.h> 37#include <linux/pci.h> 38#include <linux/poison.h> 39#include <linux/skbuff.h> 40#include <linux/kernel.h> 41#include <linux/vmalloc.h> 42#include <linux/netdevice.h> 43#include <linux/atmdev.h> 44#include <linux/atm.h> 45#include <linux/delay.h> 46#include <linux/init.h> 47#include <linux/bitops.h> 48#include <linux/wait.h> 49#include <linux/jiffies.h> 50#include <asm/semaphore.h> 51#include <asm/io.h> 52#include <asm/uaccess.h> 53#include <asm/atomic.h> 54#include <asm/byteorder.h> 55 56#ifdef CONFIG_ATM_IDT77252_USE_SUNI 57#include "suni.h" 58#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 59 60 61#include "idt77252.h" 62#include "idt77252_tables.h" 63 64static unsigned int vpibits = 1; 65 66 67#define CONFIG_ATM_IDT77252_SEND_IDLE 1 68 69 70/* 71 * Debug HACKs. 72 */ 73#define DEBUG_MODULE 1 74#undef HAVE_EEPROM /* does not work, yet. */ 75 76#ifdef CONFIG_ATM_IDT77252_DEBUG 77static unsigned long debug = DBG_GENERAL; 78#endif 79 80 81#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 82 83 84/* 85 * SCQ Handling. 86 */ 87static struct scq_info *alloc_scq(struct idt77252_dev *, int); 88static void free_scq(struct idt77252_dev *, struct scq_info *); 89static int queue_skb(struct idt77252_dev *, struct vc_map *, 90 struct sk_buff *, int oam); 91static void drain_scq(struct idt77252_dev *, struct vc_map *); 92static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 93static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 94 95/* 96 * FBQ Handling. 97 */ 98static int push_rx_skb(struct idt77252_dev *, 99 struct sk_buff *, int queue); 100static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 101static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 102static void recycle_rx_pool_skb(struct idt77252_dev *, 103 struct rx_pool *); 104static void add_rx_skb(struct idt77252_dev *, int queue, 105 unsigned int size, unsigned int count); 106 107/* 108 * RSQ Handling. 109 */ 110static int init_rsq(struct idt77252_dev *); 111static void deinit_rsq(struct idt77252_dev *); 112static void idt77252_rx(struct idt77252_dev *); 113 114/* 115 * TSQ handling. 116 */ 117static int init_tsq(struct idt77252_dev *); 118static void deinit_tsq(struct idt77252_dev *); 119static void idt77252_tx(struct idt77252_dev *); 120 121 122/* 123 * ATM Interface. 124 */ 125static void idt77252_dev_close(struct atm_dev *dev); 126static int idt77252_open(struct atm_vcc *vcc); 127static void idt77252_close(struct atm_vcc *vcc); 128static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 129static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 130 int flags); 131static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 132 unsigned long addr); 133static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 134static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 135 int flags); 136static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 137 char *page); 138static void idt77252_softint(struct work_struct *work); 139 140 141static struct atmdev_ops idt77252_ops = 142{ 143 .dev_close = idt77252_dev_close, 144 .open = idt77252_open, 145 .close = idt77252_close, 146 .send = idt77252_send, 147 .send_oam = idt77252_send_oam, 148 .phy_put = idt77252_phy_put, 149 .phy_get = idt77252_phy_get, 150 .change_qos = idt77252_change_qos, 151 .proc_read = idt77252_proc_read, 152 .owner = THIS_MODULE 153}; 154 155static struct idt77252_dev *idt77252_chain = NULL; 156static unsigned int idt77252_sram_write_errors = 0; 157 158/*****************************************************************************/ 159/* */ 160/* I/O and Utility Bus */ 161/* */ 162/*****************************************************************************/ 163 164static void 165waitfor_idle(struct idt77252_dev *card) 166{ 167 u32 stat; 168 169 stat = readl(SAR_REG_STAT); 170 while (stat & SAR_STAT_CMDBZ) 171 stat = readl(SAR_REG_STAT); 172} 173 174static u32 175read_sram(struct idt77252_dev *card, unsigned long addr) 176{ 177 unsigned long flags; 178 u32 value; 179 180 spin_lock_irqsave(&card->cmd_lock, flags); 181 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 182 waitfor_idle(card); 183 value = readl(SAR_REG_DR0); 184 spin_unlock_irqrestore(&card->cmd_lock, flags); 185 return value; 186} 187 188static void 189write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 190{ 191 unsigned long flags; 192 193 if ((idt77252_sram_write_errors == 0) && 194 (((addr > card->tst[0] + card->tst_size - 2) && 195 (addr < card->tst[0] + card->tst_size)) || 196 ((addr > card->tst[1] + card->tst_size - 2) && 197 (addr < card->tst[1] + card->tst_size)))) { 198 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 199 card->name, addr, value); 200 } 201 202 spin_lock_irqsave(&card->cmd_lock, flags); 203 writel(value, SAR_REG_DR0); 204 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 205 waitfor_idle(card); 206 spin_unlock_irqrestore(&card->cmd_lock, flags); 207} 208 209static u8 210read_utility(void *dev, unsigned long ubus_addr) 211{ 212 struct idt77252_dev *card = dev; 213 unsigned long flags; 214 u8 value; 215 216 if (!card) { 217 printk("Error: No such device.\n"); 218 return -1; 219 } 220 221 spin_lock_irqsave(&card->cmd_lock, flags); 222 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 223 waitfor_idle(card); 224 value = readl(SAR_REG_DR0); 225 spin_unlock_irqrestore(&card->cmd_lock, flags); 226 return value; 227} 228 229static void 230write_utility(void *dev, unsigned long ubus_addr, u8 value) 231{ 232 struct idt77252_dev *card = dev; 233 unsigned long flags; 234 235 if (!card) { 236 printk("Error: No such device.\n"); 237 return; 238 } 239 240 spin_lock_irqsave(&card->cmd_lock, flags); 241 writel((u32) value, SAR_REG_DR0); 242 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 243 waitfor_idle(card); 244 spin_unlock_irqrestore(&card->cmd_lock, flags); 245} 246 247#ifdef HAVE_EEPROM 248static u32 rdsrtab[] = 249{ 250 SAR_GP_EECS | SAR_GP_EESCLK, 251 0, 252 SAR_GP_EESCLK, /* 0 */ 253 0, 254 SAR_GP_EESCLK, /* 0 */ 255 0, 256 SAR_GP_EESCLK, /* 0 */ 257 0, 258 SAR_GP_EESCLK, /* 0 */ 259 0, 260 SAR_GP_EESCLK, /* 0 */ 261 SAR_GP_EEDO, 262 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 263 0, 264 SAR_GP_EESCLK, /* 0 */ 265 SAR_GP_EEDO, 266 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 267}; 268 269static u32 wrentab[] = 270{ 271 SAR_GP_EECS | SAR_GP_EESCLK, 272 0, 273 SAR_GP_EESCLK, /* 0 */ 274 0, 275 SAR_GP_EESCLK, /* 0 */ 276 0, 277 SAR_GP_EESCLK, /* 0 */ 278 0, 279 SAR_GP_EESCLK, /* 0 */ 280 SAR_GP_EEDO, 281 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 282 SAR_GP_EEDO, 283 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 284 0, 285 SAR_GP_EESCLK, /* 0 */ 286 0, 287 SAR_GP_EESCLK /* 0 */ 288}; 289 290static u32 rdtab[] = 291{ 292 SAR_GP_EECS | SAR_GP_EESCLK, 293 0, 294 SAR_GP_EESCLK, /* 0 */ 295 0, 296 SAR_GP_EESCLK, /* 0 */ 297 0, 298 SAR_GP_EESCLK, /* 0 */ 299 0, 300 SAR_GP_EESCLK, /* 0 */ 301 0, 302 SAR_GP_EESCLK, /* 0 */ 303 0, 304 SAR_GP_EESCLK, /* 0 */ 305 SAR_GP_EEDO, 306 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 307 SAR_GP_EEDO, 308 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 309}; 310 311static u32 wrtab[] = 312{ 313 SAR_GP_EECS | SAR_GP_EESCLK, 314 0, 315 SAR_GP_EESCLK, /* 0 */ 316 0, 317 SAR_GP_EESCLK, /* 0 */ 318 0, 319 SAR_GP_EESCLK, /* 0 */ 320 0, 321 SAR_GP_EESCLK, /* 0 */ 322 0, 323 SAR_GP_EESCLK, /* 0 */ 324 0, 325 SAR_GP_EESCLK, /* 0 */ 326 SAR_GP_EEDO, 327 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 328 0, 329 SAR_GP_EESCLK /* 0 */ 330}; 331 332static u32 clktab[] = 333{ 334 0, 335 SAR_GP_EESCLK, 336 0, 337 SAR_GP_EESCLK, 338 0, 339 SAR_GP_EESCLK, 340 0, 341 SAR_GP_EESCLK, 342 0, 343 SAR_GP_EESCLK, 344 0, 345 SAR_GP_EESCLK, 346 0, 347 SAR_GP_EESCLK, 348 0, 349 SAR_GP_EESCLK, 350 0 351}; 352 353static u32 354idt77252_read_gp(struct idt77252_dev *card) 355{ 356 u32 gp; 357 358 gp = readl(SAR_REG_GP); 359#if 0 360 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 361#endif 362 return gp; 363} 364 365static void 366idt77252_write_gp(struct idt77252_dev *card, u32 value) 367{ 368 unsigned long flags; 369 370#if 0 371 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 372 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 373 value & SAR_GP_EEDO ? "1" : "0"); 374#endif 375 376 spin_lock_irqsave(&card->cmd_lock, flags); 377 waitfor_idle(card); 378 writel(value, SAR_REG_GP); 379 spin_unlock_irqrestore(&card->cmd_lock, flags); 380} 381 382static u8 383idt77252_eeprom_read_status(struct idt77252_dev *card) 384{ 385 u8 byte; 386 u32 gp; 387 int i, j; 388 389 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 390 391 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 392 idt77252_write_gp(card, gp | rdsrtab[i]); 393 udelay(5); 394 } 395 idt77252_write_gp(card, gp | SAR_GP_EECS); 396 udelay(5); 397 398 byte = 0; 399 for (i = 0, j = 0; i < 8; i++) { 400 byte <<= 1; 401 402 idt77252_write_gp(card, gp | clktab[j++]); 403 udelay(5); 404 405 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 406 407 idt77252_write_gp(card, gp | clktab[j++]); 408 udelay(5); 409 } 410 idt77252_write_gp(card, gp | SAR_GP_EECS); 411 udelay(5); 412 413 return byte; 414} 415 416static u8 417idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 418{ 419 u8 byte; 420 u32 gp; 421 int i, j; 422 423 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 424 425 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 426 idt77252_write_gp(card, gp | rdtab[i]); 427 udelay(5); 428 } 429 idt77252_write_gp(card, gp | SAR_GP_EECS); 430 udelay(5); 431 432 for (i = 0, j = 0; i < 8; i++) { 433 idt77252_write_gp(card, gp | clktab[j++] | 434 (offset & 1 ? SAR_GP_EEDO : 0)); 435 udelay(5); 436 437 idt77252_write_gp(card, gp | clktab[j++] | 438 (offset & 1 ? SAR_GP_EEDO : 0)); 439 udelay(5); 440 441 offset >>= 1; 442 } 443 idt77252_write_gp(card, gp | SAR_GP_EECS); 444 udelay(5); 445 446 byte = 0; 447 for (i = 0, j = 0; i < 8; i++) { 448 byte <<= 1; 449 450 idt77252_write_gp(card, gp | clktab[j++]); 451 udelay(5); 452 453 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 454 455 idt77252_write_gp(card, gp | clktab[j++]); 456 udelay(5); 457 } 458 idt77252_write_gp(card, gp | SAR_GP_EECS); 459 udelay(5); 460 461 return byte; 462} 463 464static void 465idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 466{ 467 u32 gp; 468 int i, j; 469 470 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 471 472 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 473 idt77252_write_gp(card, gp | wrentab[i]); 474 udelay(5); 475 } 476 idt77252_write_gp(card, gp | SAR_GP_EECS); 477 udelay(5); 478 479 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 480 idt77252_write_gp(card, gp | wrtab[i]); 481 udelay(5); 482 } 483 idt77252_write_gp(card, gp | SAR_GP_EECS); 484 udelay(5); 485 486 for (i = 0, j = 0; i < 8; i++) { 487 idt77252_write_gp(card, gp | clktab[j++] | 488 (offset & 1 ? SAR_GP_EEDO : 0)); 489 udelay(5); 490 491 idt77252_write_gp(card, gp | clktab[j++] | 492 (offset & 1 ? SAR_GP_EEDO : 0)); 493 udelay(5); 494 495 offset >>= 1; 496 } 497 idt77252_write_gp(card, gp | SAR_GP_EECS); 498 udelay(5); 499 500 for (i = 0, j = 0; i < 8; i++) { 501 idt77252_write_gp(card, gp | clktab[j++] | 502 (data & 1 ? SAR_GP_EEDO : 0)); 503 udelay(5); 504 505 idt77252_write_gp(card, gp | clktab[j++] | 506 (data & 1 ? SAR_GP_EEDO : 0)); 507 udelay(5); 508 509 data >>= 1; 510 } 511 idt77252_write_gp(card, gp | SAR_GP_EECS); 512 udelay(5); 513} 514 515static void 516idt77252_eeprom_init(struct idt77252_dev *card) 517{ 518 u32 gp; 519 520 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 521 522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 523 udelay(5); 524 idt77252_write_gp(card, gp | SAR_GP_EECS); 525 udelay(5); 526 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 527 udelay(5); 528 idt77252_write_gp(card, gp | SAR_GP_EECS); 529 udelay(5); 530} 531#endif /* HAVE_EEPROM */ 532 533 534#ifdef CONFIG_ATM_IDT77252_DEBUG 535static void 536dump_tct(struct idt77252_dev *card, int index) 537{ 538 unsigned long tct; 539 int i; 540 541 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 542 543 printk("%s: TCT %x:", card->name, index); 544 for (i = 0; i < 8; i++) { 545 printk(" %08x", read_sram(card, tct + i)); 546 } 547 printk("\n"); 548} 549 550static void 551idt77252_tx_dump(struct idt77252_dev *card) 552{ 553 struct atm_vcc *vcc; 554 struct vc_map *vc; 555 int i; 556 557 printk("%s\n", __FUNCTION__); 558 for (i = 0; i < card->tct_size; i++) { 559 vc = card->vcs[i]; 560 if (!vc) 561 continue; 562 563 vcc = NULL; 564 if (vc->rx_vcc) 565 vcc = vc->rx_vcc; 566 else if (vc->tx_vcc) 567 vcc = vc->tx_vcc; 568 569 if (!vcc) 570 continue; 571 572 printk("%s: Connection %d:\n", card->name, vc->index); 573 dump_tct(card, vc->index); 574 } 575} 576#endif 577 578 579/*****************************************************************************/ 580/* */ 581/* SCQ Handling */ 582/* */ 583/*****************************************************************************/ 584 585static int 586sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 587{ 588 struct sb_pool *pool = &card->sbpool[queue]; 589 int index; 590 591 index = pool->index; 592 while (pool->skb[index]) { 593 index = (index + 1) & FBQ_MASK; 594 if (index == pool->index) 595 return -ENOBUFS; 596 } 597 598 pool->skb[index] = skb; 599 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 600 601 pool->index = (index + 1) & FBQ_MASK; 602 return 0; 603} 604 605static void 606sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 607{ 608 unsigned int queue, index; 609 u32 handle; 610 611 handle = IDT77252_PRV_POOL(skb); 612 613 queue = POOL_QUEUE(handle); 614 if (queue > 3) 615 return; 616 617 index = POOL_INDEX(handle); 618 if (index > FBQ_SIZE - 1) 619 return; 620 621 card->sbpool[queue].skb[index] = NULL; 622} 623 624static struct sk_buff * 625sb_pool_skb(struct idt77252_dev *card, u32 handle) 626{ 627 unsigned int queue, index; 628 629 queue = POOL_QUEUE(handle); 630 if (queue > 3) 631 return NULL; 632 633 index = POOL_INDEX(handle); 634 if (index > FBQ_SIZE - 1) 635 return NULL; 636 637 return card->sbpool[queue].skb[index]; 638} 639 640static struct scq_info * 641alloc_scq(struct idt77252_dev *card, int class) 642{ 643 struct scq_info *scq; 644 645 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 646 if (!scq) 647 return NULL; 648 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 649 &scq->paddr); 650 if (scq->base == NULL) { 651 kfree(scq); 652 return NULL; 653 } 654 memset(scq->base, 0, SCQ_SIZE); 655 656 scq->next = scq->base; 657 scq->last = scq->base + (SCQ_ENTRIES - 1); 658 atomic_set(&scq->used, 0); 659 660 spin_lock_init(&scq->lock); 661 spin_lock_init(&scq->skblock); 662 663 skb_queue_head_init(&scq->transmit); 664 skb_queue_head_init(&scq->pending); 665 666 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 667 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 668 669 return scq; 670} 671 672static void 673free_scq(struct idt77252_dev *card, struct scq_info *scq) 674{ 675 struct sk_buff *skb; 676 struct atm_vcc *vcc; 677 678 pci_free_consistent(card->pcidev, SCQ_SIZE, 679 scq->base, scq->paddr); 680 681 while ((skb = skb_dequeue(&scq->transmit))) { 682 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 683 skb->len, PCI_DMA_TODEVICE); 684 685 vcc = ATM_SKB(skb)->vcc; 686 if (vcc->pop) 687 vcc->pop(vcc, skb); 688 else 689 dev_kfree_skb(skb); 690 } 691 692 while ((skb = skb_dequeue(&scq->pending))) { 693 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 694 skb->len, PCI_DMA_TODEVICE); 695 696 vcc = ATM_SKB(skb)->vcc; 697 if (vcc->pop) 698 vcc->pop(vcc, skb); 699 else 700 dev_kfree_skb(skb); 701 } 702 703 kfree(scq); 704} 705 706 707static int 708push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 709{ 710 struct scq_info *scq = vc->scq; 711 unsigned long flags; 712 struct scqe *tbd; 713 int entries; 714 715 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 716 717 atomic_inc(&scq->used); 718 entries = atomic_read(&scq->used); 719 if (entries > (SCQ_ENTRIES - 1)) { 720 atomic_dec(&scq->used); 721 goto out; 722 } 723 724 skb_queue_tail(&scq->transmit, skb); 725 726 spin_lock_irqsave(&vc->lock, flags); 727 if (vc->estimator) { 728 struct atm_vcc *vcc = vc->tx_vcc; 729 struct sock *sk = sk_atm(vcc); 730 731 vc->estimator->cells += (skb->len + 47) / 48; 732 if (atomic_read(&sk->sk_wmem_alloc) > 733 (sk->sk_sndbuf >> 1)) { 734 u32 cps = vc->estimator->maxcps; 735 736 vc->estimator->cps = cps; 737 vc->estimator->avcps = cps << 5; 738 if (vc->lacr < vc->init_er) { 739 vc->lacr = vc->init_er; 740 writel(TCMDQ_LACR | (vc->lacr << 16) | 741 vc->index, SAR_REG_TCMDQ); 742 } 743 } 744 } 745 spin_unlock_irqrestore(&vc->lock, flags); 746 747 tbd = &IDT77252_PRV_TBD(skb); 748 749 spin_lock_irqsave(&scq->lock, flags); 750 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 751 SAR_TBD_TSIF | SAR_TBD_GTSI); 752 scq->next->word_2 = cpu_to_le32(tbd->word_2); 753 scq->next->word_3 = cpu_to_le32(tbd->word_3); 754 scq->next->word_4 = cpu_to_le32(tbd->word_4); 755 756 if (scq->next == scq->last) 757 scq->next = scq->base; 758 else 759 scq->next++; 760 761 write_sram(card, scq->scd, 762 scq->paddr + 763 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 764 spin_unlock_irqrestore(&scq->lock, flags); 765 766 scq->trans_start = jiffies; 767 768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 770 SAR_REG_TCMDQ); 771 } 772 773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 774 775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 776 card->name, atomic_read(&scq->used), 777 read_sram(card, scq->scd + 1), scq->next); 778 779 return 0; 780 781out: 782 if (time_after(jiffies, scq->trans_start + HZ)) { 783 printk("%s: Error pushing TBD for %d.%d\n", 784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 785#ifdef CONFIG_ATM_IDT77252_DEBUG 786 idt77252_tx_dump(card); 787#endif 788 scq->trans_start = jiffies; 789 } 790 791 return -ENOBUFS; 792} 793 794 795static void 796drain_scq(struct idt77252_dev *card, struct vc_map *vc) 797{ 798 struct scq_info *scq = vc->scq; 799 struct sk_buff *skb; 800 struct atm_vcc *vcc; 801 802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 803 card->name, atomic_read(&scq->used), scq->next); 804 805 skb = skb_dequeue(&scq->transmit); 806 if (skb) { 807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 808 809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 810 skb->len, PCI_DMA_TODEVICE); 811 812 vcc = ATM_SKB(skb)->vcc; 813 814 if (vcc->pop) 815 vcc->pop(vcc, skb); 816 else 817 dev_kfree_skb(skb); 818 819 atomic_inc(&vcc->stats->tx); 820 } 821 822 atomic_dec(&scq->used); 823 824 spin_lock(&scq->skblock); 825 while ((skb = skb_dequeue(&scq->pending))) { 826 if (push_on_scq(card, vc, skb)) { 827 skb_queue_head(&vc->scq->pending, skb); 828 break; 829 } 830 } 831 spin_unlock(&scq->skblock); 832} 833 834static int 835queue_skb(struct idt77252_dev *card, struct vc_map *vc, 836 struct sk_buff *skb, int oam) 837{ 838 struct atm_vcc *vcc; 839 struct scqe *tbd; 840 unsigned long flags; 841 int error; 842 int aal; 843 844 if (skb->len == 0) { 845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 846 return -EINVAL; 847 } 848 849 TXPRINTK("%s: Sending %d bytes of data.\n", 850 card->name, skb->len); 851 852 tbd = &IDT77252_PRV_TBD(skb); 853 vcc = ATM_SKB(skb)->vcc; 854 855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 856 skb->len, PCI_DMA_TODEVICE); 857 858 error = -EINVAL; 859 860 if (oam) { 861 if (skb->len != 52) 862 goto errout; 863 864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 866 tbd->word_3 = 0x00000000; 867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 868 (skb->data[2] << 8) | (skb->data[3] << 0); 869 870 if (test_bit(VCF_RSV, &vc->flags)) 871 vc = card->vcs[0]; 872 873 goto done; 874 } 875 876 if (test_bit(VCF_RSV, &vc->flags)) { 877 printk("%s: Trying to transmit on reserved VC\n", card->name); 878 goto errout; 879 } 880 881 aal = vcc->qos.aal; 882 883 switch (aal) { 884 case ATM_AAL0: 885 case ATM_AAL34: 886 if (skb->len > 52) 887 goto errout; 888 889 if (aal == ATM_AAL0) 890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 891 ATM_CELL_PAYLOAD; 892 else 893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 894 ATM_CELL_PAYLOAD; 895 896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 897 tbd->word_3 = 0x00000000; 898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 899 (skb->data[2] << 8) | (skb->data[3] << 0); 900 break; 901 902 case ATM_AAL5: 903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 904 tbd->word_2 = IDT77252_PRV_PADDR(skb); 905 tbd->word_3 = skb->len; 906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 907 (vcc->vci << SAR_TBD_VCI_SHIFT); 908 break; 909 910 case ATM_AAL1: 911 case ATM_AAL2: 912 default: 913 printk("%s: Traffic type not supported.\n", card->name); 914 error = -EPROTONOSUPPORT; 915 goto errout; 916 } 917 918done: 919 spin_lock_irqsave(&vc->scq->skblock, flags); 920 skb_queue_tail(&vc->scq->pending, skb); 921 922 while ((skb = skb_dequeue(&vc->scq->pending))) { 923 if (push_on_scq(card, vc, skb)) { 924 skb_queue_head(&vc->scq->pending, skb); 925 break; 926 } 927 } 928 spin_unlock_irqrestore(&vc->scq->skblock, flags); 929 930 return 0; 931 932errout: 933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 934 skb->len, PCI_DMA_TODEVICE); 935 return error; 936} 937 938static unsigned long 939get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 940{ 941 int i; 942 943 for (i = 0; i < card->scd_size; i++) { 944 if (!card->scd2vc[i]) { 945 card->scd2vc[i] = vc; 946 vc->scd_index = i; 947 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 948 } 949 } 950 return 0; 951} 952 953static void 954fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 955{ 956 write_sram(card, scq->scd, scq->paddr); 957 write_sram(card, scq->scd + 1, 0x00000000); 958 write_sram(card, scq->scd + 2, 0xffffffff); 959 write_sram(card, scq->scd + 3, 0x00000000); 960} 961 962static void 963clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 964{ 965 return; 966} 967 968/*****************************************************************************/ 969/* */ 970/* RSQ Handling */ 971/* */ 972/*****************************************************************************/ 973 974static int 975init_rsq(struct idt77252_dev *card) 976{ 977 struct rsq_entry *rsqe; 978 979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 980 &card->rsq.paddr); 981 if (card->rsq.base == NULL) { 982 printk("%s: can't allocate RSQ.\n", card->name); 983 return -1; 984 } 985 memset(card->rsq.base, 0, RSQSIZE); 986 987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 988 card->rsq.next = card->rsq.last; 989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 990 rsqe->word_4 = 0; 991 992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 993 SAR_REG_RSQH); 994 writel(card->rsq.paddr, SAR_REG_RSQB); 995 996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 997 (unsigned long) card->rsq.base, 998 readl(SAR_REG_RSQB)); 999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 1000 card->name, 1001 readl(SAR_REG_RSQH), 1002 readl(SAR_REG_RSQB), 1003 readl(SAR_REG_RSQT)); 1004 1005 return 0; 1006} 1007 1008static void 1009deinit_rsq(struct idt77252_dev *card) 1010{ 1011 pci_free_consistent(card->pcidev, RSQSIZE, 1012 card->rsq.base, card->rsq.paddr); 1013} 1014 1015static void 1016dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1017{ 1018 struct atm_vcc *vcc; 1019 struct sk_buff *skb; 1020 struct rx_pool *rpp; 1021 struct vc_map *vc; 1022 u32 header, vpi, vci; 1023 u32 stat; 1024 int i; 1025 1026 stat = le32_to_cpu(rsqe->word_4); 1027 1028 if (stat & SAR_RSQE_IDLE) { 1029 RXPRINTK("%s: message about inactive connection.\n", 1030 card->name); 1031 return; 1032 } 1033 1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1035 if (skb == NULL) { 1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1037 card->name, __FUNCTION__, 1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1040 return; 1041 } 1042 1043 header = le32_to_cpu(rsqe->word_1); 1044 vpi = (header >> 16) & 0x00ff; 1045 vci = (header >> 0) & 0xffff; 1046 1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1048 card->name, vpi, vci, skb, skb->data); 1049 1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1051 printk("%s: SDU received for out-of-range vc %u.%u\n", 1052 card->name, vpi, vci); 1053 recycle_rx_skb(card, skb); 1054 return; 1055 } 1056 1057 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1059 printk("%s: SDU received on non RX vc %u.%u\n", 1060 card->name, vpi, vci); 1061 recycle_rx_skb(card, skb); 1062 return; 1063 } 1064 1065 vcc = vc->rx_vcc; 1066 1067 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1068 skb_end_pointer(skb) - skb->data, 1069 PCI_DMA_FROMDEVICE); 1070 1071 if ((vcc->qos.aal == ATM_AAL0) || 1072 (vcc->qos.aal == ATM_AAL34)) { 1073 struct sk_buff *sb; 1074 unsigned char *cell; 1075 u32 aal0; 1076 1077 cell = skb->data; 1078 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1079 if ((sb = dev_alloc_skb(64)) == NULL) { 1080 printk("%s: Can't allocate buffers for aal0.\n", 1081 card->name); 1082 atomic_add(i, &vcc->stats->rx_drop); 1083 break; 1084 } 1085 if (!atm_charge(vcc, sb->truesize)) { 1086 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1087 card->name); 1088 atomic_add(i - 1, &vcc->stats->rx_drop); 1089 dev_kfree_skb(sb); 1090 break; 1091 } 1092 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1093 (vci << ATM_HDR_VCI_SHIFT); 1094 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1095 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1096 1097 *((u32 *) sb->data) = aal0; 1098 skb_put(sb, sizeof(u32)); 1099 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1100 cell, ATM_CELL_PAYLOAD); 1101 1102 ATM_SKB(sb)->vcc = vcc; 1103 __net_timestamp(sb); 1104 vcc->push(vcc, sb); 1105 atomic_inc(&vcc->stats->rx); 1106 1107 cell += ATM_CELL_PAYLOAD; 1108 } 1109 1110 recycle_rx_skb(card, skb); 1111 return; 1112 } 1113 if (vcc->qos.aal != ATM_AAL5) { 1114 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1115 card->name, vcc->qos.aal); 1116 recycle_rx_skb(card, skb); 1117 return; 1118 } 1119 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1120 1121 rpp = &vc->rcv.rx_pool; 1122 1123 rpp->len += skb->len; 1124 if (!rpp->count++) 1125 rpp->first = skb; 1126 *rpp->last = skb; 1127 rpp->last = &skb->next; 1128 1129 if (stat & SAR_RSQE_EPDU) { 1130 unsigned char *l1l2; 1131 unsigned int len; 1132 1133 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1134 1135 len = (l1l2[0] << 8) | l1l2[1]; 1136 len = len ? len : 0x10000; 1137 1138 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1139 1140 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1141 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1142 "(CDC: %08x)\n", 1143 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1144 recycle_rx_pool_skb(card, rpp); 1145 atomic_inc(&vcc->stats->rx_err); 1146 return; 1147 } 1148 if (stat & SAR_RSQE_CRC) { 1149 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1150 recycle_rx_pool_skb(card, rpp); 1151 atomic_inc(&vcc->stats->rx_err); 1152 return; 1153 } 1154 if (rpp->count > 1) { 1155 struct sk_buff *sb; 1156 1157 skb = dev_alloc_skb(rpp->len); 1158 if (!skb) { 1159 RXPRINTK("%s: Can't alloc RX skb.\n", 1160 card->name); 1161 recycle_rx_pool_skb(card, rpp); 1162 atomic_inc(&vcc->stats->rx_err); 1163 return; 1164 } 1165 if (!atm_charge(vcc, skb->truesize)) { 1166 recycle_rx_pool_skb(card, rpp); 1167 dev_kfree_skb(skb); 1168 return; 1169 } 1170 sb = rpp->first; 1171 for (i = 0; i < rpp->count; i++) { 1172 memcpy(skb_put(skb, sb->len), 1173 sb->data, sb->len); 1174 sb = sb->next; 1175 } 1176 1177 recycle_rx_pool_skb(card, rpp); 1178 1179 skb_trim(skb, len); 1180 ATM_SKB(skb)->vcc = vcc; 1181 __net_timestamp(skb); 1182 1183 vcc->push(vcc, skb); 1184 atomic_inc(&vcc->stats->rx); 1185 1186 return; 1187 } 1188 1189 skb->next = NULL; 1190 flush_rx_pool(card, rpp); 1191 1192 if (!atm_charge(vcc, skb->truesize)) { 1193 recycle_rx_skb(card, skb); 1194 return; 1195 } 1196 1197 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1198 skb_end_pointer(skb) - skb->data, 1199 PCI_DMA_FROMDEVICE); 1200 sb_pool_remove(card, skb); 1201 1202 skb_trim(skb, len); 1203 ATM_SKB(skb)->vcc = vcc; 1204 __net_timestamp(skb); 1205 1206 vcc->push(vcc, skb); 1207 atomic_inc(&vcc->stats->rx); 1208 1209 if (skb->truesize > SAR_FB_SIZE_3) 1210 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1211 else if (skb->truesize > SAR_FB_SIZE_2) 1212 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1213 else if (skb->truesize > SAR_FB_SIZE_1) 1214 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1215 else 1216 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1217 return; 1218 } 1219} 1220 1221static void 1222idt77252_rx(struct idt77252_dev *card) 1223{ 1224 struct rsq_entry *rsqe; 1225 1226 if (card->rsq.next == card->rsq.last) 1227 rsqe = card->rsq.base; 1228 else 1229 rsqe = card->rsq.next + 1; 1230 1231 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1232 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1233 return; 1234 } 1235 1236 do { 1237 dequeue_rx(card, rsqe); 1238 rsqe->word_4 = 0; 1239 card->rsq.next = rsqe; 1240 if (card->rsq.next == card->rsq.last) 1241 rsqe = card->rsq.base; 1242 else 1243 rsqe = card->rsq.next + 1; 1244 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1245 1246 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1247 SAR_REG_RSQH); 1248} 1249 1250static void 1251idt77252_rx_raw(struct idt77252_dev *card) 1252{ 1253 struct sk_buff *queue; 1254 u32 head, tail; 1255 struct atm_vcc *vcc; 1256 struct vc_map *vc; 1257 struct sk_buff *sb; 1258 1259 if (card->raw_cell_head == NULL) { 1260 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1261 card->raw_cell_head = sb_pool_skb(card, handle); 1262 } 1263 1264 queue = card->raw_cell_head; 1265 if (!queue) 1266 return; 1267 1268 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1269 tail = readl(SAR_REG_RAWCT); 1270 1271 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1272 skb_end_pointer(queue) - queue->head - 16, 1273 PCI_DMA_FROMDEVICE); 1274 1275 while (head != tail) { 1276 unsigned int vpi, vci, pti; 1277 u32 header; 1278 1279 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1280 1281 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1282 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1283 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1284 1285#ifdef CONFIG_ATM_IDT77252_DEBUG 1286 if (debug & DBG_RAW_CELL) { 1287 int i; 1288 1289 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1290 card->name, (header >> 28) & 0x000f, 1291 (header >> 20) & 0x00ff, 1292 (header >> 4) & 0xffff, 1293 (header >> 1) & 0x0007, 1294 (header >> 0) & 0x0001); 1295 for (i = 16; i < 64; i++) 1296 printk(" %02x", queue->data[i]); 1297 printk("\n"); 1298 } 1299#endif 1300 1301 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1302 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1303 card->name, vpi, vci); 1304 goto drop; 1305 } 1306 1307 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1308 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1309 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1310 card->name, vpi, vci); 1311 goto drop; 1312 } 1313 1314 vcc = vc->rx_vcc; 1315 1316 if (vcc->qos.aal != ATM_AAL0) { 1317 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1318 card->name, vpi, vci); 1319 atomic_inc(&vcc->stats->rx_drop); 1320 goto drop; 1321 } 1322 1323 if ((sb = dev_alloc_skb(64)) == NULL) { 1324 printk("%s: Can't allocate buffers for AAL0.\n", 1325 card->name); 1326 atomic_inc(&vcc->stats->rx_err); 1327 goto drop; 1328 } 1329 1330 if (!atm_charge(vcc, sb->truesize)) { 1331 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1332 card->name); 1333 dev_kfree_skb(sb); 1334 goto drop; 1335 } 1336 1337 *((u32 *) sb->data) = header; 1338 skb_put(sb, sizeof(u32)); 1339 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1340 ATM_CELL_PAYLOAD); 1341 1342 ATM_SKB(sb)->vcc = vcc; 1343 __net_timestamp(sb); 1344 vcc->push(vcc, sb); 1345 atomic_inc(&vcc->stats->rx); 1346 1347drop: 1348 skb_pull(queue, 64); 1349 1350 head = IDT77252_PRV_PADDR(queue) 1351 + (queue->data - queue->head - 16); 1352 1353 if (queue->len < 128) { 1354 struct sk_buff *next; 1355 u32 handle; 1356 1357 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1358 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1359 1360 next = sb_pool_skb(card, handle); 1361 recycle_rx_skb(card, queue); 1362 1363 if (next) { 1364 card->raw_cell_head = next; 1365 queue = card->raw_cell_head; 1366 pci_dma_sync_single_for_cpu(card->pcidev, 1367 IDT77252_PRV_PADDR(queue), 1368 (skb_end_pointer(queue) - 1369 queue->data), 1370 PCI_DMA_FROMDEVICE); 1371 } else { 1372 card->raw_cell_head = NULL; 1373 printk("%s: raw cell queue overrun\n", 1374 card->name); 1375 break; 1376 } 1377 } 1378 } 1379} 1380 1381 1382/*****************************************************************************/ 1383/* */ 1384/* TSQ Handling */ 1385/* */ 1386/*****************************************************************************/ 1387 1388static int 1389init_tsq(struct idt77252_dev *card) 1390{ 1391 struct tsq_entry *tsqe; 1392 1393 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1394 &card->tsq.paddr); 1395 if (card->tsq.base == NULL) { 1396 printk("%s: can't allocate TSQ.\n", card->name); 1397 return -1; 1398 } 1399 memset(card->tsq.base, 0, TSQSIZE); 1400 1401 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1402 card->tsq.next = card->tsq.last; 1403 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1404 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1405 1406 writel(card->tsq.paddr, SAR_REG_TSQB); 1407 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1408 SAR_REG_TSQH); 1409 1410 return 0; 1411} 1412 1413static void 1414deinit_tsq(struct idt77252_dev *card) 1415{ 1416 pci_free_consistent(card->pcidev, TSQSIZE, 1417 card->tsq.base, card->tsq.paddr); 1418} 1419 1420static void 1421idt77252_tx(struct idt77252_dev *card) 1422{ 1423 struct tsq_entry *tsqe; 1424 unsigned int vpi, vci; 1425 struct vc_map *vc; 1426 u32 conn, stat; 1427 1428 if (card->tsq.next == card->tsq.last) 1429 tsqe = card->tsq.base; 1430 else 1431 tsqe = card->tsq.next + 1; 1432 1433 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1434 card->tsq.base, card->tsq.next, card->tsq.last); 1435 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1436 readl(SAR_REG_TSQB), 1437 readl(SAR_REG_TSQT), 1438 readl(SAR_REG_TSQH)); 1439 1440 stat = le32_to_cpu(tsqe->word_2); 1441 1442 if (stat & SAR_TSQE_INVALID) 1443 return; 1444 1445 do { 1446 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1447 le32_to_cpu(tsqe->word_1), 1448 le32_to_cpu(tsqe->word_2)); 1449 1450 switch (stat & SAR_TSQE_TYPE) { 1451 case SAR_TSQE_TYPE_TIMER: 1452 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1453 break; 1454 1455 case SAR_TSQE_TYPE_IDLE: 1456 1457 conn = le32_to_cpu(tsqe->word_1); 1458 1459 if (SAR_TSQE_TAG(stat) == 0x10) { 1460#ifdef NOTDEF 1461 printk("%s: Connection %d halted.\n", 1462 card->name, 1463 le32_to_cpu(tsqe->word_1) & 0x1fff); 1464#endif 1465 break; 1466 } 1467 1468 vc = card->vcs[conn & 0x1fff]; 1469 if (!vc) { 1470 printk("%s: could not find VC from conn %d\n", 1471 card->name, conn & 0x1fff); 1472 break; 1473 } 1474 1475 printk("%s: Connection %d IDLE.\n", 1476 card->name, vc->index); 1477 1478 set_bit(VCF_IDLE, &vc->flags); 1479 break; 1480 1481 case SAR_TSQE_TYPE_TSR: 1482 1483 conn = le32_to_cpu(tsqe->word_1); 1484 1485 vc = card->vcs[conn & 0x1fff]; 1486 if (!vc) { 1487 printk("%s: no VC at index %d\n", 1488 card->name, 1489 le32_to_cpu(tsqe->word_1) & 0x1fff); 1490 break; 1491 } 1492 1493 drain_scq(card, vc); 1494 break; 1495 1496 case SAR_TSQE_TYPE_TBD_COMP: 1497 1498 conn = le32_to_cpu(tsqe->word_1); 1499 1500 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1501 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1502 1503 if (vpi >= (1 << card->vpibits) || 1504 vci >= (1 << card->vcibits)) { 1505 printk("%s: TBD complete: " 1506 "out of range VPI.VCI %u.%u\n", 1507 card->name, vpi, vci); 1508 break; 1509 } 1510 1511 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1512 if (!vc) { 1513 printk("%s: TBD complete: " 1514 "no VC at VPI.VCI %u.%u\n", 1515 card->name, vpi, vci); 1516 break; 1517 } 1518 1519 drain_scq(card, vc); 1520 break; 1521 } 1522 1523 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1524 1525 card->tsq.next = tsqe; 1526 if (card->tsq.next == card->tsq.last) 1527 tsqe = card->tsq.base; 1528 else 1529 tsqe = card->tsq.next + 1; 1530 1531 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1532 card->tsq.base, card->tsq.next, card->tsq.last); 1533 1534 stat = le32_to_cpu(tsqe->word_2); 1535 1536 } while (!(stat & SAR_TSQE_INVALID)); 1537 1538 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1539 SAR_REG_TSQH); 1540 1541 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1542 card->index, readl(SAR_REG_TSQH), 1543 readl(SAR_REG_TSQT), card->tsq.next); 1544} 1545 1546 1547static void 1548tst_timer(unsigned long data) 1549{ 1550 struct idt77252_dev *card = (struct idt77252_dev *)data; 1551 unsigned long base, idle, jump; 1552 unsigned long flags; 1553 u32 pc; 1554 int e; 1555 1556 spin_lock_irqsave(&card->tst_lock, flags); 1557 1558 base = card->tst[card->tst_index]; 1559 idle = card->tst[card->tst_index ^ 1]; 1560 1561 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1562 jump = base + card->tst_size - 2; 1563 1564 pc = readl(SAR_REG_NOW) >> 2; 1565 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1566 mod_timer(&card->tst_timer, jiffies + 1); 1567 goto out; 1568 } 1569 1570 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1571 1572 card->tst_index ^= 1; 1573 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1574 1575 base = card->tst[card->tst_index]; 1576 idle = card->tst[card->tst_index ^ 1]; 1577 1578 for (e = 0; e < card->tst_size - 2; e++) { 1579 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1580 write_sram(card, idle + e, 1581 card->soft_tst[e].tste & TSTE_MASK); 1582 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1583 } 1584 } 1585 } 1586 1587 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1588 1589 for (e = 0; e < card->tst_size - 2; e++) { 1590 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1591 write_sram(card, idle + e, 1592 card->soft_tst[e].tste & TSTE_MASK); 1593 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1594 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1595 } 1596 } 1597 1598 jump = base + card->tst_size - 2; 1599 1600 write_sram(card, jump, TSTE_OPC_NULL); 1601 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1602 1603 mod_timer(&card->tst_timer, jiffies + 1); 1604 } 1605 1606out: 1607 spin_unlock_irqrestore(&card->tst_lock, flags); 1608} 1609 1610static int 1611__fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1612 int n, unsigned int opc) 1613{ 1614 unsigned long cl, avail; 1615 unsigned long idle; 1616 int e, r; 1617 u32 data; 1618 1619 avail = card->tst_size - 2; 1620 for (e = 0; e < avail; e++) { 1621 if (card->soft_tst[e].vc == NULL) 1622 break; 1623 } 1624 if (e >= avail) { 1625 printk("%s: No free TST entries found\n", card->name); 1626 return -1; 1627 } 1628 1629 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1630 card->name, vc ? vc->index : -1, e); 1631 1632 r = n; 1633 cl = avail; 1634 data = opc & TSTE_OPC_MASK; 1635 if (vc && (opc != TSTE_OPC_NULL)) 1636 data = opc | vc->index; 1637 1638 idle = card->tst[card->tst_index ^ 1]; 1639 1640 /* 1641 * Fill Soft TST. 1642 */ 1643 while (r > 0) { 1644 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1645 if (vc) 1646 card->soft_tst[e].vc = vc; 1647 else 1648 card->soft_tst[e].vc = (void *)-1; 1649 1650 card->soft_tst[e].tste = data; 1651 if (timer_pending(&card->tst_timer)) 1652 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1653 else { 1654 write_sram(card, idle + e, data); 1655 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1656 } 1657 1658 cl -= card->tst_size; 1659 r--; 1660 } 1661 1662 if (++e == avail) 1663 e = 0; 1664 cl += n; 1665 } 1666 1667 return 0; 1668} 1669 1670static int 1671fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1672{ 1673 unsigned long flags; 1674 int res; 1675 1676 spin_lock_irqsave(&card->tst_lock, flags); 1677 1678 res = __fill_tst(card, vc, n, opc); 1679 1680 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1681 if (!timer_pending(&card->tst_timer)) 1682 mod_timer(&card->tst_timer, jiffies + 1); 1683 1684 spin_unlock_irqrestore(&card->tst_lock, flags); 1685 return res; 1686} 1687 1688static int 1689__clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1690{ 1691 unsigned long idle; 1692 int e; 1693 1694 idle = card->tst[card->tst_index ^ 1]; 1695 1696 for (e = 0; e < card->tst_size - 2; e++) { 1697 if (card->soft_tst[e].vc == vc) { 1698 card->soft_tst[e].vc = NULL; 1699 1700 card->soft_tst[e].tste = TSTE_OPC_VAR; 1701 if (timer_pending(&card->tst_timer)) 1702 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1703 else { 1704 write_sram(card, idle + e, TSTE_OPC_VAR); 1705 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1706 } 1707 } 1708 } 1709 1710 return 0; 1711} 1712 1713static int 1714clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1715{ 1716 unsigned long flags; 1717 int res; 1718 1719 spin_lock_irqsave(&card->tst_lock, flags); 1720 1721 res = __clear_tst(card, vc); 1722 1723 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1724 if (!timer_pending(&card->tst_timer)) 1725 mod_timer(&card->tst_timer, jiffies + 1); 1726 1727 spin_unlock_irqrestore(&card->tst_lock, flags); 1728 return res; 1729} 1730 1731static int 1732change_tst(struct idt77252_dev *card, struct vc_map *vc, 1733 int n, unsigned int opc) 1734{ 1735 unsigned long flags; 1736 int res; 1737 1738 spin_lock_irqsave(&card->tst_lock, flags); 1739 1740 __clear_tst(card, vc); 1741 res = __fill_tst(card, vc, n, opc); 1742 1743 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1744 if (!timer_pending(&card->tst_timer)) 1745 mod_timer(&card->tst_timer, jiffies + 1); 1746 1747 spin_unlock_irqrestore(&card->tst_lock, flags); 1748 return res; 1749} 1750 1751 1752static int 1753set_tct(struct idt77252_dev *card, struct vc_map *vc) 1754{ 1755 unsigned long tct; 1756 1757 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1758 1759 switch (vc->class) { 1760 case SCHED_CBR: 1761 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1762 card->name, tct, vc->scq->scd); 1763 1764 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1765 write_sram(card, tct + 1, 0); 1766 write_sram(card, tct + 2, 0); 1767 write_sram(card, tct + 3, 0); 1768 write_sram(card, tct + 4, 0); 1769 write_sram(card, tct + 5, 0); 1770 write_sram(card, tct + 6, 0); 1771 write_sram(card, tct + 7, 0); 1772 break; 1773 1774 case SCHED_UBR: 1775 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1776 card->name, tct, vc->scq->scd); 1777 1778 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1779 write_sram(card, tct + 1, 0); 1780 write_sram(card, tct + 2, TCT_TSIF); 1781 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1782 write_sram(card, tct + 4, 0); 1783 write_sram(card, tct + 5, vc->init_er); 1784 write_sram(card, tct + 6, 0); 1785 write_sram(card, tct + 7, TCT_FLAG_UBR); 1786 break; 1787 1788 case SCHED_VBR: 1789 case SCHED_ABR: 1790 default: 1791 return -ENOSYS; 1792 } 1793 1794 return 0; 1795} 1796 1797/*****************************************************************************/ 1798/* */ 1799/* FBQ Handling */ 1800/* */ 1801/*****************************************************************************/ 1802 1803static __inline__ int 1804idt77252_fbq_level(struct idt77252_dev *card, int queue) 1805{ 1806 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1807} 1808 1809static __inline__ int 1810idt77252_fbq_full(struct idt77252_dev *card, int queue) 1811{ 1812 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1813} 1814 1815static int 1816push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1817{ 1818 unsigned long flags; 1819 u32 handle; 1820 u32 addr; 1821 1822 skb->data = skb->head; 1823 skb_reset_tail_pointer(skb); 1824 skb->len = 0; 1825 1826 skb_reserve(skb, 16); 1827 1828 switch (queue) { 1829 case 0: 1830 skb_put(skb, SAR_FB_SIZE_0); 1831 break; 1832 case 1: 1833 skb_put(skb, SAR_FB_SIZE_1); 1834 break; 1835 case 2: 1836 skb_put(skb, SAR_FB_SIZE_2); 1837 break; 1838 case 3: 1839 skb_put(skb, SAR_FB_SIZE_3); 1840 break; 1841 default: 1842 dev_kfree_skb(skb); 1843 return -1; 1844 } 1845 1846 if (idt77252_fbq_full(card, queue)) 1847 return -1; 1848 1849 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1850 1851 handle = IDT77252_PRV_POOL(skb); 1852 addr = IDT77252_PRV_PADDR(skb); 1853 1854 spin_lock_irqsave(&card->cmd_lock, flags); 1855 writel(handle, card->fbq[queue]); 1856 writel(addr, card->fbq[queue]); 1857 spin_unlock_irqrestore(&card->cmd_lock, flags); 1858 1859 return 0; 1860} 1861 1862static void 1863add_rx_skb(struct idt77252_dev *card, int queue, 1864 unsigned int size, unsigned int count) 1865{ 1866 struct sk_buff *skb; 1867 dma_addr_t paddr; 1868 u32 handle; 1869 1870 while (count--) { 1871 skb = dev_alloc_skb(size); 1872 if (!skb) 1873 return; 1874 1875 if (sb_pool_add(card, skb, queue)) { 1876 printk("%s: SB POOL full\n", __FUNCTION__); 1877 goto outfree; 1878 } 1879 1880 paddr = pci_map_single(card->pcidev, skb->data, 1881 skb_end_pointer(skb) - skb->data, 1882 PCI_DMA_FROMDEVICE); 1883 IDT77252_PRV_PADDR(skb) = paddr; 1884 1885 if (push_rx_skb(card, skb, queue)) { 1886 printk("%s: FB QUEUE full\n", __FUNCTION__); 1887 goto outunmap; 1888 } 1889 } 1890 1891 return; 1892 1893outunmap: 1894 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1895 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1896 1897 handle = IDT77252_PRV_POOL(skb); 1898 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1899 1900outfree: 1901 dev_kfree_skb(skb); 1902} 1903 1904 1905static void 1906recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1907{ 1908 u32 handle = IDT77252_PRV_POOL(skb); 1909 int err; 1910 1911 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1912 skb_end_pointer(skb) - skb->data, 1913 PCI_DMA_FROMDEVICE); 1914 1915 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1916 if (err) { 1917 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1918 skb_end_pointer(skb) - skb->data, 1919 PCI_DMA_FROMDEVICE); 1920 sb_pool_remove(card, skb); 1921 dev_kfree_skb(skb); 1922 } 1923} 1924 1925static void 1926flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1927{ 1928 rpp->len = 0; 1929 rpp->count = 0; 1930 rpp->first = NULL; 1931 rpp->last = &rpp->first; 1932} 1933 1934static void 1935recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1936{ 1937 struct sk_buff *skb, *next; 1938 int i; 1939 1940 skb = rpp->first; 1941 for (i = 0; i < rpp->count; i++) { 1942 next = skb->next; 1943 skb->next = NULL; 1944 recycle_rx_skb(card, skb); 1945 skb = next; 1946 } 1947 flush_rx_pool(card, rpp); 1948} 1949 1950/*****************************************************************************/ 1951/* */ 1952/* ATM Interface */ 1953/* */ 1954/*****************************************************************************/ 1955 1956static void 1957idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1958{ 1959 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1960} 1961 1962static unsigned char 1963idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1964{ 1965 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1966} 1967 1968static inline int 1969idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1970{ 1971 struct atm_dev *dev = vcc->dev; 1972 struct idt77252_dev *card = dev->dev_data; 1973 struct vc_map *vc = vcc->dev_data; 1974 int err; 1975 1976 if (vc == NULL) { 1977 printk("%s: NULL connection in send().\n", card->name); 1978 atomic_inc(&vcc->stats->tx_err); 1979 dev_kfree_skb(skb); 1980 return -EINVAL; 1981 } 1982 if (!test_bit(VCF_TX, &vc->flags)) { 1983 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1984 atomic_inc(&vcc->stats->tx_err); 1985 dev_kfree_skb(skb); 1986 return -EINVAL; 1987 } 1988 1989 switch (vcc->qos.aal) { 1990 case ATM_AAL0: 1991 case ATM_AAL1: 1992 case ATM_AAL5: 1993 break; 1994 default: 1995 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1996 atomic_inc(&vcc->stats->tx_err); 1997 dev_kfree_skb(skb); 1998 return -EINVAL; 1999 } 2000 2001 if (skb_shinfo(skb)->nr_frags != 0) { 2002 printk("%s: No scatter-gather yet.\n", card->name); 2003 atomic_inc(&vcc->stats->tx_err); 2004 dev_kfree_skb(skb); 2005 return -EINVAL; 2006 } 2007 ATM_SKB(skb)->vcc = vcc; 2008 2009 err = queue_skb(card, vc, skb, oam); 2010 if (err) { 2011 atomic_inc(&vcc->stats->tx_err); 2012 dev_kfree_skb(skb); 2013 return err; 2014 } 2015 2016 return 0; 2017} 2018 2019int 2020idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2021{ 2022 return idt77252_send_skb(vcc, skb, 0); 2023} 2024 2025static int 2026idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2027{ 2028 struct atm_dev *dev = vcc->dev; 2029 struct idt77252_dev *card = dev->dev_data; 2030 struct sk_buff *skb; 2031 2032 skb = dev_alloc_skb(64); 2033 if (!skb) { 2034 printk("%s: Out of memory in send_oam().\n", card->name); 2035 atomic_inc(&vcc->stats->tx_err); 2036 return -ENOMEM; 2037 } 2038 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2039 2040 memcpy(skb_put(skb, 52), cell, 52); 2041 2042 return idt77252_send_skb(vcc, skb, 1); 2043} 2044 2045static __inline__ unsigned int 2046idt77252_fls(unsigned int x) 2047{ 2048 int r = 1; 2049 2050 if (x == 0) 2051 return 0; 2052 if (x & 0xffff0000) { 2053 x >>= 16; 2054 r += 16; 2055 } 2056 if (x & 0xff00) { 2057 x >>= 8; 2058 r += 8; 2059 } 2060 if (x & 0xf0) { 2061 x >>= 4; 2062 r += 4; 2063 } 2064 if (x & 0xc) { 2065 x >>= 2; 2066 r += 2; 2067 } 2068 if (x & 0x2) 2069 r += 1; 2070 return r; 2071} 2072 2073static u16 2074idt77252_int_to_atmfp(unsigned int rate) 2075{ 2076 u16 m, e; 2077 2078 if (rate == 0) 2079 return 0; 2080 e = idt77252_fls(rate) - 1; 2081 if (e < 9) 2082 m = (rate - (1 << e)) << (9 - e); 2083 else if (e == 9) 2084 m = (rate - (1 << e)); 2085 else /* e > 9 */ 2086 m = (rate - (1 << e)) >> (e - 9); 2087 return 0x4000 | (e << 9) | m; 2088} 2089 2090static u8 2091idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2092{ 2093 u16 afp; 2094 2095 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2096 if (pcr < 0) 2097 return rate_to_log[(afp >> 5) & 0x1ff]; 2098 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2099} 2100 2101static void 2102idt77252_est_timer(unsigned long data) 2103{ 2104 struct vc_map *vc = (struct vc_map *)data; 2105 struct idt77252_dev *card = vc->card; 2106 struct rate_estimator *est; 2107 unsigned long flags; 2108 u32 rate, cps; 2109 u64 ncells; 2110 u8 lacr; 2111 2112 spin_lock_irqsave(&vc->lock, flags); 2113 est = vc->estimator; 2114 if (!est) 2115 goto out; 2116 2117 ncells = est->cells; 2118 2119 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2120 est->last_cells = ncells; 2121 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2122 est->cps = (est->avcps + 0x1f) >> 5; 2123 2124 cps = est->cps; 2125 if (cps < (est->maxcps >> 4)) 2126 cps = est->maxcps >> 4; 2127 2128 lacr = idt77252_rate_logindex(card, cps); 2129 if (lacr > vc->max_er) 2130 lacr = vc->max_er; 2131 2132 if (lacr != vc->lacr) { 2133 vc->lacr = lacr; 2134 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2135 } 2136 2137 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2138 add_timer(&est->timer); 2139 2140out: 2141 spin_unlock_irqrestore(&vc->lock, flags); 2142} 2143 2144static struct rate_estimator * 2145idt77252_init_est(struct vc_map *vc, int pcr) 2146{ 2147 struct rate_estimator *est; 2148 2149 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2150 if (!est) 2151 return NULL; 2152 est->maxcps = pcr < 0 ? -pcr : pcr; 2153 est->cps = est->maxcps; 2154 est->avcps = est->cps << 5; 2155 2156 est->interval = 2; /* XXX: make this configurable */ 2157 est->ewma_log = 2; /* XXX: make this configurable */ 2158 init_timer(&est->timer); 2159 est->timer.data = (unsigned long)vc; 2160 est->timer.function = idt77252_est_timer; 2161 2162 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2163 add_timer(&est->timer); 2164 2165 return est; 2166} 2167 2168static int 2169idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2170 struct atm_vcc *vcc, struct atm_qos *qos) 2171{ 2172 int tst_free, tst_used, tst_entries; 2173 unsigned long tmpl, modl; 2174 int tcr, tcra; 2175 2176 if ((qos->txtp.max_pcr == 0) && 2177 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2178 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2179 card->name); 2180 return -EINVAL; 2181 } 2182 2183 tst_used = 0; 2184 tst_free = card->tst_free; 2185 if (test_bit(VCF_TX, &vc->flags)) 2186 tst_used = vc->ntste; 2187 tst_free += tst_used; 2188 2189 tcr = atm_pcr_goal(&qos->txtp); 2190 tcra = tcr >= 0 ? tcr : -tcr; 2191 2192 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2193 2194 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2195 modl = tmpl % (unsigned long)card->utopia_pcr; 2196 2197 tst_entries = (int) (tmpl / card->utopia_pcr); 2198 if (tcr > 0) { 2199 if (modl > 0) 2200 tst_entries++; 2201 } else if (tcr == 0) { 2202 tst_entries = tst_free - SAR_TST_RESERVED; 2203 if (tst_entries <= 0) { 2204 printk("%s: no CBR bandwidth free.\n", card->name); 2205 return -ENOSR; 2206 } 2207 } 2208 2209 if (tst_entries == 0) { 2210 printk("%s: selected CBR bandwidth < granularity.\n", 2211 card->name); 2212 return -EINVAL; 2213 } 2214 2215 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2216 printk("%s: not enough CBR bandwidth free.\n", card->name); 2217 return -ENOSR; 2218 } 2219 2220 vc->ntste = tst_entries; 2221 2222 card->tst_free = tst_free - tst_entries; 2223 if (test_bit(VCF_TX, &vc->flags)) { 2224 if (tst_used == tst_entries) 2225 return 0; 2226 2227 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2228 card->name, tst_used, tst_entries); 2229 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2230 return 0; 2231 } 2232 2233 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2234 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2235 return 0; 2236} 2237 2238static int 2239idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2240 struct atm_vcc *vcc, struct atm_qos *qos) 2241{ 2242 unsigned long flags; 2243 int tcr; 2244 2245 spin_lock_irqsave(&vc->lock, flags); 2246 if (vc->estimator) { 2247 del_timer(&vc->estimator->timer); 2248 kfree(vc->estimator); 2249 vc->estimator = NULL; 2250 } 2251 spin_unlock_irqrestore(&vc->lock, flags); 2252 2253 tcr = atm_pcr_goal(&qos->txtp); 2254 if (tcr == 0) 2255 tcr = card->link_pcr; 2256 2257 vc->estimator = idt77252_init_est(vc, tcr); 2258 2259 vc->class = SCHED_UBR; 2260 vc->init_er = idt77252_rate_logindex(card, tcr); 2261 vc->lacr = vc->init_er; 2262 if (tcr < 0) 2263 vc->max_er = vc->init_er; 2264 else 2265 vc->max_er = 0xff; 2266 2267 return 0; 2268} 2269 2270static int 2271idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2272 struct atm_vcc *vcc, struct atm_qos *qos) 2273{ 2274 int error; 2275 2276 if (test_bit(VCF_TX, &vc->flags)) 2277 return -EBUSY; 2278 2279 switch (qos->txtp.traffic_class) { 2280 case ATM_CBR: 2281 vc->class = SCHED_CBR; 2282 break; 2283 2284 case ATM_UBR: 2285 vc->class = SCHED_UBR; 2286 break; 2287 2288 case ATM_VBR: 2289 case ATM_ABR: 2290 default: 2291 return -EPROTONOSUPPORT; 2292 } 2293 2294 vc->scq = alloc_scq(card, vc->class); 2295 if (!vc->scq) { 2296 printk("%s: can't get SCQ.\n", card->name); 2297 return -ENOMEM; 2298 } 2299 2300 vc->scq->scd = get_free_scd(card, vc); 2301 if (vc->scq->scd == 0) { 2302 printk("%s: no SCD available.\n", card->name); 2303 free_scq(card, vc->scq); 2304 return -ENOMEM; 2305 } 2306 2307 fill_scd(card, vc->scq, vc->class); 2308 2309 if (set_tct(card, vc)) { 2310 printk("%s: class %d not supported.\n", 2311 card->name, qos->txtp.traffic_class); 2312 2313 card->scd2vc[vc->scd_index] = NULL; 2314 free_scq(card, vc->scq); 2315 return -EPROTONOSUPPORT; 2316 } 2317 2318 switch (vc->class) { 2319 case SCHED_CBR: 2320 error = idt77252_init_cbr(card, vc, vcc, qos); 2321 if (error) { 2322 card->scd2vc[vc->scd_index] = NULL; 2323 free_scq(card, vc->scq); 2324 return error; 2325 } 2326 2327 clear_bit(VCF_IDLE, &vc->flags); 2328 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2329 break; 2330 2331 case SCHED_UBR: 2332 error = idt77252_init_ubr(card, vc, vcc, qos); 2333 if (error) { 2334 card->scd2vc[vc->scd_index] = NULL; 2335 free_scq(card, vc->scq); 2336 return error; 2337 } 2338 2339 set_bit(VCF_IDLE, &vc->flags); 2340 break; 2341 } 2342 2343 vc->tx_vcc = vcc; 2344 set_bit(VCF_TX, &vc->flags); 2345 return 0; 2346} 2347 2348static int 2349idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2350 struct atm_vcc *vcc, struct atm_qos *qos) 2351{ 2352 unsigned long flags; 2353 unsigned long addr; 2354 u32 rcte = 0; 2355 2356 if (test_bit(VCF_RX, &vc->flags)) 2357 return -EBUSY; 2358 2359 vc->rx_vcc = vcc; 2360 set_bit(VCF_RX, &vc->flags); 2361 2362 if ((vcc->vci == 3) || (vcc->vci == 4)) 2363 return 0; 2364 2365 flush_rx_pool(card, &vc->rcv.rx_pool); 2366 2367 rcte |= SAR_RCTE_CONNECTOPEN; 2368 rcte |= SAR_RCTE_RAWCELLINTEN; 2369 2370 switch (qos->aal) { 2371 case ATM_AAL0: 2372 rcte |= SAR_RCTE_RCQ; 2373 break; 2374 case ATM_AAL1: 2375 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2376 break; 2377 case ATM_AAL34: 2378 rcte |= SAR_RCTE_AAL34; 2379 break; 2380 case ATM_AAL5: 2381 rcte |= SAR_RCTE_AAL5; 2382 break; 2383 default: 2384 rcte |= SAR_RCTE_RCQ; 2385 break; 2386 } 2387 2388 if (qos->aal != ATM_AAL5) 2389 rcte |= SAR_RCTE_FBP_1; 2390 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2391 rcte |= SAR_RCTE_FBP_3; 2392 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2393 rcte |= SAR_RCTE_FBP_2; 2394 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2395 rcte |= SAR_RCTE_FBP_1; 2396 else 2397 rcte |= SAR_RCTE_FBP_01; 2398 2399 addr = card->rct_base + (vc->index << 2); 2400 2401 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2402 write_sram(card, addr, rcte); 2403 2404 spin_lock_irqsave(&card->cmd_lock, flags); 2405 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2406 waitfor_idle(card); 2407 spin_unlock_irqrestore(&card->cmd_lock, flags); 2408 2409 return 0; 2410} 2411 2412static int 2413idt77252_open(struct atm_vcc *vcc) 2414{ 2415 struct atm_dev *dev = vcc->dev; 2416 struct idt77252_dev *card = dev->dev_data; 2417 struct vc_map *vc; 2418 unsigned int index; 2419 unsigned int inuse; 2420 int error; 2421 int vci = vcc->vci; 2422 short vpi = vcc->vpi; 2423 2424 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2425 return 0; 2426 2427 if (vpi >= (1 << card->vpibits)) { 2428 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2429 return -EINVAL; 2430 } 2431 2432 if (vci >= (1 << card->vcibits)) { 2433 printk("%s: unsupported VCI: %d\n", card->name, vci); 2434 return -EINVAL; 2435 } 2436 2437 set_bit(ATM_VF_ADDR, &vcc->flags); 2438 2439 down(&card->mutex); 2440 2441 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2442 2443 switch (vcc->qos.aal) { 2444 case ATM_AAL0: 2445 case ATM_AAL1: 2446 case ATM_AAL5: 2447 break; 2448 default: 2449 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2450 up(&card->mutex); 2451 return -EPROTONOSUPPORT; 2452 } 2453 2454 index = VPCI2VC(card, vpi, vci); 2455 if (!card->vcs[index]) { 2456 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2457 if (!card->vcs[index]) { 2458 printk("%s: can't alloc vc in open()\n", card->name); 2459 up(&card->mutex); 2460 return -ENOMEM; 2461 } 2462 card->vcs[index]->card = card; 2463 card->vcs[index]->index = index; 2464 2465 spin_lock_init(&card->vcs[index]->lock); 2466 } 2467 vc = card->vcs[index]; 2468 2469 vcc->dev_data = vc; 2470 2471 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2472 card->name, vc->index, vcc->vpi, vcc->vci, 2473 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2474 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2475 vcc->qos.rxtp.max_sdu); 2476 2477 inuse = 0; 2478 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2479 test_bit(VCF_TX, &vc->flags)) 2480 inuse = 1; 2481 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2482 test_bit(VCF_RX, &vc->flags)) 2483 inuse += 2; 2484 2485 if (inuse) { 2486 printk("%s: %s vci already in use.\n", card->name, 2487 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2488 up(&card->mutex); 2489 return -EADDRINUSE; 2490 } 2491 2492 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2493 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2494 if (error) { 2495 up(&card->mutex); 2496 return error; 2497 } 2498 } 2499 2500 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2501 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2502 if (error) { 2503 up(&card->mutex); 2504 return error; 2505 } 2506 } 2507 2508 set_bit(ATM_VF_READY, &vcc->flags); 2509 2510 up(&card->mutex); 2511 return 0; 2512} 2513 2514static void 2515idt77252_close(struct atm_vcc *vcc) 2516{ 2517 struct atm_dev *dev = vcc->dev; 2518 struct idt77252_dev *card = dev->dev_data; 2519 struct vc_map *vc = vcc->dev_data; 2520 unsigned long flags; 2521 unsigned long addr; 2522 unsigned long timeout; 2523 2524 down(&card->mutex); 2525 2526 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2527 card->name, vc->index, vcc->vpi, vcc->vci); 2528 2529 clear_bit(ATM_VF_READY, &vcc->flags); 2530 2531 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2532 2533 spin_lock_irqsave(&vc->lock, flags); 2534 clear_bit(VCF_RX, &vc->flags); 2535 vc->rx_vcc = NULL; 2536 spin_unlock_irqrestore(&vc->lock, flags); 2537 2538 if ((vcc->vci == 3) || (vcc->vci == 4)) 2539 goto done; 2540 2541 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2542 2543 spin_lock_irqsave(&card->cmd_lock, flags); 2544 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2545 waitfor_idle(card); 2546 spin_unlock_irqrestore(&card->cmd_lock, flags); 2547 2548 if (vc->rcv.rx_pool.count) { 2549 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2550 card->name); 2551 2552 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2553 } 2554 } 2555 2556done: 2557 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2558 2559 spin_lock_irqsave(&vc->lock, flags); 2560 clear_bit(VCF_TX, &vc->flags); 2561 clear_bit(VCF_IDLE, &vc->flags); 2562 clear_bit(VCF_RSV, &vc->flags); 2563 vc->tx_vcc = NULL; 2564 2565 if (vc->estimator) { 2566 del_timer(&vc->estimator->timer); 2567 kfree(vc->estimator); 2568 vc->estimator = NULL; 2569 } 2570 spin_unlock_irqrestore(&vc->lock, flags); 2571 2572 timeout = 5 * 1000; 2573 while (atomic_read(&vc->scq->used) > 0) { 2574 timeout = msleep_interruptible(timeout); 2575 if (!timeout) 2576 break; 2577 } 2578 if (!timeout) 2579 printk("%s: SCQ drain timeout: %u used\n", 2580 card->name, atomic_read(&vc->scq->used)); 2581 2582 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2583 clear_scd(card, vc->scq, vc->class); 2584 2585 if (vc->class == SCHED_CBR) { 2586 clear_tst(card, vc); 2587 card->tst_free += vc->ntste; 2588 vc->ntste = 0; 2589 } 2590 2591 card->scd2vc[vc->scd_index] = NULL; 2592 free_scq(card, vc->scq); 2593 } 2594 2595 up(&card->mutex); 2596} 2597 2598static int 2599idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2600{ 2601 struct atm_dev *dev = vcc->dev; 2602 struct idt77252_dev *card = dev->dev_data; 2603 struct vc_map *vc = vcc->dev_data; 2604 int error = 0; 2605 2606 down(&card->mutex); 2607 2608 if (qos->txtp.traffic_class != ATM_NONE) { 2609 if (!test_bit(VCF_TX, &vc->flags)) { 2610 error = idt77252_init_tx(card, vc, vcc, qos); 2611 if (error) 2612 goto out; 2613 } else { 2614 switch (qos->txtp.traffic_class) { 2615 case ATM_CBR: 2616 error = idt77252_init_cbr(card, vc, vcc, qos); 2617 if (error) 2618 goto out; 2619 break; 2620 2621 case ATM_UBR: 2622 error = idt77252_init_ubr(card, vc, vcc, qos); 2623 if (error) 2624 goto out; 2625 2626 if (!test_bit(VCF_IDLE, &vc->flags)) { 2627 writel(TCMDQ_LACR | (vc->lacr << 16) | 2628 vc->index, SAR_REG_TCMDQ); 2629 } 2630 break; 2631 2632 case ATM_VBR: 2633 case ATM_ABR: 2634 error = -EOPNOTSUPP; 2635 goto out; 2636 } 2637 } 2638 } 2639 2640 if ((qos->rxtp.traffic_class != ATM_NONE) && 2641 !test_bit(VCF_RX, &vc->flags)) { 2642 error = idt77252_init_rx(card, vc, vcc, qos); 2643 if (error) 2644 goto out; 2645 } 2646 2647 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2648 2649 set_bit(ATM_VF_HASQOS, &vcc->flags); 2650 2651out: 2652 up(&card->mutex); 2653 return error; 2654} 2655 2656static int 2657idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2658{ 2659 struct idt77252_dev *card = dev->dev_data; 2660 int i, left; 2661 2662 left = (int) *pos; 2663 if (!left--) 2664 return sprintf(page, "IDT77252 Interrupts:\n"); 2665 if (!left--) 2666 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2667 if (!left--) 2668 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2669 if (!left--) 2670 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2671 if (!left--) 2672 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2673 if (!left--) 2674 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2675 if (!left--) 2676 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2677 if (!left--) 2678 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2679 if (!left--) 2680 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2681 if (!left--) 2682 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2683 if (!left--) 2684 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2685 if (!left--) 2686 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2687 if (!left--) 2688 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2689 if (!left--) 2690 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2691 if (!left--) 2692 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2693 2694 for (i = 0; i < card->tct_size; i++) { 2695 unsigned long tct; 2696 struct atm_vcc *vcc; 2697 struct vc_map *vc; 2698 char *p; 2699 2700 vc = card->vcs[i]; 2701 if (!vc) 2702 continue; 2703 2704 vcc = NULL; 2705 if (vc->tx_vcc) 2706 vcc = vc->tx_vcc; 2707 if (!vcc) 2708 continue; 2709 if (left--) 2710 continue; 2711 2712 p = page; 2713 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2714 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2715 2716 for (i = 0; i < 8; i++) 2717 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2718 p += sprintf(p, "\n"); 2719 return p - page; 2720 } 2721 return 0; 2722} 2723 2724/*****************************************************************************/ 2725/* */ 2726/* Interrupt handler */ 2727/* */ 2728/*****************************************************************************/ 2729 2730static void 2731idt77252_collect_stat(struct idt77252_dev *card) 2732{ 2733 u32 cdc, vpec, icc; 2734 2735 cdc = readl(SAR_REG_CDC); 2736 vpec = readl(SAR_REG_VPEC); 2737 icc = readl(SAR_REG_ICC); 2738 2739#ifdef NOTDEF 2740 printk("%s:", card->name); 2741 2742 if (cdc & 0x7f0000) { 2743 char *s = ""; 2744 2745 printk(" ["); 2746 if (cdc & (1 << 22)) { 2747 printk("%sRM ID", s); 2748 s = " | "; 2749 } 2750 if (cdc & (1 << 21)) { 2751 printk("%sCON TAB", s); 2752 s = " | "; 2753 } 2754 if (cdc & (1 << 20)) { 2755 printk("%sNO FB", s); 2756 s = " | "; 2757 } 2758 if (cdc & (1 << 19)) { 2759 printk("%sOAM CRC", s); 2760 s = " | "; 2761 } 2762 if (cdc & (1 << 18)) { 2763 printk("%sRM CRC", s); 2764 s = " | "; 2765 } 2766 if (cdc & (1 << 17)) { 2767 printk("%sRM FIFO", s); 2768 s = " | "; 2769 } 2770 if (cdc & (1 << 16)) { 2771 printk("%sRX FIFO", s); 2772 s = " | "; 2773 } 2774 printk("]"); 2775 } 2776 2777 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2778 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2779#endif 2780} 2781 2782static irqreturn_t 2783idt77252_interrupt(int irq, void *dev_id) 2784{ 2785 struct idt77252_dev *card = dev_id; 2786 u32 stat; 2787 2788 stat = readl(SAR_REG_STAT) & 0xffff; 2789 if (!stat) /* no interrupt for us */ 2790 return IRQ_NONE; 2791 2792 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2793 printk("%s: Re-entering irq_handler()\n", card->name); 2794 goto out; 2795 } 2796 2797 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2798 2799 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2800 INTPRINTK("%s: TSIF\n", card->name); 2801 card->irqstat[15]++; 2802 idt77252_tx(card); 2803 } 2804 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2805 INTPRINTK("%s: TXICP\n", card->name); 2806 card->irqstat[14]++; 2807#ifdef CONFIG_ATM_IDT77252_DEBUG 2808 idt77252_tx_dump(card); 2809#endif 2810 } 2811 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2812 INTPRINTK("%s: TSQF\n", card->name); 2813 card->irqstat[12]++; 2814 idt77252_tx(card); 2815 } 2816 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2817 INTPRINTK("%s: TMROF\n", card->name); 2818 card->irqstat[11]++; 2819 idt77252_collect_stat(card); 2820 } 2821 2822 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2823 INTPRINTK("%s: EPDU\n", card->name); 2824 card->irqstat[5]++; 2825 idt77252_rx(card); 2826 } 2827 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2828 INTPRINTK("%s: RSQAF\n", card->name); 2829 card->irqstat[1]++; 2830 idt77252_rx(card); 2831 } 2832 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2833 INTPRINTK("%s: RSQF\n", card->name); 2834 card->irqstat[6]++; 2835 idt77252_rx(card); 2836 } 2837 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2838 INTPRINTK("%s: RAWCF\n", card->name); 2839 card->irqstat[4]++; 2840 idt77252_rx_raw(card); 2841 } 2842 2843 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2844 INTPRINTK("%s: PHYI", card->name); 2845 card->irqstat[10]++; 2846 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2847 card->atmdev->phy->interrupt(card->atmdev); 2848 } 2849 2850 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2851 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2852 2853 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2854 2855 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2856 2857 if (stat & SAR_STAT_FBQ0A) 2858 card->irqstat[2]++; 2859 if (stat & SAR_STAT_FBQ1A) 2860 card->irqstat[3]++; 2861 if (stat & SAR_STAT_FBQ2A) 2862 card->irqstat[7]++; 2863 if (stat & SAR_STAT_FBQ3A) 2864 card->irqstat[8]++; 2865 2866 schedule_work(&card->tqueue); 2867 } 2868 2869out: 2870 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2871 return IRQ_HANDLED; 2872} 2873 2874static void 2875idt77252_softint(struct work_struct *work) 2876{ 2877 struct idt77252_dev *card = 2878 container_of(work, struct idt77252_dev, tqueue); 2879 u32 stat; 2880 int done; 2881 2882 for (done = 1; ; done = 1) { 2883 stat = readl(SAR_REG_STAT) >> 16; 2884 2885 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2886 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2887 done = 0; 2888 } 2889 2890 stat >>= 4; 2891 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2892 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2893 done = 0; 2894 } 2895 2896 stat >>= 4; 2897 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2898 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2899 done = 0; 2900 } 2901 2902 stat >>= 4; 2903 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2904 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2905 done = 0; 2906 } 2907 2908 if (done) 2909 break; 2910 } 2911 2912 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2913} 2914 2915 2916static int 2917open_card_oam(struct idt77252_dev *card) 2918{ 2919 unsigned long flags; 2920 unsigned long addr; 2921 struct vc_map *vc; 2922 int vpi, vci; 2923 int index; 2924 u32 rcte; 2925 2926 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2927 for (vci = 3; vci < 5; vci++) { 2928 index = VPCI2VC(card, vpi, vci); 2929 2930 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2931 if (!vc) { 2932 printk("%s: can't alloc vc\n", card->name); 2933 return -ENOMEM; 2934 } 2935 vc->index = index; 2936 card->vcs[index] = vc; 2937 2938 flush_rx_pool(card, &vc->rcv.rx_pool); 2939 2940 rcte = SAR_RCTE_CONNECTOPEN | 2941 SAR_RCTE_RAWCELLINTEN | 2942 SAR_RCTE_RCQ | 2943 SAR_RCTE_FBP_1; 2944 2945 addr = card->rct_base + (vc->index << 2); 2946 write_sram(card, addr, rcte); 2947 2948 spin_lock_irqsave(&card->cmd_lock, flags); 2949 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2950 SAR_REG_CMD); 2951 waitfor_idle(card); 2952 spin_unlock_irqrestore(&card->cmd_lock, flags); 2953 } 2954 } 2955 2956 return 0; 2957} 2958 2959static void 2960close_card_oam(struct idt77252_dev *card) 2961{ 2962 unsigned long flags; 2963 unsigned long addr; 2964 struct vc_map *vc; 2965 int vpi, vci; 2966 int index; 2967 2968 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2969 for (vci = 3; vci < 5; vci++) { 2970 index = VPCI2VC(card, vpi, vci); 2971 vc = card->vcs[index]; 2972 2973 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2974 2975 spin_lock_irqsave(&card->cmd_lock, flags); 2976 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2977 SAR_REG_CMD); 2978 waitfor_idle(card); 2979 spin_unlock_irqrestore(&card->cmd_lock, flags); 2980 2981 if (vc->rcv.rx_pool.count) { 2982 DPRINTK("%s: closing a VC " 2983 "with pending rx buffers.\n", 2984 card->name); 2985 2986 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2987 } 2988 } 2989 } 2990} 2991 2992static int 2993open_card_ubr0(struct idt77252_dev *card) 2994{ 2995 struct vc_map *vc; 2996 2997 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2998 if (!vc) { 2999 printk("%s: can't alloc vc\n", card->name); 3000 return -ENOMEM; 3001 } 3002 card->vcs[0] = vc; 3003 vc->class = SCHED_UBR0; 3004 3005 vc->scq = alloc_scq(card, vc->class); 3006 if (!vc->scq) { 3007 printk("%s: can't get SCQ.\n", card->name); 3008 return -ENOMEM; 3009 } 3010 3011 card->scd2vc[0] = vc; 3012 vc->scd_index = 0; 3013 vc->scq->scd = card->scd_base; 3014 3015 fill_scd(card, vc->scq, vc->class); 3016 3017 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 3018 write_sram(card, card->tct_base + 1, 0); 3019 write_sram(card, card->tct_base + 2, 0); 3020 write_sram(card, card->tct_base + 3, 0); 3021 write_sram(card, card->tct_base + 4, 0); 3022 write_sram(card, card->tct_base + 5, 0); 3023 write_sram(card, card->tct_base + 6, 0); 3024 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3025 3026 clear_bit(VCF_IDLE, &vc->flags); 3027 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3028 return 0; 3029} 3030 3031static int 3032idt77252_dev_open(struct idt77252_dev *card) 3033{ 3034 u32 conf; 3035 3036 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3037 printk("%s: SAR not yet initialized.\n", card->name); 3038 return -1; 3039 } 3040 3041 conf = SAR_CFG_RXPTH| /* enable receive path */ 3042 SAR_RX_DELAY | /* interrupt on complete PDU */ 3043 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3044 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3045 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3046 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3047 SAR_CFG_TXEN | /* transmit operation enable */ 3048 SAR_CFG_TXINT | /* interrupt on transmit status */ 3049 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3050 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3051 SAR_CFG_PHYIE /* enable PHY interrupts */ 3052 ; 3053 3054#ifdef CONFIG_ATM_IDT77252_RCV_ALL 3055 /* Test RAW cell receive. */ 3056 conf |= SAR_CFG_VPECA; 3057#endif 3058 3059 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3060 3061 if (open_card_oam(card)) { 3062 printk("%s: Error initializing OAM.\n", card->name); 3063 return -1; 3064 } 3065 3066 if (open_card_ubr0(card)) { 3067 printk("%s: Error initializing UBR0.\n", card->name); 3068 return -1; 3069 } 3070 3071 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3072 return 0; 3073} 3074 3075void 3076idt77252_dev_close(struct atm_dev *dev) 3077{ 3078 struct idt77252_dev *card = dev->dev_data; 3079 u32 conf; 3080 3081 close_card_oam(card); 3082 3083 conf = SAR_CFG_RXPTH | /* enable receive path */ 3084 SAR_RX_DELAY | /* interrupt on complete PDU */ 3085 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3086 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3087 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3088 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3089 SAR_CFG_TXEN | /* transmit operation enable */ 3090 SAR_CFG_TXINT | /* interrupt on transmit status */ 3091 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3092 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3093 ; 3094 3095 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3096 3097 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3098} 3099 3100 3101/*****************************************************************************/ 3102/* */ 3103/* Initialisation and Deinitialization of IDT77252 */ 3104/* */ 3105/*****************************************************************************/ 3106 3107 3108static void 3109deinit_card(struct idt77252_dev *card) 3110{ 3111 struct sk_buff *skb; 3112 int i, j; 3113 3114 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3115 printk("%s: SAR not yet initialized.\n", card->name); 3116 return; 3117 } 3118 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3119 3120 writel(0, SAR_REG_CFG); 3121 3122 if (card->atmdev) 3123 atm_dev_deregister(card->atmdev); 3124 3125 for (i = 0; i < 4; i++) { 3126 for (j = 0; j < FBQ_SIZE; j++) { 3127 skb = card->sbpool[i].skb[j]; 3128 if (skb) { 3129 pci_unmap_single(card->pcidev, 3130 IDT77252_PRV_PADDR(skb), 3131 (skb_end_pointer(skb) - 3132 skb->data), 3133 PCI_DMA_FROMDEVICE); 3134 card->sbpool[i].skb[j] = NULL; 3135 dev_kfree_skb(skb); 3136 } 3137 } 3138 } 3139 3140 vfree(card->soft_tst); 3141 3142 vfree(card->scd2vc); 3143 3144 vfree(card->vcs); 3145 3146 if (card->raw_cell_hnd) { 3147 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3148 card->raw_cell_hnd, card->raw_cell_paddr); 3149 } 3150 3151 if (card->rsq.base) { 3152 DIPRINTK("%s: Release RSQ ...\n", card->name); 3153 deinit_rsq(card); 3154 } 3155 3156 if (card->tsq.base) { 3157 DIPRINTK("%s: Release TSQ ...\n", card->name); 3158 deinit_tsq(card); 3159 } 3160 3161 DIPRINTK("idt77252: Release IRQ.\n"); 3162 free_irq(card->pcidev->irq, card); 3163 3164 for (i = 0; i < 4; i++) { 3165 if (card->fbq[i]) 3166 iounmap(card->fbq[i]); 3167 } 3168 3169 if (card->membase) 3170 iounmap(card->membase); 3171 3172 clear_bit(IDT77252_BIT_INIT, &card->flags); 3173 DIPRINTK("%s: Card deinitialized.\n", card->name); 3174} 3175 3176 3177static int __devinit 3178init_sram(struct idt77252_dev *card) 3179{ 3180 int i; 3181 3182 for (i = 0; i < card->sramsize; i += 4) 3183 write_sram(card, (i >> 2), 0); 3184 3185 /* set SRAM layout for THIS card */ 3186 if (card->sramsize == (512 * 1024)) { 3187 card->tct_base = SAR_SRAM_TCT_128_BASE; 3188 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3189 / SAR_SRAM_TCT_SIZE; 3190 card->rct_base = SAR_SRAM_RCT_128_BASE; 3191 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3192 / SAR_SRAM_RCT_SIZE; 3193 card->rt_base = SAR_SRAM_RT_128_BASE; 3194 card->scd_base = SAR_SRAM_SCD_128_BASE; 3195 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3196 / SAR_SRAM_SCD_SIZE; 3197 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3198 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3199 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3200 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3201 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3202 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3203 card->fifo_size = SAR_RXFD_SIZE_32K; 3204 } else { 3205 card->tct_base = SAR_SRAM_TCT_32_BASE; 3206 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3207 / SAR_SRAM_TCT_SIZE; 3208 card->rct_base = SAR_SRAM_RCT_32_BASE; 3209 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3210 / SAR_SRAM_RCT_SIZE; 3211 card->rt_base = SAR_SRAM_RT_32_BASE; 3212 card->scd_base = SAR_SRAM_SCD_32_BASE; 3213 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3214 / SAR_SRAM_SCD_SIZE; 3215 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3216 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3217 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3218 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3219 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3220 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3221 card->fifo_size = SAR_RXFD_SIZE_4K; 3222 } 3223 3224 /* Initialize TCT */ 3225 for (i = 0; i < card->tct_size; i++) { 3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3233 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3234 } 3235 3236 /* Initialize RCT */ 3237 for (i = 0; i < card->rct_size; i++) { 3238 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3239 (u32) SAR_RCTE_RAWCELLINTEN); 3240 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3241 (u32) 0); 3242 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3243 (u32) 0); 3244 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3245 (u32) 0xffffffff); 3246 } 3247 3248 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3249 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3250 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3251 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3252 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3253 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3254 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3255 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3256 3257 /* Initialize rate table */ 3258 for (i = 0; i < 256; i++) { 3259 write_sram(card, card->rt_base + i, log_to_rate[i]); 3260 } 3261 3262 for (i = 0; i < 128; i++) { 3263 unsigned int tmp; 3264 3265 tmp = rate_to_log[(i << 2) + 0] << 0; 3266 tmp |= rate_to_log[(i << 2) + 1] << 8; 3267 tmp |= rate_to_log[(i << 2) + 2] << 16; 3268 tmp |= rate_to_log[(i << 2) + 3] << 24; 3269 write_sram(card, card->rt_base + 256 + i, tmp); 3270 } 3271 3272#if 0 /* Fill RDF and AIR tables. */ 3273 for (i = 0; i < 128; i++) { 3274 unsigned int tmp; 3275 3276 tmp = RDF[0][(i << 1) + 0] << 16; 3277 tmp |= RDF[0][(i << 1) + 1] << 0; 3278 write_sram(card, card->rt_base + 512 + i, tmp); 3279 } 3280 3281 for (i = 0; i < 128; i++) { 3282 unsigned int tmp; 3283 3284 tmp = AIR[0][(i << 1) + 0] << 16; 3285 tmp |= AIR[0][(i << 1) + 1] << 0; 3286 write_sram(card, card->rt_base + 640 + i, tmp); 3287 } 3288#endif 3289 3290 IPRINTK("%s: initialize rate table ...\n", card->name); 3291 writel(card->rt_base << 2, SAR_REG_RTBL); 3292 3293 /* Initialize TSTs */ 3294 IPRINTK("%s: initialize TST ...\n", card->name); 3295 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3296 3297 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3298 write_sram(card, i, TSTE_OPC_VAR); 3299 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3300 idt77252_sram_write_errors = 1; 3301 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3302 idt77252_sram_write_errors = 0; 3303 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3304 write_sram(card, i, TSTE_OPC_VAR); 3305 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3306 idt77252_sram_write_errors = 1; 3307 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3308 idt77252_sram_write_errors = 0; 3309 3310 card->tst_index = 0; 3311 writel(card->tst[0] << 2, SAR_REG_TSTB); 3312 3313 /* Initialize ABRSTD and Receive FIFO */ 3314 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3315 writel(card->abrst_size | (card->abrst_base << 2), 3316 SAR_REG_ABRSTD); 3317 3318 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3319 writel(card->fifo_size | (card->fifo_base << 2), 3320 SAR_REG_RXFD); 3321 3322 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3323 return 0; 3324} 3325 3326static int __devinit 3327init_card(struct atm_dev *dev) 3328{ 3329 struct idt77252_dev *card = dev->dev_data; 3330 struct pci_dev *pcidev = card->pcidev; 3331 unsigned long tmpl, modl; 3332 unsigned int linkrate, rsvdcr; 3333 unsigned int tst_entries; 3334 struct net_device *tmp; 3335 char tname[10]; 3336 3337 u32 size; 3338 u_char pci_byte; 3339 u32 conf; 3340 int i, k; 3341 3342 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3343 printk("Error: SAR already initialized.\n"); 3344 return -1; 3345 } 3346 3347/*****************************************************************/ 3348/* P C I C O N F I G U R A T I O N */ 3349/*****************************************************************/ 3350 3351 /* Set PCI Retry-Timeout and TRDY timeout */ 3352 IPRINTK("%s: Checking PCI retries.\n", card->name); 3353 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3354 printk("%s: can't read PCI retry timeout.\n", card->name); 3355 deinit_card(card); 3356 return -1; 3357 } 3358 if (pci_byte != 0) { 3359 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3360 card->name, pci_byte); 3361 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3362 printk("%s: can't set PCI retry timeout.\n", 3363 card->name); 3364 deinit_card(card); 3365 return -1; 3366 } 3367 } 3368 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3369 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3370 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3371 deinit_card(card); 3372 return -1; 3373 } 3374 if (pci_byte != 0) { 3375 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3376 card->name, pci_byte); 3377 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3378 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3379 deinit_card(card); 3380 return -1; 3381 } 3382 } 3383 /* Reset Timer register */ 3384 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3385 printk("%s: resetting timer overflow.\n", card->name); 3386 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3387 } 3388 IPRINTK("%s: Request IRQ ... ", card->name); 3389 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3390 card->name, card) != 0) { 3391 printk("%s: can't allocate IRQ.\n", card->name); 3392 deinit_card(card); 3393 return -1; 3394 } 3395 IPRINTK("got %d.\n", pcidev->irq); 3396 3397/*****************************************************************/ 3398/* C H E C K A N D I N I T S R A M */ 3399/*****************************************************************/ 3400 3401 IPRINTK("%s: Initializing SRAM\n", card->name); 3402 3403 /* preset size of connecton table, so that init_sram() knows about it */ 3404 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3405 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3406 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3407#ifndef CONFIG_ATM_IDT77252_SEND_IDLE 3408 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3409#endif 3410 0; 3411 3412 if (card->sramsize == (512 * 1024)) 3413 conf |= SAR_CFG_CNTBL_1k; 3414 else 3415 conf |= SAR_CFG_CNTBL_512; 3416 3417 switch (vpibits) { 3418 case 0: 3419 conf |= SAR_CFG_VPVCS_0; 3420 break; 3421 default: 3422 case 1: 3423 conf |= SAR_CFG_VPVCS_1; 3424 break; 3425 case 2: 3426 conf |= SAR_CFG_VPVCS_2; 3427 break; 3428 case 8: 3429 conf |= SAR_CFG_VPVCS_8; 3430 break; 3431 } 3432 3433 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3434 3435 if (init_sram(card) < 0) 3436 return -1; 3437 3438/********************************************************************/ 3439/* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3440/********************************************************************/ 3441 /* Initialize TSQ */ 3442 if (0 != init_tsq(card)) { 3443 deinit_card(card); 3444 return -1; 3445 } 3446 /* Initialize RSQ */ 3447 if (0 != init_rsq(card)) { 3448 deinit_card(card); 3449 return -1; 3450 } 3451 3452 card->vpibits = vpibits; 3453 if (card->sramsize == (512 * 1024)) { 3454 card->vcibits = 10 - card->vpibits; 3455 } else { 3456 card->vcibits = 9 - card->vpibits; 3457 } 3458 3459 card->vcimask = 0; 3460 for (k = 0, i = 1; k < card->vcibits; k++) { 3461 card->vcimask |= i; 3462 i <<= 1; 3463 } 3464 3465 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3466 writel(0, SAR_REG_VPM); 3467 3468 /* Little Endian Order */ 3469 writel(0, SAR_REG_GP); 3470 3471 /* Initialize RAW Cell Handle Register */ 3472 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3473 &card->raw_cell_paddr); 3474 if (!card->raw_cell_hnd) { 3475 printk("%s: memory allocation failure.\n", card->name); 3476 deinit_card(card); 3477 return -1; 3478 } 3479 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3480 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3481 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3482 card->raw_cell_hnd); 3483 3484 size = sizeof(struct vc_map *) * card->tct_size; 3485 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3486 if (NULL == (card->vcs = vmalloc(size))) { 3487 printk("%s: memory allocation failure.\n", card->name); 3488 deinit_card(card); 3489 return -1; 3490 } 3491 memset(card->vcs, 0, size); 3492 3493 size = sizeof(struct vc_map *) * card->scd_size; 3494 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3495 card->name, size); 3496 if (NULL == (card->scd2vc = vmalloc(size))) { 3497 printk("%s: memory allocation failure.\n", card->name); 3498 deinit_card(card); 3499 return -1; 3500 } 3501 memset(card->scd2vc, 0, size); 3502 3503 size = sizeof(struct tst_info) * (card->tst_size - 2); 3504 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3505 card->name, size); 3506 if (NULL == (card->soft_tst = vmalloc(size))) { 3507 printk("%s: memory allocation failure.\n", card->name); 3508 deinit_card(card); 3509 return -1; 3510 } 3511 for (i = 0; i < card->tst_size - 2; i++) { 3512 card->soft_tst[i].tste = TSTE_OPC_VAR; 3513 card->soft_tst[i].vc = NULL; 3514 } 3515 3516 if (dev->phy == NULL) { 3517 printk("%s: No LT device defined.\n", card->name); 3518 deinit_card(card); 3519 return -1; 3520 } 3521 if (dev->phy->ioctl == NULL) { 3522 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3523 deinit_card(card); 3524 return -1; 3525 } 3526 3527#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3528 /* 3529 * this is a jhs hack to get around special functionality in the 3530 * phy driver for the atecom hardware; the functionality doesn't 3531 * exist in the linux atm suni driver 3532 * 3533 * it isn't the right way to do things, but as the guy from NIST 3534 * said, talking about their measurement of the fine structure 3535 * constant, "it's good enough for government work." 3536 */ 3537 linkrate = 149760000; 3538#endif 3539 3540 card->link_pcr = (linkrate / 8 / 53); 3541 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3542 card->name, linkrate, card->link_pcr); 3543 3544#ifdef CONFIG_ATM_IDT77252_SEND_IDLE 3545 card->utopia_pcr = card->link_pcr; 3546#else 3547 card->utopia_pcr = (160000000 / 8 / 54); 3548#endif 3549 3550 rsvdcr = 0; 3551 if (card->utopia_pcr > card->link_pcr) 3552 rsvdcr = card->utopia_pcr - card->link_pcr; 3553 3554 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3555 modl = tmpl % (unsigned long)card->utopia_pcr; 3556 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3557 if (modl) 3558 tst_entries++; 3559 card->tst_free -= tst_entries; 3560 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3561 3562#ifdef HAVE_EEPROM 3563 idt77252_eeprom_init(card); 3564 printk("%s: EEPROM: %02x:", card->name, 3565 idt77252_eeprom_read_status(card)); 3566 3567 for (i = 0; i < 0x80; i++) { 3568 printk(" %02x", 3569 idt77252_eeprom_read_byte(card, i) 3570 ); 3571 } 3572 printk("\n"); 3573#endif /* HAVE_EEPROM */ 3574 3575 /* 3576 * XXX: <hack> 3577 */ 3578 sprintf(tname, "eth%d", card->index); 3579 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */ 3580 if (tmp) { 3581 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3582 3583 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3584 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3585 card->atmdev->esi[2], card->atmdev->esi[3], 3586 card->atmdev->esi[4], card->atmdev->esi[5]); 3587 } 3588 /* 3589 * XXX: </hack> 3590 */ 3591 3592 /* Set Maximum Deficit Count for now. */ 3593 writel(0xffff, SAR_REG_MDFCT); 3594 3595 set_bit(IDT77252_BIT_INIT, &card->flags); 3596 3597 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3598 return 0; 3599} 3600 3601 3602/*****************************************************************************/ 3603/* */ 3604/* Probing of IDT77252 ABR SAR */ 3605/* */ 3606/*****************************************************************************/ 3607 3608 3609static int __devinit 3610idt77252_preset(struct idt77252_dev *card) 3611{ 3612 u16 pci_command; 3613 3614/*****************************************************************/ 3615/* P C I C O N F I G U R A T I O N */ 3616/*****************************************************************/ 3617 3618 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3619 card->name); 3620 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3621 printk("%s: can't read PCI_COMMAND.\n", card->name); 3622 deinit_card(card); 3623 return -1; 3624 } 3625 if (!(pci_command & PCI_COMMAND_IO)) { 3626 printk("%s: PCI_COMMAND: %04x (???)\n", 3627 card->name, pci_command); 3628 deinit_card(card); 3629 return (-1); 3630 } 3631 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3632 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3633 printk("%s: can't write PCI_COMMAND.\n", card->name); 3634 deinit_card(card); 3635 return -1; 3636 } 3637/*****************************************************************/ 3638/* G E N E R I C R E S E T */ 3639/*****************************************************************/ 3640 3641 /* Software reset */ 3642 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3643 mdelay(1); 3644 writel(0, SAR_REG_CFG); 3645 3646 IPRINTK("%s: Software resetted.\n", card->name); 3647 return 0; 3648} 3649 3650 3651static unsigned long __devinit 3652probe_sram(struct idt77252_dev *card) 3653{ 3654 u32 data, addr; 3655 3656 writel(0, SAR_REG_DR0); 3657 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3658 3659 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3660 writel(ATM_POISON, SAR_REG_DR0); 3661 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3662 3663 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3664 data = readl(SAR_REG_DR0); 3665 3666 if (data != 0) 3667 break; 3668 } 3669 3670 return addr * sizeof(u32); 3671} 3672 3673static int __devinit 3674idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3675{ 3676 static struct idt77252_dev **last = &idt77252_chain; 3677 static int index = 0; 3678 3679 unsigned long membase, srambase; 3680 struct idt77252_dev *card; 3681 struct atm_dev *dev; 3682 ushort revision = 0; 3683 int i, err; 3684 3685 3686 if ((err = pci_enable_device(pcidev))) { 3687 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3688 return err; 3689 } 3690 3691 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) { 3692 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index); 3693 err = -ENODEV; 3694 goto err_out_disable_pdev; 3695 } 3696 3697 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3698 if (!card) { 3699 printk("idt77252-%d: can't allocate private data\n", index); 3700 err = -ENOMEM; 3701 goto err_out_disable_pdev; 3702 } 3703 card->revision = revision; 3704 card->index = index; 3705 card->pcidev = pcidev; 3706 sprintf(card->name, "idt77252-%d", card->index); 3707 3708 INIT_WORK(&card->tqueue, idt77252_softint); 3709 3710 membase = pci_resource_start(pcidev, 1); 3711 srambase = pci_resource_start(pcidev, 2); 3712 3713 init_MUTEX(&card->mutex); 3714 spin_lock_init(&card->cmd_lock); 3715 spin_lock_init(&card->tst_lock); 3716 3717 init_timer(&card->tst_timer); 3718 card->tst_timer.data = (unsigned long)card; 3719 card->tst_timer.function = tst_timer; 3720 3721 /* Do the I/O remapping... */ 3722 card->membase = ioremap(membase, 1024); 3723 if (!card->membase) { 3724 printk("%s: can't ioremap() membase\n", card->name); 3725 err = -EIO; 3726 goto err_out_free_card; 3727 } 3728 3729 if (idt77252_preset(card)) { 3730 printk("%s: preset failed\n", card->name); 3731 err = -EIO; 3732 goto err_out_iounmap; 3733 } 3734 3735 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3736 if (!dev) { 3737 printk("%s: can't register atm device\n", card->name); 3738 err = -EIO; 3739 goto err_out_iounmap; 3740 } 3741 dev->dev_data = card; 3742 card->atmdev = dev; 3743 3744#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3745 suni_init(dev); 3746 if (!dev->phy) { 3747 printk("%s: can't init SUNI\n", card->name); 3748 err = -EIO; 3749 goto err_out_deinit_card; 3750 } 3751#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3752 3753 card->sramsize = probe_sram(card); 3754 3755 for (i = 0; i < 4; i++) { 3756 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3757 if (!card->fbq[i]) { 3758 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3759 err = -EIO; 3760 goto err_out_deinit_card; 3761 } 3762 } 3763 3764 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3765 card->name, ((revision > 1) && (revision < 25)) ? 3766 'A' + revision - 1 : '?', membase, srambase, 3767 card->sramsize / 1024); 3768 3769 if (init_card(dev)) { 3770 printk("%s: init_card failed\n", card->name); 3771 err = -EIO; 3772 goto err_out_deinit_card; 3773 } 3774 3775 dev->ci_range.vpi_bits = card->vpibits; 3776 dev->ci_range.vci_bits = card->vcibits; 3777 dev->link_rate = card->link_pcr; 3778 3779 if (dev->phy->start) 3780 dev->phy->start(dev); 3781 3782 if (idt77252_dev_open(card)) { 3783 printk("%s: dev_open failed\n", card->name); 3784 err = -EIO; 3785 goto err_out_stop; 3786 } 3787 3788 *last = card; 3789 last = &card->next; 3790 index++; 3791 3792 return 0; 3793 3794err_out_stop: 3795 if (dev->phy->stop) 3796 dev->phy->stop(dev); 3797 3798err_out_deinit_card: 3799 deinit_card(card); 3800 3801err_out_iounmap: 3802 iounmap(card->membase); 3803 3804err_out_free_card: 3805 kfree(card); 3806 3807err_out_disable_pdev: 3808 pci_disable_device(pcidev); 3809 return err; 3810} 3811 3812static struct pci_device_id idt77252_pci_tbl[] = 3813{ 3814 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3816 { 0, } 3817}; 3818 3819MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3820 3821static struct pci_driver idt77252_driver = { 3822 .name = "idt77252", 3823 .id_table = idt77252_pci_tbl, 3824 .probe = idt77252_init_one, 3825}; 3826 3827static int __init idt77252_init(void) 3828{ 3829 struct sk_buff *skb; 3830 3831 printk("%s: at %p\n", __FUNCTION__, idt77252_init); 3832 3833 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3834 sizeof(struct idt77252_skb_prv)) { 3835 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3836 __FUNCTION__, (unsigned long) sizeof(skb->cb), 3837 (unsigned long) sizeof(struct atm_skb_data) + 3838 sizeof(struct idt77252_skb_prv)); 3839 return -EIO; 3840 } 3841 3842 return pci_register_driver(&idt77252_driver); 3843} 3844 3845static void __exit idt77252_exit(void) 3846{ 3847 struct idt77252_dev *card; 3848 struct atm_dev *dev; 3849 3850 pci_unregister_driver(&idt77252_driver); 3851 3852 while (idt77252_chain) { 3853 card = idt77252_chain; 3854 dev = card->atmdev; 3855 idt77252_chain = card->next; 3856 3857 if (dev->phy->stop) 3858 dev->phy->stop(dev); 3859 deinit_card(card); 3860 pci_disable_device(card->pcidev); 3861 kfree(card); 3862 } 3863 3864 DIPRINTK("idt77252: finished cleanup-module().\n"); 3865} 3866 3867module_init(idt77252_init); 3868module_exit(idt77252_exit); 3869 3870MODULE_LICENSE("GPL"); 3871 3872module_param(vpibits, uint, 0); 3873MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3874#ifdef CONFIG_ATM_IDT77252_DEBUG 3875module_param(debug, ulong, 0644); 3876MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3877#endif 3878 3879MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3880MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3881