idt77252.c revision a6b7a407865aab9f849dd99a71072b7cd1175116
1/******************************************************************* 2 * 3 * Copyright (c) 2000 ATecoM GmbH 4 * 5 * The author may be reached at ecd@atecom.com. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 *******************************************************************/ 28 29#include <linux/module.h> 30#include <linux/pci.h> 31#include <linux/poison.h> 32#include <linux/skbuff.h> 33#include <linux/kernel.h> 34#include <linux/vmalloc.h> 35#include <linux/netdevice.h> 36#include <linux/atmdev.h> 37#include <linux/atm.h> 38#include <linux/delay.h> 39#include <linux/init.h> 40#include <linux/interrupt.h> 41#include <linux/bitops.h> 42#include <linux/wait.h> 43#include <linux/jiffies.h> 44#include <linux/mutex.h> 45#include <linux/slab.h> 46 47#include <asm/io.h> 48#include <asm/uaccess.h> 49#include <asm/atomic.h> 50#include <asm/byteorder.h> 51 52#ifdef CONFIG_ATM_IDT77252_USE_SUNI 53#include "suni.h" 54#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 55 56 57#include "idt77252.h" 58#include "idt77252_tables.h" 59 60static unsigned int vpibits = 1; 61 62 63#define ATM_IDT77252_SEND_IDLE 1 64 65 66/* 67 * Debug HACKs. 68 */ 69#define DEBUG_MODULE 1 70#undef HAVE_EEPROM /* does not work, yet. */ 71 72#ifdef CONFIG_ATM_IDT77252_DEBUG 73static unsigned long debug = DBG_GENERAL; 74#endif 75 76 77#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 78 79 80/* 81 * SCQ Handling. 82 */ 83static struct scq_info *alloc_scq(struct idt77252_dev *, int); 84static void free_scq(struct idt77252_dev *, struct scq_info *); 85static int queue_skb(struct idt77252_dev *, struct vc_map *, 86 struct sk_buff *, int oam); 87static void drain_scq(struct idt77252_dev *, struct vc_map *); 88static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 89static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 90 91/* 92 * FBQ Handling. 93 */ 94static int push_rx_skb(struct idt77252_dev *, 95 struct sk_buff *, int queue); 96static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 97static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 98static void recycle_rx_pool_skb(struct idt77252_dev *, 99 struct rx_pool *); 100static void add_rx_skb(struct idt77252_dev *, int queue, 101 unsigned int size, unsigned int count); 102 103/* 104 * RSQ Handling. 105 */ 106static int init_rsq(struct idt77252_dev *); 107static void deinit_rsq(struct idt77252_dev *); 108static void idt77252_rx(struct idt77252_dev *); 109 110/* 111 * TSQ handling. 112 */ 113static int init_tsq(struct idt77252_dev *); 114static void deinit_tsq(struct idt77252_dev *); 115static void idt77252_tx(struct idt77252_dev *); 116 117 118/* 119 * ATM Interface. 120 */ 121static void idt77252_dev_close(struct atm_dev *dev); 122static int idt77252_open(struct atm_vcc *vcc); 123static void idt77252_close(struct atm_vcc *vcc); 124static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 125static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 126 int flags); 127static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 128 unsigned long addr); 129static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 130static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 131 int flags); 132static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 133 char *page); 134static void idt77252_softint(struct work_struct *work); 135 136 137static struct atmdev_ops idt77252_ops = 138{ 139 .dev_close = idt77252_dev_close, 140 .open = idt77252_open, 141 .close = idt77252_close, 142 .send = idt77252_send, 143 .send_oam = idt77252_send_oam, 144 .phy_put = idt77252_phy_put, 145 .phy_get = idt77252_phy_get, 146 .change_qos = idt77252_change_qos, 147 .proc_read = idt77252_proc_read, 148 .owner = THIS_MODULE 149}; 150 151static struct idt77252_dev *idt77252_chain = NULL; 152static unsigned int idt77252_sram_write_errors = 0; 153 154/*****************************************************************************/ 155/* */ 156/* I/O and Utility Bus */ 157/* */ 158/*****************************************************************************/ 159 160static void 161waitfor_idle(struct idt77252_dev *card) 162{ 163 u32 stat; 164 165 stat = readl(SAR_REG_STAT); 166 while (stat & SAR_STAT_CMDBZ) 167 stat = readl(SAR_REG_STAT); 168} 169 170static u32 171read_sram(struct idt77252_dev *card, unsigned long addr) 172{ 173 unsigned long flags; 174 u32 value; 175 176 spin_lock_irqsave(&card->cmd_lock, flags); 177 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 178 waitfor_idle(card); 179 value = readl(SAR_REG_DR0); 180 spin_unlock_irqrestore(&card->cmd_lock, flags); 181 return value; 182} 183 184static void 185write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 186{ 187 unsigned long flags; 188 189 if ((idt77252_sram_write_errors == 0) && 190 (((addr > card->tst[0] + card->tst_size - 2) && 191 (addr < card->tst[0] + card->tst_size)) || 192 ((addr > card->tst[1] + card->tst_size - 2) && 193 (addr < card->tst[1] + card->tst_size)))) { 194 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 195 card->name, addr, value); 196 } 197 198 spin_lock_irqsave(&card->cmd_lock, flags); 199 writel(value, SAR_REG_DR0); 200 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 201 waitfor_idle(card); 202 spin_unlock_irqrestore(&card->cmd_lock, flags); 203} 204 205static u8 206read_utility(void *dev, unsigned long ubus_addr) 207{ 208 struct idt77252_dev *card = dev; 209 unsigned long flags; 210 u8 value; 211 212 if (!card) { 213 printk("Error: No such device.\n"); 214 return -1; 215 } 216 217 spin_lock_irqsave(&card->cmd_lock, flags); 218 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 219 waitfor_idle(card); 220 value = readl(SAR_REG_DR0); 221 spin_unlock_irqrestore(&card->cmd_lock, flags); 222 return value; 223} 224 225static void 226write_utility(void *dev, unsigned long ubus_addr, u8 value) 227{ 228 struct idt77252_dev *card = dev; 229 unsigned long flags; 230 231 if (!card) { 232 printk("Error: No such device.\n"); 233 return; 234 } 235 236 spin_lock_irqsave(&card->cmd_lock, flags); 237 writel((u32) value, SAR_REG_DR0); 238 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 239 waitfor_idle(card); 240 spin_unlock_irqrestore(&card->cmd_lock, flags); 241} 242 243#ifdef HAVE_EEPROM 244static u32 rdsrtab[] = 245{ 246 SAR_GP_EECS | SAR_GP_EESCLK, 247 0, 248 SAR_GP_EESCLK, /* 0 */ 249 0, 250 SAR_GP_EESCLK, /* 0 */ 251 0, 252 SAR_GP_EESCLK, /* 0 */ 253 0, 254 SAR_GP_EESCLK, /* 0 */ 255 0, 256 SAR_GP_EESCLK, /* 0 */ 257 SAR_GP_EEDO, 258 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 259 0, 260 SAR_GP_EESCLK, /* 0 */ 261 SAR_GP_EEDO, 262 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 263}; 264 265static u32 wrentab[] = 266{ 267 SAR_GP_EECS | SAR_GP_EESCLK, 268 0, 269 SAR_GP_EESCLK, /* 0 */ 270 0, 271 SAR_GP_EESCLK, /* 0 */ 272 0, 273 SAR_GP_EESCLK, /* 0 */ 274 0, 275 SAR_GP_EESCLK, /* 0 */ 276 SAR_GP_EEDO, 277 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 278 SAR_GP_EEDO, 279 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 280 0, 281 SAR_GP_EESCLK, /* 0 */ 282 0, 283 SAR_GP_EESCLK /* 0 */ 284}; 285 286static u32 rdtab[] = 287{ 288 SAR_GP_EECS | SAR_GP_EESCLK, 289 0, 290 SAR_GP_EESCLK, /* 0 */ 291 0, 292 SAR_GP_EESCLK, /* 0 */ 293 0, 294 SAR_GP_EESCLK, /* 0 */ 295 0, 296 SAR_GP_EESCLK, /* 0 */ 297 0, 298 SAR_GP_EESCLK, /* 0 */ 299 0, 300 SAR_GP_EESCLK, /* 0 */ 301 SAR_GP_EEDO, 302 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 303 SAR_GP_EEDO, 304 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 305}; 306 307static u32 wrtab[] = 308{ 309 SAR_GP_EECS | SAR_GP_EESCLK, 310 0, 311 SAR_GP_EESCLK, /* 0 */ 312 0, 313 SAR_GP_EESCLK, /* 0 */ 314 0, 315 SAR_GP_EESCLK, /* 0 */ 316 0, 317 SAR_GP_EESCLK, /* 0 */ 318 0, 319 SAR_GP_EESCLK, /* 0 */ 320 0, 321 SAR_GP_EESCLK, /* 0 */ 322 SAR_GP_EEDO, 323 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 324 0, 325 SAR_GP_EESCLK /* 0 */ 326}; 327 328static u32 clktab[] = 329{ 330 0, 331 SAR_GP_EESCLK, 332 0, 333 SAR_GP_EESCLK, 334 0, 335 SAR_GP_EESCLK, 336 0, 337 SAR_GP_EESCLK, 338 0, 339 SAR_GP_EESCLK, 340 0, 341 SAR_GP_EESCLK, 342 0, 343 SAR_GP_EESCLK, 344 0, 345 SAR_GP_EESCLK, 346 0 347}; 348 349static u32 350idt77252_read_gp(struct idt77252_dev *card) 351{ 352 u32 gp; 353 354 gp = readl(SAR_REG_GP); 355#if 0 356 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 357#endif 358 return gp; 359} 360 361static void 362idt77252_write_gp(struct idt77252_dev *card, u32 value) 363{ 364 unsigned long flags; 365 366#if 0 367 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 368 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 369 value & SAR_GP_EEDO ? "1" : "0"); 370#endif 371 372 spin_lock_irqsave(&card->cmd_lock, flags); 373 waitfor_idle(card); 374 writel(value, SAR_REG_GP); 375 spin_unlock_irqrestore(&card->cmd_lock, flags); 376} 377 378static u8 379idt77252_eeprom_read_status(struct idt77252_dev *card) 380{ 381 u8 byte; 382 u32 gp; 383 int i, j; 384 385 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 386 387 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 388 idt77252_write_gp(card, gp | rdsrtab[i]); 389 udelay(5); 390 } 391 idt77252_write_gp(card, gp | SAR_GP_EECS); 392 udelay(5); 393 394 byte = 0; 395 for (i = 0, j = 0; i < 8; i++) { 396 byte <<= 1; 397 398 idt77252_write_gp(card, gp | clktab[j++]); 399 udelay(5); 400 401 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 402 403 idt77252_write_gp(card, gp | clktab[j++]); 404 udelay(5); 405 } 406 idt77252_write_gp(card, gp | SAR_GP_EECS); 407 udelay(5); 408 409 return byte; 410} 411 412static u8 413idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 414{ 415 u8 byte; 416 u32 gp; 417 int i, j; 418 419 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 420 421 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 422 idt77252_write_gp(card, gp | rdtab[i]); 423 udelay(5); 424 } 425 idt77252_write_gp(card, gp | SAR_GP_EECS); 426 udelay(5); 427 428 for (i = 0, j = 0; i < 8; i++) { 429 idt77252_write_gp(card, gp | clktab[j++] | 430 (offset & 1 ? SAR_GP_EEDO : 0)); 431 udelay(5); 432 433 idt77252_write_gp(card, gp | clktab[j++] | 434 (offset & 1 ? SAR_GP_EEDO : 0)); 435 udelay(5); 436 437 offset >>= 1; 438 } 439 idt77252_write_gp(card, gp | SAR_GP_EECS); 440 udelay(5); 441 442 byte = 0; 443 for (i = 0, j = 0; i < 8; i++) { 444 byte <<= 1; 445 446 idt77252_write_gp(card, gp | clktab[j++]); 447 udelay(5); 448 449 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 450 451 idt77252_write_gp(card, gp | clktab[j++]); 452 udelay(5); 453 } 454 idt77252_write_gp(card, gp | SAR_GP_EECS); 455 udelay(5); 456 457 return byte; 458} 459 460static void 461idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 462{ 463 u32 gp; 464 int i, j; 465 466 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 467 468 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 469 idt77252_write_gp(card, gp | wrentab[i]); 470 udelay(5); 471 } 472 idt77252_write_gp(card, gp | SAR_GP_EECS); 473 udelay(5); 474 475 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 476 idt77252_write_gp(card, gp | wrtab[i]); 477 udelay(5); 478 } 479 idt77252_write_gp(card, gp | SAR_GP_EECS); 480 udelay(5); 481 482 for (i = 0, j = 0; i < 8; i++) { 483 idt77252_write_gp(card, gp | clktab[j++] | 484 (offset & 1 ? SAR_GP_EEDO : 0)); 485 udelay(5); 486 487 idt77252_write_gp(card, gp | clktab[j++] | 488 (offset & 1 ? SAR_GP_EEDO : 0)); 489 udelay(5); 490 491 offset >>= 1; 492 } 493 idt77252_write_gp(card, gp | SAR_GP_EECS); 494 udelay(5); 495 496 for (i = 0, j = 0; i < 8; i++) { 497 idt77252_write_gp(card, gp | clktab[j++] | 498 (data & 1 ? SAR_GP_EEDO : 0)); 499 udelay(5); 500 501 idt77252_write_gp(card, gp | clktab[j++] | 502 (data & 1 ? SAR_GP_EEDO : 0)); 503 udelay(5); 504 505 data >>= 1; 506 } 507 idt77252_write_gp(card, gp | SAR_GP_EECS); 508 udelay(5); 509} 510 511static void 512idt77252_eeprom_init(struct idt77252_dev *card) 513{ 514 u32 gp; 515 516 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 517 518 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 519 udelay(5); 520 idt77252_write_gp(card, gp | SAR_GP_EECS); 521 udelay(5); 522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 523 udelay(5); 524 idt77252_write_gp(card, gp | SAR_GP_EECS); 525 udelay(5); 526} 527#endif /* HAVE_EEPROM */ 528 529 530#ifdef CONFIG_ATM_IDT77252_DEBUG 531static void 532dump_tct(struct idt77252_dev *card, int index) 533{ 534 unsigned long tct; 535 int i; 536 537 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 538 539 printk("%s: TCT %x:", card->name, index); 540 for (i = 0; i < 8; i++) { 541 printk(" %08x", read_sram(card, tct + i)); 542 } 543 printk("\n"); 544} 545 546static void 547idt77252_tx_dump(struct idt77252_dev *card) 548{ 549 struct atm_vcc *vcc; 550 struct vc_map *vc; 551 int i; 552 553 printk("%s\n", __func__); 554 for (i = 0; i < card->tct_size; i++) { 555 vc = card->vcs[i]; 556 if (!vc) 557 continue; 558 559 vcc = NULL; 560 if (vc->rx_vcc) 561 vcc = vc->rx_vcc; 562 else if (vc->tx_vcc) 563 vcc = vc->tx_vcc; 564 565 if (!vcc) 566 continue; 567 568 printk("%s: Connection %d:\n", card->name, vc->index); 569 dump_tct(card, vc->index); 570 } 571} 572#endif 573 574 575/*****************************************************************************/ 576/* */ 577/* SCQ Handling */ 578/* */ 579/*****************************************************************************/ 580 581static int 582sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 583{ 584 struct sb_pool *pool = &card->sbpool[queue]; 585 int index; 586 587 index = pool->index; 588 while (pool->skb[index]) { 589 index = (index + 1) & FBQ_MASK; 590 if (index == pool->index) 591 return -ENOBUFS; 592 } 593 594 pool->skb[index] = skb; 595 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 596 597 pool->index = (index + 1) & FBQ_MASK; 598 return 0; 599} 600 601static void 602sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 603{ 604 unsigned int queue, index; 605 u32 handle; 606 607 handle = IDT77252_PRV_POOL(skb); 608 609 queue = POOL_QUEUE(handle); 610 if (queue > 3) 611 return; 612 613 index = POOL_INDEX(handle); 614 if (index > FBQ_SIZE - 1) 615 return; 616 617 card->sbpool[queue].skb[index] = NULL; 618} 619 620static struct sk_buff * 621sb_pool_skb(struct idt77252_dev *card, u32 handle) 622{ 623 unsigned int queue, index; 624 625 queue = POOL_QUEUE(handle); 626 if (queue > 3) 627 return NULL; 628 629 index = POOL_INDEX(handle); 630 if (index > FBQ_SIZE - 1) 631 return NULL; 632 633 return card->sbpool[queue].skb[index]; 634} 635 636static struct scq_info * 637alloc_scq(struct idt77252_dev *card, int class) 638{ 639 struct scq_info *scq; 640 641 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 642 if (!scq) 643 return NULL; 644 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 645 &scq->paddr); 646 if (scq->base == NULL) { 647 kfree(scq); 648 return NULL; 649 } 650 memset(scq->base, 0, SCQ_SIZE); 651 652 scq->next = scq->base; 653 scq->last = scq->base + (SCQ_ENTRIES - 1); 654 atomic_set(&scq->used, 0); 655 656 spin_lock_init(&scq->lock); 657 spin_lock_init(&scq->skblock); 658 659 skb_queue_head_init(&scq->transmit); 660 skb_queue_head_init(&scq->pending); 661 662 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 663 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 664 665 return scq; 666} 667 668static void 669free_scq(struct idt77252_dev *card, struct scq_info *scq) 670{ 671 struct sk_buff *skb; 672 struct atm_vcc *vcc; 673 674 pci_free_consistent(card->pcidev, SCQ_SIZE, 675 scq->base, scq->paddr); 676 677 while ((skb = skb_dequeue(&scq->transmit))) { 678 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 679 skb->len, PCI_DMA_TODEVICE); 680 681 vcc = ATM_SKB(skb)->vcc; 682 if (vcc->pop) 683 vcc->pop(vcc, skb); 684 else 685 dev_kfree_skb(skb); 686 } 687 688 while ((skb = skb_dequeue(&scq->pending))) { 689 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 690 skb->len, PCI_DMA_TODEVICE); 691 692 vcc = ATM_SKB(skb)->vcc; 693 if (vcc->pop) 694 vcc->pop(vcc, skb); 695 else 696 dev_kfree_skb(skb); 697 } 698 699 kfree(scq); 700} 701 702 703static int 704push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 705{ 706 struct scq_info *scq = vc->scq; 707 unsigned long flags; 708 struct scqe *tbd; 709 int entries; 710 711 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 712 713 atomic_inc(&scq->used); 714 entries = atomic_read(&scq->used); 715 if (entries > (SCQ_ENTRIES - 1)) { 716 atomic_dec(&scq->used); 717 goto out; 718 } 719 720 skb_queue_tail(&scq->transmit, skb); 721 722 spin_lock_irqsave(&vc->lock, flags); 723 if (vc->estimator) { 724 struct atm_vcc *vcc = vc->tx_vcc; 725 struct sock *sk = sk_atm(vcc); 726 727 vc->estimator->cells += (skb->len + 47) / 48; 728 if (atomic_read(&sk->sk_wmem_alloc) > 729 (sk->sk_sndbuf >> 1)) { 730 u32 cps = vc->estimator->maxcps; 731 732 vc->estimator->cps = cps; 733 vc->estimator->avcps = cps << 5; 734 if (vc->lacr < vc->init_er) { 735 vc->lacr = vc->init_er; 736 writel(TCMDQ_LACR | (vc->lacr << 16) | 737 vc->index, SAR_REG_TCMDQ); 738 } 739 } 740 } 741 spin_unlock_irqrestore(&vc->lock, flags); 742 743 tbd = &IDT77252_PRV_TBD(skb); 744 745 spin_lock_irqsave(&scq->lock, flags); 746 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 747 SAR_TBD_TSIF | SAR_TBD_GTSI); 748 scq->next->word_2 = cpu_to_le32(tbd->word_2); 749 scq->next->word_3 = cpu_to_le32(tbd->word_3); 750 scq->next->word_4 = cpu_to_le32(tbd->word_4); 751 752 if (scq->next == scq->last) 753 scq->next = scq->base; 754 else 755 scq->next++; 756 757 write_sram(card, scq->scd, 758 scq->paddr + 759 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 760 spin_unlock_irqrestore(&scq->lock, flags); 761 762 scq->trans_start = jiffies; 763 764 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 765 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 766 SAR_REG_TCMDQ); 767 } 768 769 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 770 771 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 772 card->name, atomic_read(&scq->used), 773 read_sram(card, scq->scd + 1), scq->next); 774 775 return 0; 776 777out: 778 if (time_after(jiffies, scq->trans_start + HZ)) { 779 printk("%s: Error pushing TBD for %d.%d\n", 780 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 781#ifdef CONFIG_ATM_IDT77252_DEBUG 782 idt77252_tx_dump(card); 783#endif 784 scq->trans_start = jiffies; 785 } 786 787 return -ENOBUFS; 788} 789 790 791static void 792drain_scq(struct idt77252_dev *card, struct vc_map *vc) 793{ 794 struct scq_info *scq = vc->scq; 795 struct sk_buff *skb; 796 struct atm_vcc *vcc; 797 798 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 799 card->name, atomic_read(&scq->used), scq->next); 800 801 skb = skb_dequeue(&scq->transmit); 802 if (skb) { 803 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 804 805 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 806 skb->len, PCI_DMA_TODEVICE); 807 808 vcc = ATM_SKB(skb)->vcc; 809 810 if (vcc->pop) 811 vcc->pop(vcc, skb); 812 else 813 dev_kfree_skb(skb); 814 815 atomic_inc(&vcc->stats->tx); 816 } 817 818 atomic_dec(&scq->used); 819 820 spin_lock(&scq->skblock); 821 while ((skb = skb_dequeue(&scq->pending))) { 822 if (push_on_scq(card, vc, skb)) { 823 skb_queue_head(&vc->scq->pending, skb); 824 break; 825 } 826 } 827 spin_unlock(&scq->skblock); 828} 829 830static int 831queue_skb(struct idt77252_dev *card, struct vc_map *vc, 832 struct sk_buff *skb, int oam) 833{ 834 struct atm_vcc *vcc; 835 struct scqe *tbd; 836 unsigned long flags; 837 int error; 838 int aal; 839 840 if (skb->len == 0) { 841 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 842 return -EINVAL; 843 } 844 845 TXPRINTK("%s: Sending %d bytes of data.\n", 846 card->name, skb->len); 847 848 tbd = &IDT77252_PRV_TBD(skb); 849 vcc = ATM_SKB(skb)->vcc; 850 851 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 852 skb->len, PCI_DMA_TODEVICE); 853 854 error = -EINVAL; 855 856 if (oam) { 857 if (skb->len != 52) 858 goto errout; 859 860 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 861 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 862 tbd->word_3 = 0x00000000; 863 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 864 (skb->data[2] << 8) | (skb->data[3] << 0); 865 866 if (test_bit(VCF_RSV, &vc->flags)) 867 vc = card->vcs[0]; 868 869 goto done; 870 } 871 872 if (test_bit(VCF_RSV, &vc->flags)) { 873 printk("%s: Trying to transmit on reserved VC\n", card->name); 874 goto errout; 875 } 876 877 aal = vcc->qos.aal; 878 879 switch (aal) { 880 case ATM_AAL0: 881 case ATM_AAL34: 882 if (skb->len > 52) 883 goto errout; 884 885 if (aal == ATM_AAL0) 886 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 887 ATM_CELL_PAYLOAD; 888 else 889 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 890 ATM_CELL_PAYLOAD; 891 892 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 893 tbd->word_3 = 0x00000000; 894 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 895 (skb->data[2] << 8) | (skb->data[3] << 0); 896 break; 897 898 case ATM_AAL5: 899 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 900 tbd->word_2 = IDT77252_PRV_PADDR(skb); 901 tbd->word_3 = skb->len; 902 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 903 (vcc->vci << SAR_TBD_VCI_SHIFT); 904 break; 905 906 case ATM_AAL1: 907 case ATM_AAL2: 908 default: 909 printk("%s: Traffic type not supported.\n", card->name); 910 error = -EPROTONOSUPPORT; 911 goto errout; 912 } 913 914done: 915 spin_lock_irqsave(&vc->scq->skblock, flags); 916 skb_queue_tail(&vc->scq->pending, skb); 917 918 while ((skb = skb_dequeue(&vc->scq->pending))) { 919 if (push_on_scq(card, vc, skb)) { 920 skb_queue_head(&vc->scq->pending, skb); 921 break; 922 } 923 } 924 spin_unlock_irqrestore(&vc->scq->skblock, flags); 925 926 return 0; 927 928errout: 929 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 930 skb->len, PCI_DMA_TODEVICE); 931 return error; 932} 933 934static unsigned long 935get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 936{ 937 int i; 938 939 for (i = 0; i < card->scd_size; i++) { 940 if (!card->scd2vc[i]) { 941 card->scd2vc[i] = vc; 942 vc->scd_index = i; 943 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 944 } 945 } 946 return 0; 947} 948 949static void 950fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 951{ 952 write_sram(card, scq->scd, scq->paddr); 953 write_sram(card, scq->scd + 1, 0x00000000); 954 write_sram(card, scq->scd + 2, 0xffffffff); 955 write_sram(card, scq->scd + 3, 0x00000000); 956} 957 958static void 959clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 960{ 961 return; 962} 963 964/*****************************************************************************/ 965/* */ 966/* RSQ Handling */ 967/* */ 968/*****************************************************************************/ 969 970static int 971init_rsq(struct idt77252_dev *card) 972{ 973 struct rsq_entry *rsqe; 974 975 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 976 &card->rsq.paddr); 977 if (card->rsq.base == NULL) { 978 printk("%s: can't allocate RSQ.\n", card->name); 979 return -1; 980 } 981 memset(card->rsq.base, 0, RSQSIZE); 982 983 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 984 card->rsq.next = card->rsq.last; 985 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 986 rsqe->word_4 = 0; 987 988 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 989 SAR_REG_RSQH); 990 writel(card->rsq.paddr, SAR_REG_RSQB); 991 992 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 993 (unsigned long) card->rsq.base, 994 readl(SAR_REG_RSQB)); 995 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 996 card->name, 997 readl(SAR_REG_RSQH), 998 readl(SAR_REG_RSQB), 999 readl(SAR_REG_RSQT)); 1000 1001 return 0; 1002} 1003 1004static void 1005deinit_rsq(struct idt77252_dev *card) 1006{ 1007 pci_free_consistent(card->pcidev, RSQSIZE, 1008 card->rsq.base, card->rsq.paddr); 1009} 1010 1011static void 1012dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1013{ 1014 struct atm_vcc *vcc; 1015 struct sk_buff *skb; 1016 struct rx_pool *rpp; 1017 struct vc_map *vc; 1018 u32 header, vpi, vci; 1019 u32 stat; 1020 int i; 1021 1022 stat = le32_to_cpu(rsqe->word_4); 1023 1024 if (stat & SAR_RSQE_IDLE) { 1025 RXPRINTK("%s: message about inactive connection.\n", 1026 card->name); 1027 return; 1028 } 1029 1030 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1031 if (skb == NULL) { 1032 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1033 card->name, __func__, 1034 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1035 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1036 return; 1037 } 1038 1039 header = le32_to_cpu(rsqe->word_1); 1040 vpi = (header >> 16) & 0x00ff; 1041 vci = (header >> 0) & 0xffff; 1042 1043 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1044 card->name, vpi, vci, skb, skb->data); 1045 1046 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1047 printk("%s: SDU received for out-of-range vc %u.%u\n", 1048 card->name, vpi, vci); 1049 recycle_rx_skb(card, skb); 1050 return; 1051 } 1052 1053 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1054 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1055 printk("%s: SDU received on non RX vc %u.%u\n", 1056 card->name, vpi, vci); 1057 recycle_rx_skb(card, skb); 1058 return; 1059 } 1060 1061 vcc = vc->rx_vcc; 1062 1063 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1064 skb_end_pointer(skb) - skb->data, 1065 PCI_DMA_FROMDEVICE); 1066 1067 if ((vcc->qos.aal == ATM_AAL0) || 1068 (vcc->qos.aal == ATM_AAL34)) { 1069 struct sk_buff *sb; 1070 unsigned char *cell; 1071 u32 aal0; 1072 1073 cell = skb->data; 1074 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1075 if ((sb = dev_alloc_skb(64)) == NULL) { 1076 printk("%s: Can't allocate buffers for aal0.\n", 1077 card->name); 1078 atomic_add(i, &vcc->stats->rx_drop); 1079 break; 1080 } 1081 if (!atm_charge(vcc, sb->truesize)) { 1082 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1083 card->name); 1084 atomic_add(i - 1, &vcc->stats->rx_drop); 1085 dev_kfree_skb(sb); 1086 break; 1087 } 1088 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1089 (vci << ATM_HDR_VCI_SHIFT); 1090 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1091 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1092 1093 *((u32 *) sb->data) = aal0; 1094 skb_put(sb, sizeof(u32)); 1095 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1096 cell, ATM_CELL_PAYLOAD); 1097 1098 ATM_SKB(sb)->vcc = vcc; 1099 __net_timestamp(sb); 1100 vcc->push(vcc, sb); 1101 atomic_inc(&vcc->stats->rx); 1102 1103 cell += ATM_CELL_PAYLOAD; 1104 } 1105 1106 recycle_rx_skb(card, skb); 1107 return; 1108 } 1109 if (vcc->qos.aal != ATM_AAL5) { 1110 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1111 card->name, vcc->qos.aal); 1112 recycle_rx_skb(card, skb); 1113 return; 1114 } 1115 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1116 1117 rpp = &vc->rcv.rx_pool; 1118 1119 __skb_queue_tail(&rpp->queue, skb); 1120 rpp->len += skb->len; 1121 1122 if (stat & SAR_RSQE_EPDU) { 1123 unsigned char *l1l2; 1124 unsigned int len; 1125 1126 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1127 1128 len = (l1l2[0] << 8) | l1l2[1]; 1129 len = len ? len : 0x10000; 1130 1131 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1132 1133 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1134 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1135 "(CDC: %08x)\n", 1136 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1137 recycle_rx_pool_skb(card, rpp); 1138 atomic_inc(&vcc->stats->rx_err); 1139 return; 1140 } 1141 if (stat & SAR_RSQE_CRC) { 1142 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1143 recycle_rx_pool_skb(card, rpp); 1144 atomic_inc(&vcc->stats->rx_err); 1145 return; 1146 } 1147 if (skb_queue_len(&rpp->queue) > 1) { 1148 struct sk_buff *sb; 1149 1150 skb = dev_alloc_skb(rpp->len); 1151 if (!skb) { 1152 RXPRINTK("%s: Can't alloc RX skb.\n", 1153 card->name); 1154 recycle_rx_pool_skb(card, rpp); 1155 atomic_inc(&vcc->stats->rx_err); 1156 return; 1157 } 1158 if (!atm_charge(vcc, skb->truesize)) { 1159 recycle_rx_pool_skb(card, rpp); 1160 dev_kfree_skb(skb); 1161 return; 1162 } 1163 skb_queue_walk(&rpp->queue, sb) 1164 memcpy(skb_put(skb, sb->len), 1165 sb->data, sb->len); 1166 1167 recycle_rx_pool_skb(card, rpp); 1168 1169 skb_trim(skb, len); 1170 ATM_SKB(skb)->vcc = vcc; 1171 __net_timestamp(skb); 1172 1173 vcc->push(vcc, skb); 1174 atomic_inc(&vcc->stats->rx); 1175 1176 return; 1177 } 1178 1179 flush_rx_pool(card, rpp); 1180 1181 if (!atm_charge(vcc, skb->truesize)) { 1182 recycle_rx_skb(card, skb); 1183 return; 1184 } 1185 1186 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1187 skb_end_pointer(skb) - skb->data, 1188 PCI_DMA_FROMDEVICE); 1189 sb_pool_remove(card, skb); 1190 1191 skb_trim(skb, len); 1192 ATM_SKB(skb)->vcc = vcc; 1193 __net_timestamp(skb); 1194 1195 vcc->push(vcc, skb); 1196 atomic_inc(&vcc->stats->rx); 1197 1198 if (skb->truesize > SAR_FB_SIZE_3) 1199 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1200 else if (skb->truesize > SAR_FB_SIZE_2) 1201 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1202 else if (skb->truesize > SAR_FB_SIZE_1) 1203 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1204 else 1205 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1206 return; 1207 } 1208} 1209 1210static void 1211idt77252_rx(struct idt77252_dev *card) 1212{ 1213 struct rsq_entry *rsqe; 1214 1215 if (card->rsq.next == card->rsq.last) 1216 rsqe = card->rsq.base; 1217 else 1218 rsqe = card->rsq.next + 1; 1219 1220 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1221 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1222 return; 1223 } 1224 1225 do { 1226 dequeue_rx(card, rsqe); 1227 rsqe->word_4 = 0; 1228 card->rsq.next = rsqe; 1229 if (card->rsq.next == card->rsq.last) 1230 rsqe = card->rsq.base; 1231 else 1232 rsqe = card->rsq.next + 1; 1233 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1234 1235 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1236 SAR_REG_RSQH); 1237} 1238 1239static void 1240idt77252_rx_raw(struct idt77252_dev *card) 1241{ 1242 struct sk_buff *queue; 1243 u32 head, tail; 1244 struct atm_vcc *vcc; 1245 struct vc_map *vc; 1246 struct sk_buff *sb; 1247 1248 if (card->raw_cell_head == NULL) { 1249 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1250 card->raw_cell_head = sb_pool_skb(card, handle); 1251 } 1252 1253 queue = card->raw_cell_head; 1254 if (!queue) 1255 return; 1256 1257 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1258 tail = readl(SAR_REG_RAWCT); 1259 1260 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1261 skb_end_pointer(queue) - queue->head - 16, 1262 PCI_DMA_FROMDEVICE); 1263 1264 while (head != tail) { 1265 unsigned int vpi, vci; 1266 u32 header; 1267 1268 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1269 1270 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1271 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1272 1273#ifdef CONFIG_ATM_IDT77252_DEBUG 1274 if (debug & DBG_RAW_CELL) { 1275 int i; 1276 1277 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1278 card->name, (header >> 28) & 0x000f, 1279 (header >> 20) & 0x00ff, 1280 (header >> 4) & 0xffff, 1281 (header >> 1) & 0x0007, 1282 (header >> 0) & 0x0001); 1283 for (i = 16; i < 64; i++) 1284 printk(" %02x", queue->data[i]); 1285 printk("\n"); 1286 } 1287#endif 1288 1289 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1290 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1291 card->name, vpi, vci); 1292 goto drop; 1293 } 1294 1295 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1296 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1297 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1298 card->name, vpi, vci); 1299 goto drop; 1300 } 1301 1302 vcc = vc->rx_vcc; 1303 1304 if (vcc->qos.aal != ATM_AAL0) { 1305 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1306 card->name, vpi, vci); 1307 atomic_inc(&vcc->stats->rx_drop); 1308 goto drop; 1309 } 1310 1311 if ((sb = dev_alloc_skb(64)) == NULL) { 1312 printk("%s: Can't allocate buffers for AAL0.\n", 1313 card->name); 1314 atomic_inc(&vcc->stats->rx_err); 1315 goto drop; 1316 } 1317 1318 if (!atm_charge(vcc, sb->truesize)) { 1319 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1320 card->name); 1321 dev_kfree_skb(sb); 1322 goto drop; 1323 } 1324 1325 *((u32 *) sb->data) = header; 1326 skb_put(sb, sizeof(u32)); 1327 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1328 ATM_CELL_PAYLOAD); 1329 1330 ATM_SKB(sb)->vcc = vcc; 1331 __net_timestamp(sb); 1332 vcc->push(vcc, sb); 1333 atomic_inc(&vcc->stats->rx); 1334 1335drop: 1336 skb_pull(queue, 64); 1337 1338 head = IDT77252_PRV_PADDR(queue) 1339 + (queue->data - queue->head - 16); 1340 1341 if (queue->len < 128) { 1342 struct sk_buff *next; 1343 u32 handle; 1344 1345 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1346 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1347 1348 next = sb_pool_skb(card, handle); 1349 recycle_rx_skb(card, queue); 1350 1351 if (next) { 1352 card->raw_cell_head = next; 1353 queue = card->raw_cell_head; 1354 pci_dma_sync_single_for_cpu(card->pcidev, 1355 IDT77252_PRV_PADDR(queue), 1356 (skb_end_pointer(queue) - 1357 queue->data), 1358 PCI_DMA_FROMDEVICE); 1359 } else { 1360 card->raw_cell_head = NULL; 1361 printk("%s: raw cell queue overrun\n", 1362 card->name); 1363 break; 1364 } 1365 } 1366 } 1367} 1368 1369 1370/*****************************************************************************/ 1371/* */ 1372/* TSQ Handling */ 1373/* */ 1374/*****************************************************************************/ 1375 1376static int 1377init_tsq(struct idt77252_dev *card) 1378{ 1379 struct tsq_entry *tsqe; 1380 1381 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1382 &card->tsq.paddr); 1383 if (card->tsq.base == NULL) { 1384 printk("%s: can't allocate TSQ.\n", card->name); 1385 return -1; 1386 } 1387 memset(card->tsq.base, 0, TSQSIZE); 1388 1389 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1390 card->tsq.next = card->tsq.last; 1391 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1392 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1393 1394 writel(card->tsq.paddr, SAR_REG_TSQB); 1395 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1396 SAR_REG_TSQH); 1397 1398 return 0; 1399} 1400 1401static void 1402deinit_tsq(struct idt77252_dev *card) 1403{ 1404 pci_free_consistent(card->pcidev, TSQSIZE, 1405 card->tsq.base, card->tsq.paddr); 1406} 1407 1408static void 1409idt77252_tx(struct idt77252_dev *card) 1410{ 1411 struct tsq_entry *tsqe; 1412 unsigned int vpi, vci; 1413 struct vc_map *vc; 1414 u32 conn, stat; 1415 1416 if (card->tsq.next == card->tsq.last) 1417 tsqe = card->tsq.base; 1418 else 1419 tsqe = card->tsq.next + 1; 1420 1421 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1422 card->tsq.base, card->tsq.next, card->tsq.last); 1423 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1424 readl(SAR_REG_TSQB), 1425 readl(SAR_REG_TSQT), 1426 readl(SAR_REG_TSQH)); 1427 1428 stat = le32_to_cpu(tsqe->word_2); 1429 1430 if (stat & SAR_TSQE_INVALID) 1431 return; 1432 1433 do { 1434 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1435 le32_to_cpu(tsqe->word_1), 1436 le32_to_cpu(tsqe->word_2)); 1437 1438 switch (stat & SAR_TSQE_TYPE) { 1439 case SAR_TSQE_TYPE_TIMER: 1440 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1441 break; 1442 1443 case SAR_TSQE_TYPE_IDLE: 1444 1445 conn = le32_to_cpu(tsqe->word_1); 1446 1447 if (SAR_TSQE_TAG(stat) == 0x10) { 1448#ifdef NOTDEF 1449 printk("%s: Connection %d halted.\n", 1450 card->name, 1451 le32_to_cpu(tsqe->word_1) & 0x1fff); 1452#endif 1453 break; 1454 } 1455 1456 vc = card->vcs[conn & 0x1fff]; 1457 if (!vc) { 1458 printk("%s: could not find VC from conn %d\n", 1459 card->name, conn & 0x1fff); 1460 break; 1461 } 1462 1463 printk("%s: Connection %d IDLE.\n", 1464 card->name, vc->index); 1465 1466 set_bit(VCF_IDLE, &vc->flags); 1467 break; 1468 1469 case SAR_TSQE_TYPE_TSR: 1470 1471 conn = le32_to_cpu(tsqe->word_1); 1472 1473 vc = card->vcs[conn & 0x1fff]; 1474 if (!vc) { 1475 printk("%s: no VC at index %d\n", 1476 card->name, 1477 le32_to_cpu(tsqe->word_1) & 0x1fff); 1478 break; 1479 } 1480 1481 drain_scq(card, vc); 1482 break; 1483 1484 case SAR_TSQE_TYPE_TBD_COMP: 1485 1486 conn = le32_to_cpu(tsqe->word_1); 1487 1488 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1489 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1490 1491 if (vpi >= (1 << card->vpibits) || 1492 vci >= (1 << card->vcibits)) { 1493 printk("%s: TBD complete: " 1494 "out of range VPI.VCI %u.%u\n", 1495 card->name, vpi, vci); 1496 break; 1497 } 1498 1499 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1500 if (!vc) { 1501 printk("%s: TBD complete: " 1502 "no VC at VPI.VCI %u.%u\n", 1503 card->name, vpi, vci); 1504 break; 1505 } 1506 1507 drain_scq(card, vc); 1508 break; 1509 } 1510 1511 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1512 1513 card->tsq.next = tsqe; 1514 if (card->tsq.next == card->tsq.last) 1515 tsqe = card->tsq.base; 1516 else 1517 tsqe = card->tsq.next + 1; 1518 1519 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1520 card->tsq.base, card->tsq.next, card->tsq.last); 1521 1522 stat = le32_to_cpu(tsqe->word_2); 1523 1524 } while (!(stat & SAR_TSQE_INVALID)); 1525 1526 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1527 SAR_REG_TSQH); 1528 1529 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1530 card->index, readl(SAR_REG_TSQH), 1531 readl(SAR_REG_TSQT), card->tsq.next); 1532} 1533 1534 1535static void 1536tst_timer(unsigned long data) 1537{ 1538 struct idt77252_dev *card = (struct idt77252_dev *)data; 1539 unsigned long base, idle, jump; 1540 unsigned long flags; 1541 u32 pc; 1542 int e; 1543 1544 spin_lock_irqsave(&card->tst_lock, flags); 1545 1546 base = card->tst[card->tst_index]; 1547 idle = card->tst[card->tst_index ^ 1]; 1548 1549 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1550 jump = base + card->tst_size - 2; 1551 1552 pc = readl(SAR_REG_NOW) >> 2; 1553 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1554 mod_timer(&card->tst_timer, jiffies + 1); 1555 goto out; 1556 } 1557 1558 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1559 1560 card->tst_index ^= 1; 1561 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1562 1563 base = card->tst[card->tst_index]; 1564 idle = card->tst[card->tst_index ^ 1]; 1565 1566 for (e = 0; e < card->tst_size - 2; e++) { 1567 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1568 write_sram(card, idle + e, 1569 card->soft_tst[e].tste & TSTE_MASK); 1570 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1571 } 1572 } 1573 } 1574 1575 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1576 1577 for (e = 0; e < card->tst_size - 2; e++) { 1578 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1579 write_sram(card, idle + e, 1580 card->soft_tst[e].tste & TSTE_MASK); 1581 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1582 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1583 } 1584 } 1585 1586 jump = base + card->tst_size - 2; 1587 1588 write_sram(card, jump, TSTE_OPC_NULL); 1589 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1590 1591 mod_timer(&card->tst_timer, jiffies + 1); 1592 } 1593 1594out: 1595 spin_unlock_irqrestore(&card->tst_lock, flags); 1596} 1597 1598static int 1599__fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1600 int n, unsigned int opc) 1601{ 1602 unsigned long cl, avail; 1603 unsigned long idle; 1604 int e, r; 1605 u32 data; 1606 1607 avail = card->tst_size - 2; 1608 for (e = 0; e < avail; e++) { 1609 if (card->soft_tst[e].vc == NULL) 1610 break; 1611 } 1612 if (e >= avail) { 1613 printk("%s: No free TST entries found\n", card->name); 1614 return -1; 1615 } 1616 1617 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1618 card->name, vc ? vc->index : -1, e); 1619 1620 r = n; 1621 cl = avail; 1622 data = opc & TSTE_OPC_MASK; 1623 if (vc && (opc != TSTE_OPC_NULL)) 1624 data = opc | vc->index; 1625 1626 idle = card->tst[card->tst_index ^ 1]; 1627 1628 /* 1629 * Fill Soft TST. 1630 */ 1631 while (r > 0) { 1632 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1633 if (vc) 1634 card->soft_tst[e].vc = vc; 1635 else 1636 card->soft_tst[e].vc = (void *)-1; 1637 1638 card->soft_tst[e].tste = data; 1639 if (timer_pending(&card->tst_timer)) 1640 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1641 else { 1642 write_sram(card, idle + e, data); 1643 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1644 } 1645 1646 cl -= card->tst_size; 1647 r--; 1648 } 1649 1650 if (++e == avail) 1651 e = 0; 1652 cl += n; 1653 } 1654 1655 return 0; 1656} 1657 1658static int 1659fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1660{ 1661 unsigned long flags; 1662 int res; 1663 1664 spin_lock_irqsave(&card->tst_lock, flags); 1665 1666 res = __fill_tst(card, vc, n, opc); 1667 1668 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1669 if (!timer_pending(&card->tst_timer)) 1670 mod_timer(&card->tst_timer, jiffies + 1); 1671 1672 spin_unlock_irqrestore(&card->tst_lock, flags); 1673 return res; 1674} 1675 1676static int 1677__clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1678{ 1679 unsigned long idle; 1680 int e; 1681 1682 idle = card->tst[card->tst_index ^ 1]; 1683 1684 for (e = 0; e < card->tst_size - 2; e++) { 1685 if (card->soft_tst[e].vc == vc) { 1686 card->soft_tst[e].vc = NULL; 1687 1688 card->soft_tst[e].tste = TSTE_OPC_VAR; 1689 if (timer_pending(&card->tst_timer)) 1690 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1691 else { 1692 write_sram(card, idle + e, TSTE_OPC_VAR); 1693 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1694 } 1695 } 1696 } 1697 1698 return 0; 1699} 1700 1701static int 1702clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1703{ 1704 unsigned long flags; 1705 int res; 1706 1707 spin_lock_irqsave(&card->tst_lock, flags); 1708 1709 res = __clear_tst(card, vc); 1710 1711 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1712 if (!timer_pending(&card->tst_timer)) 1713 mod_timer(&card->tst_timer, jiffies + 1); 1714 1715 spin_unlock_irqrestore(&card->tst_lock, flags); 1716 return res; 1717} 1718 1719static int 1720change_tst(struct idt77252_dev *card, struct vc_map *vc, 1721 int n, unsigned int opc) 1722{ 1723 unsigned long flags; 1724 int res; 1725 1726 spin_lock_irqsave(&card->tst_lock, flags); 1727 1728 __clear_tst(card, vc); 1729 res = __fill_tst(card, vc, n, opc); 1730 1731 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1732 if (!timer_pending(&card->tst_timer)) 1733 mod_timer(&card->tst_timer, jiffies + 1); 1734 1735 spin_unlock_irqrestore(&card->tst_lock, flags); 1736 return res; 1737} 1738 1739 1740static int 1741set_tct(struct idt77252_dev *card, struct vc_map *vc) 1742{ 1743 unsigned long tct; 1744 1745 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1746 1747 switch (vc->class) { 1748 case SCHED_CBR: 1749 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1750 card->name, tct, vc->scq->scd); 1751 1752 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1753 write_sram(card, tct + 1, 0); 1754 write_sram(card, tct + 2, 0); 1755 write_sram(card, tct + 3, 0); 1756 write_sram(card, tct + 4, 0); 1757 write_sram(card, tct + 5, 0); 1758 write_sram(card, tct + 6, 0); 1759 write_sram(card, tct + 7, 0); 1760 break; 1761 1762 case SCHED_UBR: 1763 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1764 card->name, tct, vc->scq->scd); 1765 1766 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1767 write_sram(card, tct + 1, 0); 1768 write_sram(card, tct + 2, TCT_TSIF); 1769 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1770 write_sram(card, tct + 4, 0); 1771 write_sram(card, tct + 5, vc->init_er); 1772 write_sram(card, tct + 6, 0); 1773 write_sram(card, tct + 7, TCT_FLAG_UBR); 1774 break; 1775 1776 case SCHED_VBR: 1777 case SCHED_ABR: 1778 default: 1779 return -ENOSYS; 1780 } 1781 1782 return 0; 1783} 1784 1785/*****************************************************************************/ 1786/* */ 1787/* FBQ Handling */ 1788/* */ 1789/*****************************************************************************/ 1790 1791static __inline__ int 1792idt77252_fbq_level(struct idt77252_dev *card, int queue) 1793{ 1794 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1795} 1796 1797static __inline__ int 1798idt77252_fbq_full(struct idt77252_dev *card, int queue) 1799{ 1800 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1801} 1802 1803static int 1804push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1805{ 1806 unsigned long flags; 1807 u32 handle; 1808 u32 addr; 1809 1810 skb->data = skb->head; 1811 skb_reset_tail_pointer(skb); 1812 skb->len = 0; 1813 1814 skb_reserve(skb, 16); 1815 1816 switch (queue) { 1817 case 0: 1818 skb_put(skb, SAR_FB_SIZE_0); 1819 break; 1820 case 1: 1821 skb_put(skb, SAR_FB_SIZE_1); 1822 break; 1823 case 2: 1824 skb_put(skb, SAR_FB_SIZE_2); 1825 break; 1826 case 3: 1827 skb_put(skb, SAR_FB_SIZE_3); 1828 break; 1829 default: 1830 return -1; 1831 } 1832 1833 if (idt77252_fbq_full(card, queue)) 1834 return -1; 1835 1836 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1837 1838 handle = IDT77252_PRV_POOL(skb); 1839 addr = IDT77252_PRV_PADDR(skb); 1840 1841 spin_lock_irqsave(&card->cmd_lock, flags); 1842 writel(handle, card->fbq[queue]); 1843 writel(addr, card->fbq[queue]); 1844 spin_unlock_irqrestore(&card->cmd_lock, flags); 1845 1846 return 0; 1847} 1848 1849static void 1850add_rx_skb(struct idt77252_dev *card, int queue, 1851 unsigned int size, unsigned int count) 1852{ 1853 struct sk_buff *skb; 1854 dma_addr_t paddr; 1855 u32 handle; 1856 1857 while (count--) { 1858 skb = dev_alloc_skb(size); 1859 if (!skb) 1860 return; 1861 1862 if (sb_pool_add(card, skb, queue)) { 1863 printk("%s: SB POOL full\n", __func__); 1864 goto outfree; 1865 } 1866 1867 paddr = pci_map_single(card->pcidev, skb->data, 1868 skb_end_pointer(skb) - skb->data, 1869 PCI_DMA_FROMDEVICE); 1870 IDT77252_PRV_PADDR(skb) = paddr; 1871 1872 if (push_rx_skb(card, skb, queue)) { 1873 printk("%s: FB QUEUE full\n", __func__); 1874 goto outunmap; 1875 } 1876 } 1877 1878 return; 1879 1880outunmap: 1881 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1882 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1883 1884 handle = IDT77252_PRV_POOL(skb); 1885 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1886 1887outfree: 1888 dev_kfree_skb(skb); 1889} 1890 1891 1892static void 1893recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1894{ 1895 u32 handle = IDT77252_PRV_POOL(skb); 1896 int err; 1897 1898 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1899 skb_end_pointer(skb) - skb->data, 1900 PCI_DMA_FROMDEVICE); 1901 1902 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1903 if (err) { 1904 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1905 skb_end_pointer(skb) - skb->data, 1906 PCI_DMA_FROMDEVICE); 1907 sb_pool_remove(card, skb); 1908 dev_kfree_skb(skb); 1909 } 1910} 1911 1912static void 1913flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1914{ 1915 skb_queue_head_init(&rpp->queue); 1916 rpp->len = 0; 1917} 1918 1919static void 1920recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1921{ 1922 struct sk_buff *skb, *tmp; 1923 1924 skb_queue_walk_safe(&rpp->queue, skb, tmp) 1925 recycle_rx_skb(card, skb); 1926 1927 flush_rx_pool(card, rpp); 1928} 1929 1930/*****************************************************************************/ 1931/* */ 1932/* ATM Interface */ 1933/* */ 1934/*****************************************************************************/ 1935 1936static void 1937idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1938{ 1939 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1940} 1941 1942static unsigned char 1943idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1944{ 1945 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1946} 1947 1948static inline int 1949idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1950{ 1951 struct atm_dev *dev = vcc->dev; 1952 struct idt77252_dev *card = dev->dev_data; 1953 struct vc_map *vc = vcc->dev_data; 1954 int err; 1955 1956 if (vc == NULL) { 1957 printk("%s: NULL connection in send().\n", card->name); 1958 atomic_inc(&vcc->stats->tx_err); 1959 dev_kfree_skb(skb); 1960 return -EINVAL; 1961 } 1962 if (!test_bit(VCF_TX, &vc->flags)) { 1963 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1964 atomic_inc(&vcc->stats->tx_err); 1965 dev_kfree_skb(skb); 1966 return -EINVAL; 1967 } 1968 1969 switch (vcc->qos.aal) { 1970 case ATM_AAL0: 1971 case ATM_AAL1: 1972 case ATM_AAL5: 1973 break; 1974 default: 1975 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1976 atomic_inc(&vcc->stats->tx_err); 1977 dev_kfree_skb(skb); 1978 return -EINVAL; 1979 } 1980 1981 if (skb_shinfo(skb)->nr_frags != 0) { 1982 printk("%s: No scatter-gather yet.\n", card->name); 1983 atomic_inc(&vcc->stats->tx_err); 1984 dev_kfree_skb(skb); 1985 return -EINVAL; 1986 } 1987 ATM_SKB(skb)->vcc = vcc; 1988 1989 err = queue_skb(card, vc, skb, oam); 1990 if (err) { 1991 atomic_inc(&vcc->stats->tx_err); 1992 dev_kfree_skb(skb); 1993 return err; 1994 } 1995 1996 return 0; 1997} 1998 1999static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2000{ 2001 return idt77252_send_skb(vcc, skb, 0); 2002} 2003 2004static int 2005idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2006{ 2007 struct atm_dev *dev = vcc->dev; 2008 struct idt77252_dev *card = dev->dev_data; 2009 struct sk_buff *skb; 2010 2011 skb = dev_alloc_skb(64); 2012 if (!skb) { 2013 printk("%s: Out of memory in send_oam().\n", card->name); 2014 atomic_inc(&vcc->stats->tx_err); 2015 return -ENOMEM; 2016 } 2017 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2018 2019 memcpy(skb_put(skb, 52), cell, 52); 2020 2021 return idt77252_send_skb(vcc, skb, 1); 2022} 2023 2024static __inline__ unsigned int 2025idt77252_fls(unsigned int x) 2026{ 2027 int r = 1; 2028 2029 if (x == 0) 2030 return 0; 2031 if (x & 0xffff0000) { 2032 x >>= 16; 2033 r += 16; 2034 } 2035 if (x & 0xff00) { 2036 x >>= 8; 2037 r += 8; 2038 } 2039 if (x & 0xf0) { 2040 x >>= 4; 2041 r += 4; 2042 } 2043 if (x & 0xc) { 2044 x >>= 2; 2045 r += 2; 2046 } 2047 if (x & 0x2) 2048 r += 1; 2049 return r; 2050} 2051 2052static u16 2053idt77252_int_to_atmfp(unsigned int rate) 2054{ 2055 u16 m, e; 2056 2057 if (rate == 0) 2058 return 0; 2059 e = idt77252_fls(rate) - 1; 2060 if (e < 9) 2061 m = (rate - (1 << e)) << (9 - e); 2062 else if (e == 9) 2063 m = (rate - (1 << e)); 2064 else /* e > 9 */ 2065 m = (rate - (1 << e)) >> (e - 9); 2066 return 0x4000 | (e << 9) | m; 2067} 2068 2069static u8 2070idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2071{ 2072 u16 afp; 2073 2074 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2075 if (pcr < 0) 2076 return rate_to_log[(afp >> 5) & 0x1ff]; 2077 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2078} 2079 2080static void 2081idt77252_est_timer(unsigned long data) 2082{ 2083 struct vc_map *vc = (struct vc_map *)data; 2084 struct idt77252_dev *card = vc->card; 2085 struct rate_estimator *est; 2086 unsigned long flags; 2087 u32 rate, cps; 2088 u64 ncells; 2089 u8 lacr; 2090 2091 spin_lock_irqsave(&vc->lock, flags); 2092 est = vc->estimator; 2093 if (!est) 2094 goto out; 2095 2096 ncells = est->cells; 2097 2098 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2099 est->last_cells = ncells; 2100 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2101 est->cps = (est->avcps + 0x1f) >> 5; 2102 2103 cps = est->cps; 2104 if (cps < (est->maxcps >> 4)) 2105 cps = est->maxcps >> 4; 2106 2107 lacr = idt77252_rate_logindex(card, cps); 2108 if (lacr > vc->max_er) 2109 lacr = vc->max_er; 2110 2111 if (lacr != vc->lacr) { 2112 vc->lacr = lacr; 2113 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2114 } 2115 2116 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2117 add_timer(&est->timer); 2118 2119out: 2120 spin_unlock_irqrestore(&vc->lock, flags); 2121} 2122 2123static struct rate_estimator * 2124idt77252_init_est(struct vc_map *vc, int pcr) 2125{ 2126 struct rate_estimator *est; 2127 2128 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2129 if (!est) 2130 return NULL; 2131 est->maxcps = pcr < 0 ? -pcr : pcr; 2132 est->cps = est->maxcps; 2133 est->avcps = est->cps << 5; 2134 2135 est->interval = 2; /* XXX: make this configurable */ 2136 est->ewma_log = 2; /* XXX: make this configurable */ 2137 init_timer(&est->timer); 2138 est->timer.data = (unsigned long)vc; 2139 est->timer.function = idt77252_est_timer; 2140 2141 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2142 add_timer(&est->timer); 2143 2144 return est; 2145} 2146 2147static int 2148idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2149 struct atm_vcc *vcc, struct atm_qos *qos) 2150{ 2151 int tst_free, tst_used, tst_entries; 2152 unsigned long tmpl, modl; 2153 int tcr, tcra; 2154 2155 if ((qos->txtp.max_pcr == 0) && 2156 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2157 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2158 card->name); 2159 return -EINVAL; 2160 } 2161 2162 tst_used = 0; 2163 tst_free = card->tst_free; 2164 if (test_bit(VCF_TX, &vc->flags)) 2165 tst_used = vc->ntste; 2166 tst_free += tst_used; 2167 2168 tcr = atm_pcr_goal(&qos->txtp); 2169 tcra = tcr >= 0 ? tcr : -tcr; 2170 2171 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2172 2173 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2174 modl = tmpl % (unsigned long)card->utopia_pcr; 2175 2176 tst_entries = (int) (tmpl / card->utopia_pcr); 2177 if (tcr > 0) { 2178 if (modl > 0) 2179 tst_entries++; 2180 } else if (tcr == 0) { 2181 tst_entries = tst_free - SAR_TST_RESERVED; 2182 if (tst_entries <= 0) { 2183 printk("%s: no CBR bandwidth free.\n", card->name); 2184 return -ENOSR; 2185 } 2186 } 2187 2188 if (tst_entries == 0) { 2189 printk("%s: selected CBR bandwidth < granularity.\n", 2190 card->name); 2191 return -EINVAL; 2192 } 2193 2194 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2195 printk("%s: not enough CBR bandwidth free.\n", card->name); 2196 return -ENOSR; 2197 } 2198 2199 vc->ntste = tst_entries; 2200 2201 card->tst_free = tst_free - tst_entries; 2202 if (test_bit(VCF_TX, &vc->flags)) { 2203 if (tst_used == tst_entries) 2204 return 0; 2205 2206 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2207 card->name, tst_used, tst_entries); 2208 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2209 return 0; 2210 } 2211 2212 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2213 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2214 return 0; 2215} 2216 2217static int 2218idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2219 struct atm_vcc *vcc, struct atm_qos *qos) 2220{ 2221 unsigned long flags; 2222 int tcr; 2223 2224 spin_lock_irqsave(&vc->lock, flags); 2225 if (vc->estimator) { 2226 del_timer(&vc->estimator->timer); 2227 kfree(vc->estimator); 2228 vc->estimator = NULL; 2229 } 2230 spin_unlock_irqrestore(&vc->lock, flags); 2231 2232 tcr = atm_pcr_goal(&qos->txtp); 2233 if (tcr == 0) 2234 tcr = card->link_pcr; 2235 2236 vc->estimator = idt77252_init_est(vc, tcr); 2237 2238 vc->class = SCHED_UBR; 2239 vc->init_er = idt77252_rate_logindex(card, tcr); 2240 vc->lacr = vc->init_er; 2241 if (tcr < 0) 2242 vc->max_er = vc->init_er; 2243 else 2244 vc->max_er = 0xff; 2245 2246 return 0; 2247} 2248 2249static int 2250idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2251 struct atm_vcc *vcc, struct atm_qos *qos) 2252{ 2253 int error; 2254 2255 if (test_bit(VCF_TX, &vc->flags)) 2256 return -EBUSY; 2257 2258 switch (qos->txtp.traffic_class) { 2259 case ATM_CBR: 2260 vc->class = SCHED_CBR; 2261 break; 2262 2263 case ATM_UBR: 2264 vc->class = SCHED_UBR; 2265 break; 2266 2267 case ATM_VBR: 2268 case ATM_ABR: 2269 default: 2270 return -EPROTONOSUPPORT; 2271 } 2272 2273 vc->scq = alloc_scq(card, vc->class); 2274 if (!vc->scq) { 2275 printk("%s: can't get SCQ.\n", card->name); 2276 return -ENOMEM; 2277 } 2278 2279 vc->scq->scd = get_free_scd(card, vc); 2280 if (vc->scq->scd == 0) { 2281 printk("%s: no SCD available.\n", card->name); 2282 free_scq(card, vc->scq); 2283 return -ENOMEM; 2284 } 2285 2286 fill_scd(card, vc->scq, vc->class); 2287 2288 if (set_tct(card, vc)) { 2289 printk("%s: class %d not supported.\n", 2290 card->name, qos->txtp.traffic_class); 2291 2292 card->scd2vc[vc->scd_index] = NULL; 2293 free_scq(card, vc->scq); 2294 return -EPROTONOSUPPORT; 2295 } 2296 2297 switch (vc->class) { 2298 case SCHED_CBR: 2299 error = idt77252_init_cbr(card, vc, vcc, qos); 2300 if (error) { 2301 card->scd2vc[vc->scd_index] = NULL; 2302 free_scq(card, vc->scq); 2303 return error; 2304 } 2305 2306 clear_bit(VCF_IDLE, &vc->flags); 2307 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2308 break; 2309 2310 case SCHED_UBR: 2311 error = idt77252_init_ubr(card, vc, vcc, qos); 2312 if (error) { 2313 card->scd2vc[vc->scd_index] = NULL; 2314 free_scq(card, vc->scq); 2315 return error; 2316 } 2317 2318 set_bit(VCF_IDLE, &vc->flags); 2319 break; 2320 } 2321 2322 vc->tx_vcc = vcc; 2323 set_bit(VCF_TX, &vc->flags); 2324 return 0; 2325} 2326 2327static int 2328idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2329 struct atm_vcc *vcc, struct atm_qos *qos) 2330{ 2331 unsigned long flags; 2332 unsigned long addr; 2333 u32 rcte = 0; 2334 2335 if (test_bit(VCF_RX, &vc->flags)) 2336 return -EBUSY; 2337 2338 vc->rx_vcc = vcc; 2339 set_bit(VCF_RX, &vc->flags); 2340 2341 if ((vcc->vci == 3) || (vcc->vci == 4)) 2342 return 0; 2343 2344 flush_rx_pool(card, &vc->rcv.rx_pool); 2345 2346 rcte |= SAR_RCTE_CONNECTOPEN; 2347 rcte |= SAR_RCTE_RAWCELLINTEN; 2348 2349 switch (qos->aal) { 2350 case ATM_AAL0: 2351 rcte |= SAR_RCTE_RCQ; 2352 break; 2353 case ATM_AAL1: 2354 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2355 break; 2356 case ATM_AAL34: 2357 rcte |= SAR_RCTE_AAL34; 2358 break; 2359 case ATM_AAL5: 2360 rcte |= SAR_RCTE_AAL5; 2361 break; 2362 default: 2363 rcte |= SAR_RCTE_RCQ; 2364 break; 2365 } 2366 2367 if (qos->aal != ATM_AAL5) 2368 rcte |= SAR_RCTE_FBP_1; 2369 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2370 rcte |= SAR_RCTE_FBP_3; 2371 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2372 rcte |= SAR_RCTE_FBP_2; 2373 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2374 rcte |= SAR_RCTE_FBP_1; 2375 else 2376 rcte |= SAR_RCTE_FBP_01; 2377 2378 addr = card->rct_base + (vc->index << 2); 2379 2380 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2381 write_sram(card, addr, rcte); 2382 2383 spin_lock_irqsave(&card->cmd_lock, flags); 2384 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2385 waitfor_idle(card); 2386 spin_unlock_irqrestore(&card->cmd_lock, flags); 2387 2388 return 0; 2389} 2390 2391static int 2392idt77252_open(struct atm_vcc *vcc) 2393{ 2394 struct atm_dev *dev = vcc->dev; 2395 struct idt77252_dev *card = dev->dev_data; 2396 struct vc_map *vc; 2397 unsigned int index; 2398 unsigned int inuse; 2399 int error; 2400 int vci = vcc->vci; 2401 short vpi = vcc->vpi; 2402 2403 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2404 return 0; 2405 2406 if (vpi >= (1 << card->vpibits)) { 2407 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2408 return -EINVAL; 2409 } 2410 2411 if (vci >= (1 << card->vcibits)) { 2412 printk("%s: unsupported VCI: %d\n", card->name, vci); 2413 return -EINVAL; 2414 } 2415 2416 set_bit(ATM_VF_ADDR, &vcc->flags); 2417 2418 mutex_lock(&card->mutex); 2419 2420 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2421 2422 switch (vcc->qos.aal) { 2423 case ATM_AAL0: 2424 case ATM_AAL1: 2425 case ATM_AAL5: 2426 break; 2427 default: 2428 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2429 mutex_unlock(&card->mutex); 2430 return -EPROTONOSUPPORT; 2431 } 2432 2433 index = VPCI2VC(card, vpi, vci); 2434 if (!card->vcs[index]) { 2435 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2436 if (!card->vcs[index]) { 2437 printk("%s: can't alloc vc in open()\n", card->name); 2438 mutex_unlock(&card->mutex); 2439 return -ENOMEM; 2440 } 2441 card->vcs[index]->card = card; 2442 card->vcs[index]->index = index; 2443 2444 spin_lock_init(&card->vcs[index]->lock); 2445 } 2446 vc = card->vcs[index]; 2447 2448 vcc->dev_data = vc; 2449 2450 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2451 card->name, vc->index, vcc->vpi, vcc->vci, 2452 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2453 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2454 vcc->qos.rxtp.max_sdu); 2455 2456 inuse = 0; 2457 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2458 test_bit(VCF_TX, &vc->flags)) 2459 inuse = 1; 2460 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2461 test_bit(VCF_RX, &vc->flags)) 2462 inuse += 2; 2463 2464 if (inuse) { 2465 printk("%s: %s vci already in use.\n", card->name, 2466 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2467 mutex_unlock(&card->mutex); 2468 return -EADDRINUSE; 2469 } 2470 2471 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2472 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2473 if (error) { 2474 mutex_unlock(&card->mutex); 2475 return error; 2476 } 2477 } 2478 2479 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2480 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2481 if (error) { 2482 mutex_unlock(&card->mutex); 2483 return error; 2484 } 2485 } 2486 2487 set_bit(ATM_VF_READY, &vcc->flags); 2488 2489 mutex_unlock(&card->mutex); 2490 return 0; 2491} 2492 2493static void 2494idt77252_close(struct atm_vcc *vcc) 2495{ 2496 struct atm_dev *dev = vcc->dev; 2497 struct idt77252_dev *card = dev->dev_data; 2498 struct vc_map *vc = vcc->dev_data; 2499 unsigned long flags; 2500 unsigned long addr; 2501 unsigned long timeout; 2502 2503 mutex_lock(&card->mutex); 2504 2505 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2506 card->name, vc->index, vcc->vpi, vcc->vci); 2507 2508 clear_bit(ATM_VF_READY, &vcc->flags); 2509 2510 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2511 2512 spin_lock_irqsave(&vc->lock, flags); 2513 clear_bit(VCF_RX, &vc->flags); 2514 vc->rx_vcc = NULL; 2515 spin_unlock_irqrestore(&vc->lock, flags); 2516 2517 if ((vcc->vci == 3) || (vcc->vci == 4)) 2518 goto done; 2519 2520 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2521 2522 spin_lock_irqsave(&card->cmd_lock, flags); 2523 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2524 waitfor_idle(card); 2525 spin_unlock_irqrestore(&card->cmd_lock, flags); 2526 2527 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2528 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2529 card->name); 2530 2531 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2532 } 2533 } 2534 2535done: 2536 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2537 2538 spin_lock_irqsave(&vc->lock, flags); 2539 clear_bit(VCF_TX, &vc->flags); 2540 clear_bit(VCF_IDLE, &vc->flags); 2541 clear_bit(VCF_RSV, &vc->flags); 2542 vc->tx_vcc = NULL; 2543 2544 if (vc->estimator) { 2545 del_timer(&vc->estimator->timer); 2546 kfree(vc->estimator); 2547 vc->estimator = NULL; 2548 } 2549 spin_unlock_irqrestore(&vc->lock, flags); 2550 2551 timeout = 5 * 1000; 2552 while (atomic_read(&vc->scq->used) > 0) { 2553 timeout = msleep_interruptible(timeout); 2554 if (!timeout) 2555 break; 2556 } 2557 if (!timeout) 2558 printk("%s: SCQ drain timeout: %u used\n", 2559 card->name, atomic_read(&vc->scq->used)); 2560 2561 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2562 clear_scd(card, vc->scq, vc->class); 2563 2564 if (vc->class == SCHED_CBR) { 2565 clear_tst(card, vc); 2566 card->tst_free += vc->ntste; 2567 vc->ntste = 0; 2568 } 2569 2570 card->scd2vc[vc->scd_index] = NULL; 2571 free_scq(card, vc->scq); 2572 } 2573 2574 mutex_unlock(&card->mutex); 2575} 2576 2577static int 2578idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2579{ 2580 struct atm_dev *dev = vcc->dev; 2581 struct idt77252_dev *card = dev->dev_data; 2582 struct vc_map *vc = vcc->dev_data; 2583 int error = 0; 2584 2585 mutex_lock(&card->mutex); 2586 2587 if (qos->txtp.traffic_class != ATM_NONE) { 2588 if (!test_bit(VCF_TX, &vc->flags)) { 2589 error = idt77252_init_tx(card, vc, vcc, qos); 2590 if (error) 2591 goto out; 2592 } else { 2593 switch (qos->txtp.traffic_class) { 2594 case ATM_CBR: 2595 error = idt77252_init_cbr(card, vc, vcc, qos); 2596 if (error) 2597 goto out; 2598 break; 2599 2600 case ATM_UBR: 2601 error = idt77252_init_ubr(card, vc, vcc, qos); 2602 if (error) 2603 goto out; 2604 2605 if (!test_bit(VCF_IDLE, &vc->flags)) { 2606 writel(TCMDQ_LACR | (vc->lacr << 16) | 2607 vc->index, SAR_REG_TCMDQ); 2608 } 2609 break; 2610 2611 case ATM_VBR: 2612 case ATM_ABR: 2613 error = -EOPNOTSUPP; 2614 goto out; 2615 } 2616 } 2617 } 2618 2619 if ((qos->rxtp.traffic_class != ATM_NONE) && 2620 !test_bit(VCF_RX, &vc->flags)) { 2621 error = idt77252_init_rx(card, vc, vcc, qos); 2622 if (error) 2623 goto out; 2624 } 2625 2626 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2627 2628 set_bit(ATM_VF_HASQOS, &vcc->flags); 2629 2630out: 2631 mutex_unlock(&card->mutex); 2632 return error; 2633} 2634 2635static int 2636idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2637{ 2638 struct idt77252_dev *card = dev->dev_data; 2639 int i, left; 2640 2641 left = (int) *pos; 2642 if (!left--) 2643 return sprintf(page, "IDT77252 Interrupts:\n"); 2644 if (!left--) 2645 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2646 if (!left--) 2647 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2648 if (!left--) 2649 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2650 if (!left--) 2651 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2652 if (!left--) 2653 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2654 if (!left--) 2655 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2656 if (!left--) 2657 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2658 if (!left--) 2659 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2660 if (!left--) 2661 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2662 if (!left--) 2663 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2664 if (!left--) 2665 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2666 if (!left--) 2667 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2668 if (!left--) 2669 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2670 if (!left--) 2671 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2672 2673 for (i = 0; i < card->tct_size; i++) { 2674 unsigned long tct; 2675 struct atm_vcc *vcc; 2676 struct vc_map *vc; 2677 char *p; 2678 2679 vc = card->vcs[i]; 2680 if (!vc) 2681 continue; 2682 2683 vcc = NULL; 2684 if (vc->tx_vcc) 2685 vcc = vc->tx_vcc; 2686 if (!vcc) 2687 continue; 2688 if (left--) 2689 continue; 2690 2691 p = page; 2692 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2693 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2694 2695 for (i = 0; i < 8; i++) 2696 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2697 p += sprintf(p, "\n"); 2698 return p - page; 2699 } 2700 return 0; 2701} 2702 2703/*****************************************************************************/ 2704/* */ 2705/* Interrupt handler */ 2706/* */ 2707/*****************************************************************************/ 2708 2709static void 2710idt77252_collect_stat(struct idt77252_dev *card) 2711{ 2712 (void) readl(SAR_REG_CDC); 2713 (void) readl(SAR_REG_VPEC); 2714 (void) readl(SAR_REG_ICC); 2715 2716} 2717 2718static irqreturn_t 2719idt77252_interrupt(int irq, void *dev_id) 2720{ 2721 struct idt77252_dev *card = dev_id; 2722 u32 stat; 2723 2724 stat = readl(SAR_REG_STAT) & 0xffff; 2725 if (!stat) /* no interrupt for us */ 2726 return IRQ_NONE; 2727 2728 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2729 printk("%s: Re-entering irq_handler()\n", card->name); 2730 goto out; 2731 } 2732 2733 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2734 2735 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2736 INTPRINTK("%s: TSIF\n", card->name); 2737 card->irqstat[15]++; 2738 idt77252_tx(card); 2739 } 2740 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2741 INTPRINTK("%s: TXICP\n", card->name); 2742 card->irqstat[14]++; 2743#ifdef CONFIG_ATM_IDT77252_DEBUG 2744 idt77252_tx_dump(card); 2745#endif 2746 } 2747 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2748 INTPRINTK("%s: TSQF\n", card->name); 2749 card->irqstat[12]++; 2750 idt77252_tx(card); 2751 } 2752 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2753 INTPRINTK("%s: TMROF\n", card->name); 2754 card->irqstat[11]++; 2755 idt77252_collect_stat(card); 2756 } 2757 2758 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2759 INTPRINTK("%s: EPDU\n", card->name); 2760 card->irqstat[5]++; 2761 idt77252_rx(card); 2762 } 2763 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2764 INTPRINTK("%s: RSQAF\n", card->name); 2765 card->irqstat[1]++; 2766 idt77252_rx(card); 2767 } 2768 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2769 INTPRINTK("%s: RSQF\n", card->name); 2770 card->irqstat[6]++; 2771 idt77252_rx(card); 2772 } 2773 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2774 INTPRINTK("%s: RAWCF\n", card->name); 2775 card->irqstat[4]++; 2776 idt77252_rx_raw(card); 2777 } 2778 2779 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2780 INTPRINTK("%s: PHYI", card->name); 2781 card->irqstat[10]++; 2782 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2783 card->atmdev->phy->interrupt(card->atmdev); 2784 } 2785 2786 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2787 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2788 2789 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2790 2791 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2792 2793 if (stat & SAR_STAT_FBQ0A) 2794 card->irqstat[2]++; 2795 if (stat & SAR_STAT_FBQ1A) 2796 card->irqstat[3]++; 2797 if (stat & SAR_STAT_FBQ2A) 2798 card->irqstat[7]++; 2799 if (stat & SAR_STAT_FBQ3A) 2800 card->irqstat[8]++; 2801 2802 schedule_work(&card->tqueue); 2803 } 2804 2805out: 2806 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2807 return IRQ_HANDLED; 2808} 2809 2810static void 2811idt77252_softint(struct work_struct *work) 2812{ 2813 struct idt77252_dev *card = 2814 container_of(work, struct idt77252_dev, tqueue); 2815 u32 stat; 2816 int done; 2817 2818 for (done = 1; ; done = 1) { 2819 stat = readl(SAR_REG_STAT) >> 16; 2820 2821 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2822 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2823 done = 0; 2824 } 2825 2826 stat >>= 4; 2827 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2828 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2829 done = 0; 2830 } 2831 2832 stat >>= 4; 2833 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2834 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2835 done = 0; 2836 } 2837 2838 stat >>= 4; 2839 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2840 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2841 done = 0; 2842 } 2843 2844 if (done) 2845 break; 2846 } 2847 2848 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2849} 2850 2851 2852static int 2853open_card_oam(struct idt77252_dev *card) 2854{ 2855 unsigned long flags; 2856 unsigned long addr; 2857 struct vc_map *vc; 2858 int vpi, vci; 2859 int index; 2860 u32 rcte; 2861 2862 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2863 for (vci = 3; vci < 5; vci++) { 2864 index = VPCI2VC(card, vpi, vci); 2865 2866 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2867 if (!vc) { 2868 printk("%s: can't alloc vc\n", card->name); 2869 return -ENOMEM; 2870 } 2871 vc->index = index; 2872 card->vcs[index] = vc; 2873 2874 flush_rx_pool(card, &vc->rcv.rx_pool); 2875 2876 rcte = SAR_RCTE_CONNECTOPEN | 2877 SAR_RCTE_RAWCELLINTEN | 2878 SAR_RCTE_RCQ | 2879 SAR_RCTE_FBP_1; 2880 2881 addr = card->rct_base + (vc->index << 2); 2882 write_sram(card, addr, rcte); 2883 2884 spin_lock_irqsave(&card->cmd_lock, flags); 2885 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2886 SAR_REG_CMD); 2887 waitfor_idle(card); 2888 spin_unlock_irqrestore(&card->cmd_lock, flags); 2889 } 2890 } 2891 2892 return 0; 2893} 2894 2895static void 2896close_card_oam(struct idt77252_dev *card) 2897{ 2898 unsigned long flags; 2899 unsigned long addr; 2900 struct vc_map *vc; 2901 int vpi, vci; 2902 int index; 2903 2904 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2905 for (vci = 3; vci < 5; vci++) { 2906 index = VPCI2VC(card, vpi, vci); 2907 vc = card->vcs[index]; 2908 2909 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2910 2911 spin_lock_irqsave(&card->cmd_lock, flags); 2912 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2913 SAR_REG_CMD); 2914 waitfor_idle(card); 2915 spin_unlock_irqrestore(&card->cmd_lock, flags); 2916 2917 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2918 DPRINTK("%s: closing a VC " 2919 "with pending rx buffers.\n", 2920 card->name); 2921 2922 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2923 } 2924 } 2925 } 2926} 2927 2928static int 2929open_card_ubr0(struct idt77252_dev *card) 2930{ 2931 struct vc_map *vc; 2932 2933 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2934 if (!vc) { 2935 printk("%s: can't alloc vc\n", card->name); 2936 return -ENOMEM; 2937 } 2938 card->vcs[0] = vc; 2939 vc->class = SCHED_UBR0; 2940 2941 vc->scq = alloc_scq(card, vc->class); 2942 if (!vc->scq) { 2943 printk("%s: can't get SCQ.\n", card->name); 2944 return -ENOMEM; 2945 } 2946 2947 card->scd2vc[0] = vc; 2948 vc->scd_index = 0; 2949 vc->scq->scd = card->scd_base; 2950 2951 fill_scd(card, vc->scq, vc->class); 2952 2953 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 2954 write_sram(card, card->tct_base + 1, 0); 2955 write_sram(card, card->tct_base + 2, 0); 2956 write_sram(card, card->tct_base + 3, 0); 2957 write_sram(card, card->tct_base + 4, 0); 2958 write_sram(card, card->tct_base + 5, 0); 2959 write_sram(card, card->tct_base + 6, 0); 2960 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 2961 2962 clear_bit(VCF_IDLE, &vc->flags); 2963 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 2964 return 0; 2965} 2966 2967static int 2968idt77252_dev_open(struct idt77252_dev *card) 2969{ 2970 u32 conf; 2971 2972 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 2973 printk("%s: SAR not yet initialized.\n", card->name); 2974 return -1; 2975 } 2976 2977 conf = SAR_CFG_RXPTH| /* enable receive path */ 2978 SAR_RX_DELAY | /* interrupt on complete PDU */ 2979 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 2980 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 2981 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 2982 SAR_CFG_FBIE | /* interrupt on low free buffers */ 2983 SAR_CFG_TXEN | /* transmit operation enable */ 2984 SAR_CFG_TXINT | /* interrupt on transmit status */ 2985 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 2986 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 2987 SAR_CFG_PHYIE /* enable PHY interrupts */ 2988 ; 2989 2990#ifdef CONFIG_ATM_IDT77252_RCV_ALL 2991 /* Test RAW cell receive. */ 2992 conf |= SAR_CFG_VPECA; 2993#endif 2994 2995 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 2996 2997 if (open_card_oam(card)) { 2998 printk("%s: Error initializing OAM.\n", card->name); 2999 return -1; 3000 } 3001 3002 if (open_card_ubr0(card)) { 3003 printk("%s: Error initializing UBR0.\n", card->name); 3004 return -1; 3005 } 3006 3007 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3008 return 0; 3009} 3010 3011static void idt77252_dev_close(struct atm_dev *dev) 3012{ 3013 struct idt77252_dev *card = dev->dev_data; 3014 u32 conf; 3015 3016 close_card_oam(card); 3017 3018 conf = SAR_CFG_RXPTH | /* enable receive path */ 3019 SAR_RX_DELAY | /* interrupt on complete PDU */ 3020 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3021 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3022 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3023 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3024 SAR_CFG_TXEN | /* transmit operation enable */ 3025 SAR_CFG_TXINT | /* interrupt on transmit status */ 3026 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3027 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3028 ; 3029 3030 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3031 3032 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3033} 3034 3035 3036/*****************************************************************************/ 3037/* */ 3038/* Initialisation and Deinitialization of IDT77252 */ 3039/* */ 3040/*****************************************************************************/ 3041 3042 3043static void 3044deinit_card(struct idt77252_dev *card) 3045{ 3046 struct sk_buff *skb; 3047 int i, j; 3048 3049 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3050 printk("%s: SAR not yet initialized.\n", card->name); 3051 return; 3052 } 3053 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3054 3055 writel(0, SAR_REG_CFG); 3056 3057 if (card->atmdev) 3058 atm_dev_deregister(card->atmdev); 3059 3060 for (i = 0; i < 4; i++) { 3061 for (j = 0; j < FBQ_SIZE; j++) { 3062 skb = card->sbpool[i].skb[j]; 3063 if (skb) { 3064 pci_unmap_single(card->pcidev, 3065 IDT77252_PRV_PADDR(skb), 3066 (skb_end_pointer(skb) - 3067 skb->data), 3068 PCI_DMA_FROMDEVICE); 3069 card->sbpool[i].skb[j] = NULL; 3070 dev_kfree_skb(skb); 3071 } 3072 } 3073 } 3074 3075 vfree(card->soft_tst); 3076 3077 vfree(card->scd2vc); 3078 3079 vfree(card->vcs); 3080 3081 if (card->raw_cell_hnd) { 3082 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3083 card->raw_cell_hnd, card->raw_cell_paddr); 3084 } 3085 3086 if (card->rsq.base) { 3087 DIPRINTK("%s: Release RSQ ...\n", card->name); 3088 deinit_rsq(card); 3089 } 3090 3091 if (card->tsq.base) { 3092 DIPRINTK("%s: Release TSQ ...\n", card->name); 3093 deinit_tsq(card); 3094 } 3095 3096 DIPRINTK("idt77252: Release IRQ.\n"); 3097 free_irq(card->pcidev->irq, card); 3098 3099 for (i = 0; i < 4; i++) { 3100 if (card->fbq[i]) 3101 iounmap(card->fbq[i]); 3102 } 3103 3104 if (card->membase) 3105 iounmap(card->membase); 3106 3107 clear_bit(IDT77252_BIT_INIT, &card->flags); 3108 DIPRINTK("%s: Card deinitialized.\n", card->name); 3109} 3110 3111 3112static void __devinit 3113init_sram(struct idt77252_dev *card) 3114{ 3115 int i; 3116 3117 for (i = 0; i < card->sramsize; i += 4) 3118 write_sram(card, (i >> 2), 0); 3119 3120 /* set SRAM layout for THIS card */ 3121 if (card->sramsize == (512 * 1024)) { 3122 card->tct_base = SAR_SRAM_TCT_128_BASE; 3123 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3124 / SAR_SRAM_TCT_SIZE; 3125 card->rct_base = SAR_SRAM_RCT_128_BASE; 3126 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3127 / SAR_SRAM_RCT_SIZE; 3128 card->rt_base = SAR_SRAM_RT_128_BASE; 3129 card->scd_base = SAR_SRAM_SCD_128_BASE; 3130 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3131 / SAR_SRAM_SCD_SIZE; 3132 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3133 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3134 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3135 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3136 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3137 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3138 card->fifo_size = SAR_RXFD_SIZE_32K; 3139 } else { 3140 card->tct_base = SAR_SRAM_TCT_32_BASE; 3141 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3142 / SAR_SRAM_TCT_SIZE; 3143 card->rct_base = SAR_SRAM_RCT_32_BASE; 3144 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3145 / SAR_SRAM_RCT_SIZE; 3146 card->rt_base = SAR_SRAM_RT_32_BASE; 3147 card->scd_base = SAR_SRAM_SCD_32_BASE; 3148 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3149 / SAR_SRAM_SCD_SIZE; 3150 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3151 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3152 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3153 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3154 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3155 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3156 card->fifo_size = SAR_RXFD_SIZE_4K; 3157 } 3158 3159 /* Initialize TCT */ 3160 for (i = 0; i < card->tct_size; i++) { 3161 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3162 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3163 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3164 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3165 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3166 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3167 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3168 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3169 } 3170 3171 /* Initialize RCT */ 3172 for (i = 0; i < card->rct_size; i++) { 3173 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3174 (u32) SAR_RCTE_RAWCELLINTEN); 3175 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3176 (u32) 0); 3177 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3178 (u32) 0); 3179 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3180 (u32) 0xffffffff); 3181 } 3182 3183 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3184 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3185 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3186 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3187 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3188 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3189 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3190 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3191 3192 /* Initialize rate table */ 3193 for (i = 0; i < 256; i++) { 3194 write_sram(card, card->rt_base + i, log_to_rate[i]); 3195 } 3196 3197 for (i = 0; i < 128; i++) { 3198 unsigned int tmp; 3199 3200 tmp = rate_to_log[(i << 2) + 0] << 0; 3201 tmp |= rate_to_log[(i << 2) + 1] << 8; 3202 tmp |= rate_to_log[(i << 2) + 2] << 16; 3203 tmp |= rate_to_log[(i << 2) + 3] << 24; 3204 write_sram(card, card->rt_base + 256 + i, tmp); 3205 } 3206 3207#if 0 /* Fill RDF and AIR tables. */ 3208 for (i = 0; i < 128; i++) { 3209 unsigned int tmp; 3210 3211 tmp = RDF[0][(i << 1) + 0] << 16; 3212 tmp |= RDF[0][(i << 1) + 1] << 0; 3213 write_sram(card, card->rt_base + 512 + i, tmp); 3214 } 3215 3216 for (i = 0; i < 128; i++) { 3217 unsigned int tmp; 3218 3219 tmp = AIR[0][(i << 1) + 0] << 16; 3220 tmp |= AIR[0][(i << 1) + 1] << 0; 3221 write_sram(card, card->rt_base + 640 + i, tmp); 3222 } 3223#endif 3224 3225 IPRINTK("%s: initialize rate table ...\n", card->name); 3226 writel(card->rt_base << 2, SAR_REG_RTBL); 3227 3228 /* Initialize TSTs */ 3229 IPRINTK("%s: initialize TST ...\n", card->name); 3230 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3231 3232 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3233 write_sram(card, i, TSTE_OPC_VAR); 3234 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3235 idt77252_sram_write_errors = 1; 3236 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3237 idt77252_sram_write_errors = 0; 3238 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3239 write_sram(card, i, TSTE_OPC_VAR); 3240 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3241 idt77252_sram_write_errors = 1; 3242 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3243 idt77252_sram_write_errors = 0; 3244 3245 card->tst_index = 0; 3246 writel(card->tst[0] << 2, SAR_REG_TSTB); 3247 3248 /* Initialize ABRSTD and Receive FIFO */ 3249 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3250 writel(card->abrst_size | (card->abrst_base << 2), 3251 SAR_REG_ABRSTD); 3252 3253 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3254 writel(card->fifo_size | (card->fifo_base << 2), 3255 SAR_REG_RXFD); 3256 3257 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3258} 3259 3260static int __devinit 3261init_card(struct atm_dev *dev) 3262{ 3263 struct idt77252_dev *card = dev->dev_data; 3264 struct pci_dev *pcidev = card->pcidev; 3265 unsigned long tmpl, modl; 3266 unsigned int linkrate, rsvdcr; 3267 unsigned int tst_entries; 3268 struct net_device *tmp; 3269 char tname[10]; 3270 3271 u32 size; 3272 u_char pci_byte; 3273 u32 conf; 3274 int i, k; 3275 3276 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3277 printk("Error: SAR already initialized.\n"); 3278 return -1; 3279 } 3280 3281/*****************************************************************/ 3282/* P C I C O N F I G U R A T I O N */ 3283/*****************************************************************/ 3284 3285 /* Set PCI Retry-Timeout and TRDY timeout */ 3286 IPRINTK("%s: Checking PCI retries.\n", card->name); 3287 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3288 printk("%s: can't read PCI retry timeout.\n", card->name); 3289 deinit_card(card); 3290 return -1; 3291 } 3292 if (pci_byte != 0) { 3293 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3294 card->name, pci_byte); 3295 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3296 printk("%s: can't set PCI retry timeout.\n", 3297 card->name); 3298 deinit_card(card); 3299 return -1; 3300 } 3301 } 3302 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3303 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3304 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3305 deinit_card(card); 3306 return -1; 3307 } 3308 if (pci_byte != 0) { 3309 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3310 card->name, pci_byte); 3311 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3312 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3313 deinit_card(card); 3314 return -1; 3315 } 3316 } 3317 /* Reset Timer register */ 3318 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3319 printk("%s: resetting timer overflow.\n", card->name); 3320 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3321 } 3322 IPRINTK("%s: Request IRQ ... ", card->name); 3323 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED, 3324 card->name, card) != 0) { 3325 printk("%s: can't allocate IRQ.\n", card->name); 3326 deinit_card(card); 3327 return -1; 3328 } 3329 IPRINTK("got %d.\n", pcidev->irq); 3330 3331/*****************************************************************/ 3332/* C H E C K A N D I N I T S R A M */ 3333/*****************************************************************/ 3334 3335 IPRINTK("%s: Initializing SRAM\n", card->name); 3336 3337 /* preset size of connecton table, so that init_sram() knows about it */ 3338 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3339 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3340 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3341#ifndef ATM_IDT77252_SEND_IDLE 3342 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3343#endif 3344 0; 3345 3346 if (card->sramsize == (512 * 1024)) 3347 conf |= SAR_CFG_CNTBL_1k; 3348 else 3349 conf |= SAR_CFG_CNTBL_512; 3350 3351 switch (vpibits) { 3352 case 0: 3353 conf |= SAR_CFG_VPVCS_0; 3354 break; 3355 default: 3356 case 1: 3357 conf |= SAR_CFG_VPVCS_1; 3358 break; 3359 case 2: 3360 conf |= SAR_CFG_VPVCS_2; 3361 break; 3362 case 8: 3363 conf |= SAR_CFG_VPVCS_8; 3364 break; 3365 } 3366 3367 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3368 3369 init_sram(card); 3370 3371/********************************************************************/ 3372/* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3373/********************************************************************/ 3374 /* Initialize TSQ */ 3375 if (0 != init_tsq(card)) { 3376 deinit_card(card); 3377 return -1; 3378 } 3379 /* Initialize RSQ */ 3380 if (0 != init_rsq(card)) { 3381 deinit_card(card); 3382 return -1; 3383 } 3384 3385 card->vpibits = vpibits; 3386 if (card->sramsize == (512 * 1024)) { 3387 card->vcibits = 10 - card->vpibits; 3388 } else { 3389 card->vcibits = 9 - card->vpibits; 3390 } 3391 3392 card->vcimask = 0; 3393 for (k = 0, i = 1; k < card->vcibits; k++) { 3394 card->vcimask |= i; 3395 i <<= 1; 3396 } 3397 3398 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3399 writel(0, SAR_REG_VPM); 3400 3401 /* Little Endian Order */ 3402 writel(0, SAR_REG_GP); 3403 3404 /* Initialize RAW Cell Handle Register */ 3405 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3406 &card->raw_cell_paddr); 3407 if (!card->raw_cell_hnd) { 3408 printk("%s: memory allocation failure.\n", card->name); 3409 deinit_card(card); 3410 return -1; 3411 } 3412 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3413 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3414 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3415 card->raw_cell_hnd); 3416 3417 size = sizeof(struct vc_map *) * card->tct_size; 3418 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3419 if (NULL == (card->vcs = vmalloc(size))) { 3420 printk("%s: memory allocation failure.\n", card->name); 3421 deinit_card(card); 3422 return -1; 3423 } 3424 memset(card->vcs, 0, size); 3425 3426 size = sizeof(struct vc_map *) * card->scd_size; 3427 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3428 card->name, size); 3429 if (NULL == (card->scd2vc = vmalloc(size))) { 3430 printk("%s: memory allocation failure.\n", card->name); 3431 deinit_card(card); 3432 return -1; 3433 } 3434 memset(card->scd2vc, 0, size); 3435 3436 size = sizeof(struct tst_info) * (card->tst_size - 2); 3437 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3438 card->name, size); 3439 if (NULL == (card->soft_tst = vmalloc(size))) { 3440 printk("%s: memory allocation failure.\n", card->name); 3441 deinit_card(card); 3442 return -1; 3443 } 3444 for (i = 0; i < card->tst_size - 2; i++) { 3445 card->soft_tst[i].tste = TSTE_OPC_VAR; 3446 card->soft_tst[i].vc = NULL; 3447 } 3448 3449 if (dev->phy == NULL) { 3450 printk("%s: No LT device defined.\n", card->name); 3451 deinit_card(card); 3452 return -1; 3453 } 3454 if (dev->phy->ioctl == NULL) { 3455 printk("%s: LT had no IOCTL function defined.\n", card->name); 3456 deinit_card(card); 3457 return -1; 3458 } 3459 3460#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3461 /* 3462 * this is a jhs hack to get around special functionality in the 3463 * phy driver for the atecom hardware; the functionality doesn't 3464 * exist in the linux atm suni driver 3465 * 3466 * it isn't the right way to do things, but as the guy from NIST 3467 * said, talking about their measurement of the fine structure 3468 * constant, "it's good enough for government work." 3469 */ 3470 linkrate = 149760000; 3471#endif 3472 3473 card->link_pcr = (linkrate / 8 / 53); 3474 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3475 card->name, linkrate, card->link_pcr); 3476 3477#ifdef ATM_IDT77252_SEND_IDLE 3478 card->utopia_pcr = card->link_pcr; 3479#else 3480 card->utopia_pcr = (160000000 / 8 / 54); 3481#endif 3482 3483 rsvdcr = 0; 3484 if (card->utopia_pcr > card->link_pcr) 3485 rsvdcr = card->utopia_pcr - card->link_pcr; 3486 3487 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3488 modl = tmpl % (unsigned long)card->utopia_pcr; 3489 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3490 if (modl) 3491 tst_entries++; 3492 card->tst_free -= tst_entries; 3493 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3494 3495#ifdef HAVE_EEPROM 3496 idt77252_eeprom_init(card); 3497 printk("%s: EEPROM: %02x:", card->name, 3498 idt77252_eeprom_read_status(card)); 3499 3500 for (i = 0; i < 0x80; i++) { 3501 printk(" %02x", 3502 idt77252_eeprom_read_byte(card, i) 3503 ); 3504 } 3505 printk("\n"); 3506#endif /* HAVE_EEPROM */ 3507 3508 /* 3509 * XXX: <hack> 3510 */ 3511 sprintf(tname, "eth%d", card->index); 3512 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ 3513 if (tmp) { 3514 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3515 3516 printk("%s: ESI %pM\n", card->name, card->atmdev->esi); 3517 } 3518 /* 3519 * XXX: </hack> 3520 */ 3521 3522 /* Set Maximum Deficit Count for now. */ 3523 writel(0xffff, SAR_REG_MDFCT); 3524 3525 set_bit(IDT77252_BIT_INIT, &card->flags); 3526 3527 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3528 return 0; 3529} 3530 3531 3532/*****************************************************************************/ 3533/* */ 3534/* Probing of IDT77252 ABR SAR */ 3535/* */ 3536/*****************************************************************************/ 3537 3538 3539static int __devinit 3540idt77252_preset(struct idt77252_dev *card) 3541{ 3542 u16 pci_command; 3543 3544/*****************************************************************/ 3545/* P C I C O N F I G U R A T I O N */ 3546/*****************************************************************/ 3547 3548 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3549 card->name); 3550 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3551 printk("%s: can't read PCI_COMMAND.\n", card->name); 3552 deinit_card(card); 3553 return -1; 3554 } 3555 if (!(pci_command & PCI_COMMAND_IO)) { 3556 printk("%s: PCI_COMMAND: %04x (???)\n", 3557 card->name, pci_command); 3558 deinit_card(card); 3559 return (-1); 3560 } 3561 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3562 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3563 printk("%s: can't write PCI_COMMAND.\n", card->name); 3564 deinit_card(card); 3565 return -1; 3566 } 3567/*****************************************************************/ 3568/* G E N E R I C R E S E T */ 3569/*****************************************************************/ 3570 3571 /* Software reset */ 3572 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3573 mdelay(1); 3574 writel(0, SAR_REG_CFG); 3575 3576 IPRINTK("%s: Software resetted.\n", card->name); 3577 return 0; 3578} 3579 3580 3581static unsigned long __devinit 3582probe_sram(struct idt77252_dev *card) 3583{ 3584 u32 data, addr; 3585 3586 writel(0, SAR_REG_DR0); 3587 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3588 3589 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3590 writel(ATM_POISON, SAR_REG_DR0); 3591 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3592 3593 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3594 data = readl(SAR_REG_DR0); 3595 3596 if (data != 0) 3597 break; 3598 } 3599 3600 return addr * sizeof(u32); 3601} 3602 3603static int __devinit 3604idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3605{ 3606 static struct idt77252_dev **last = &idt77252_chain; 3607 static int index = 0; 3608 3609 unsigned long membase, srambase; 3610 struct idt77252_dev *card; 3611 struct atm_dev *dev; 3612 int i, err; 3613 3614 3615 if ((err = pci_enable_device(pcidev))) { 3616 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3617 return err; 3618 } 3619 3620 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3621 if (!card) { 3622 printk("idt77252-%d: can't allocate private data\n", index); 3623 err = -ENOMEM; 3624 goto err_out_disable_pdev; 3625 } 3626 card->revision = pcidev->revision; 3627 card->index = index; 3628 card->pcidev = pcidev; 3629 sprintf(card->name, "idt77252-%d", card->index); 3630 3631 INIT_WORK(&card->tqueue, idt77252_softint); 3632 3633 membase = pci_resource_start(pcidev, 1); 3634 srambase = pci_resource_start(pcidev, 2); 3635 3636 mutex_init(&card->mutex); 3637 spin_lock_init(&card->cmd_lock); 3638 spin_lock_init(&card->tst_lock); 3639 3640 init_timer(&card->tst_timer); 3641 card->tst_timer.data = (unsigned long)card; 3642 card->tst_timer.function = tst_timer; 3643 3644 /* Do the I/O remapping... */ 3645 card->membase = ioremap(membase, 1024); 3646 if (!card->membase) { 3647 printk("%s: can't ioremap() membase\n", card->name); 3648 err = -EIO; 3649 goto err_out_free_card; 3650 } 3651 3652 if (idt77252_preset(card)) { 3653 printk("%s: preset failed\n", card->name); 3654 err = -EIO; 3655 goto err_out_iounmap; 3656 } 3657 3658 dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1, 3659 NULL); 3660 if (!dev) { 3661 printk("%s: can't register atm device\n", card->name); 3662 err = -EIO; 3663 goto err_out_iounmap; 3664 } 3665 dev->dev_data = card; 3666 card->atmdev = dev; 3667 3668#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3669 suni_init(dev); 3670 if (!dev->phy) { 3671 printk("%s: can't init SUNI\n", card->name); 3672 err = -EIO; 3673 goto err_out_deinit_card; 3674 } 3675#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3676 3677 card->sramsize = probe_sram(card); 3678 3679 for (i = 0; i < 4; i++) { 3680 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3681 if (!card->fbq[i]) { 3682 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3683 err = -EIO; 3684 goto err_out_deinit_card; 3685 } 3686 } 3687 3688 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3689 card->name, ((card->revision > 1) && (card->revision < 25)) ? 3690 'A' + card->revision - 1 : '?', membase, srambase, 3691 card->sramsize / 1024); 3692 3693 if (init_card(dev)) { 3694 printk("%s: init_card failed\n", card->name); 3695 err = -EIO; 3696 goto err_out_deinit_card; 3697 } 3698 3699 dev->ci_range.vpi_bits = card->vpibits; 3700 dev->ci_range.vci_bits = card->vcibits; 3701 dev->link_rate = card->link_pcr; 3702 3703 if (dev->phy->start) 3704 dev->phy->start(dev); 3705 3706 if (idt77252_dev_open(card)) { 3707 printk("%s: dev_open failed\n", card->name); 3708 err = -EIO; 3709 goto err_out_stop; 3710 } 3711 3712 *last = card; 3713 last = &card->next; 3714 index++; 3715 3716 return 0; 3717 3718err_out_stop: 3719 if (dev->phy->stop) 3720 dev->phy->stop(dev); 3721 3722err_out_deinit_card: 3723 deinit_card(card); 3724 3725err_out_iounmap: 3726 iounmap(card->membase); 3727 3728err_out_free_card: 3729 kfree(card); 3730 3731err_out_disable_pdev: 3732 pci_disable_device(pcidev); 3733 return err; 3734} 3735 3736static struct pci_device_id idt77252_pci_tbl[] = 3737{ 3738 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 }, 3739 { 0, } 3740}; 3741 3742MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3743 3744static struct pci_driver idt77252_driver = { 3745 .name = "idt77252", 3746 .id_table = idt77252_pci_tbl, 3747 .probe = idt77252_init_one, 3748}; 3749 3750static int __init idt77252_init(void) 3751{ 3752 struct sk_buff *skb; 3753 3754 printk("%s: at %p\n", __func__, idt77252_init); 3755 3756 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3757 sizeof(struct idt77252_skb_prv)) { 3758 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3759 __func__, (unsigned long) sizeof(skb->cb), 3760 (unsigned long) sizeof(struct atm_skb_data) + 3761 sizeof(struct idt77252_skb_prv)); 3762 return -EIO; 3763 } 3764 3765 return pci_register_driver(&idt77252_driver); 3766} 3767 3768static void __exit idt77252_exit(void) 3769{ 3770 struct idt77252_dev *card; 3771 struct atm_dev *dev; 3772 3773 pci_unregister_driver(&idt77252_driver); 3774 3775 while (idt77252_chain) { 3776 card = idt77252_chain; 3777 dev = card->atmdev; 3778 idt77252_chain = card->next; 3779 3780 if (dev->phy->stop) 3781 dev->phy->stop(dev); 3782 deinit_card(card); 3783 pci_disable_device(card->pcidev); 3784 kfree(card); 3785 } 3786 3787 DIPRINTK("idt77252: finished cleanup-module().\n"); 3788} 3789 3790module_init(idt77252_init); 3791module_exit(idt77252_exit); 3792 3793MODULE_LICENSE("GPL"); 3794 3795module_param(vpibits, uint, 0); 3796MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3797#ifdef CONFIG_ATM_IDT77252_DEBUG 3798module_param(debug, ulong, 0644); 3799MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3800#endif 3801 3802MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3803MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3804