idt77252.c revision dace145374b8e39aeb920304c358ab5e220341ab
1/******************************************************************* 2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $" 3 * 4 * $Author: ecd $ 5 * $Date: 2001/11/11 08:13:54 $ 6 * 7 * Copyright (c) 2000 ATecoM GmbH 8 * 9 * The author may be reached at ecd@atecom.com. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 *******************************************************************/ 32static char const rcsid[] = 33"$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"; 34 35 36#include <linux/module.h> 37#include <linux/pci.h> 38#include <linux/skbuff.h> 39#include <linux/kernel.h> 40#include <linux/vmalloc.h> 41#include <linux/netdevice.h> 42#include <linux/atmdev.h> 43#include <linux/atm.h> 44#include <linux/delay.h> 45#include <linux/init.h> 46#include <linux/bitops.h> 47#include <linux/wait.h> 48#include <linux/jiffies.h> 49#include <asm/semaphore.h> 50#include <asm/io.h> 51#include <asm/uaccess.h> 52#include <asm/atomic.h> 53#include <asm/byteorder.h> 54 55#ifdef CONFIG_ATM_IDT77252_USE_SUNI 56#include "suni.h" 57#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 58 59 60#include "idt77252.h" 61#include "idt77252_tables.h" 62 63static unsigned int vpibits = 1; 64 65 66#define CONFIG_ATM_IDT77252_SEND_IDLE 1 67 68 69/* 70 * Debug HACKs. 71 */ 72#define DEBUG_MODULE 1 73#undef HAVE_EEPROM /* does not work, yet. */ 74 75#ifdef CONFIG_ATM_IDT77252_DEBUG 76static unsigned long debug = DBG_GENERAL; 77#endif 78 79 80#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 81 82 83/* 84 * SCQ Handling. 85 */ 86static struct scq_info *alloc_scq(struct idt77252_dev *, int); 87static void free_scq(struct idt77252_dev *, struct scq_info *); 88static int queue_skb(struct idt77252_dev *, struct vc_map *, 89 struct sk_buff *, int oam); 90static void drain_scq(struct idt77252_dev *, struct vc_map *); 91static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 92static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 93 94/* 95 * FBQ Handling. 96 */ 97static int push_rx_skb(struct idt77252_dev *, 98 struct sk_buff *, int queue); 99static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 100static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 101static void recycle_rx_pool_skb(struct idt77252_dev *, 102 struct rx_pool *); 103static void add_rx_skb(struct idt77252_dev *, int queue, 104 unsigned int size, unsigned int count); 105 106/* 107 * RSQ Handling. 108 */ 109static int init_rsq(struct idt77252_dev *); 110static void deinit_rsq(struct idt77252_dev *); 111static void idt77252_rx(struct idt77252_dev *); 112 113/* 114 * TSQ handling. 115 */ 116static int init_tsq(struct idt77252_dev *); 117static void deinit_tsq(struct idt77252_dev *); 118static void idt77252_tx(struct idt77252_dev *); 119 120 121/* 122 * ATM Interface. 123 */ 124static void idt77252_dev_close(struct atm_dev *dev); 125static int idt77252_open(struct atm_vcc *vcc); 126static void idt77252_close(struct atm_vcc *vcc); 127static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 128static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 129 int flags); 130static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 131 unsigned long addr); 132static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 133static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 134 int flags); 135static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 136 char *page); 137static void idt77252_softint(void *dev_id); 138 139 140static struct atmdev_ops idt77252_ops = 141{ 142 .dev_close = idt77252_dev_close, 143 .open = idt77252_open, 144 .close = idt77252_close, 145 .send = idt77252_send, 146 .send_oam = idt77252_send_oam, 147 .phy_put = idt77252_phy_put, 148 .phy_get = idt77252_phy_get, 149 .change_qos = idt77252_change_qos, 150 .proc_read = idt77252_proc_read, 151 .owner = THIS_MODULE 152}; 153 154static struct idt77252_dev *idt77252_chain = NULL; 155static unsigned int idt77252_sram_write_errors = 0; 156 157/*****************************************************************************/ 158/* */ 159/* I/O and Utility Bus */ 160/* */ 161/*****************************************************************************/ 162 163static void 164waitfor_idle(struct idt77252_dev *card) 165{ 166 u32 stat; 167 168 stat = readl(SAR_REG_STAT); 169 while (stat & SAR_STAT_CMDBZ) 170 stat = readl(SAR_REG_STAT); 171} 172 173static u32 174read_sram(struct idt77252_dev *card, unsigned long addr) 175{ 176 unsigned long flags; 177 u32 value; 178 179 spin_lock_irqsave(&card->cmd_lock, flags); 180 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 181 waitfor_idle(card); 182 value = readl(SAR_REG_DR0); 183 spin_unlock_irqrestore(&card->cmd_lock, flags); 184 return value; 185} 186 187static void 188write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 189{ 190 unsigned long flags; 191 192 if ((idt77252_sram_write_errors == 0) && 193 (((addr > card->tst[0] + card->tst_size - 2) && 194 (addr < card->tst[0] + card->tst_size)) || 195 ((addr > card->tst[1] + card->tst_size - 2) && 196 (addr < card->tst[1] + card->tst_size)))) { 197 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 198 card->name, addr, value); 199 } 200 201 spin_lock_irqsave(&card->cmd_lock, flags); 202 writel(value, SAR_REG_DR0); 203 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 204 waitfor_idle(card); 205 spin_unlock_irqrestore(&card->cmd_lock, flags); 206} 207 208static u8 209read_utility(void *dev, unsigned long ubus_addr) 210{ 211 struct idt77252_dev *card = dev; 212 unsigned long flags; 213 u8 value; 214 215 if (!card) { 216 printk("Error: No such device.\n"); 217 return -1; 218 } 219 220 spin_lock_irqsave(&card->cmd_lock, flags); 221 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 222 waitfor_idle(card); 223 value = readl(SAR_REG_DR0); 224 spin_unlock_irqrestore(&card->cmd_lock, flags); 225 return value; 226} 227 228static void 229write_utility(void *dev, unsigned long ubus_addr, u8 value) 230{ 231 struct idt77252_dev *card = dev; 232 unsigned long flags; 233 234 if (!card) { 235 printk("Error: No such device.\n"); 236 return; 237 } 238 239 spin_lock_irqsave(&card->cmd_lock, flags); 240 writel((u32) value, SAR_REG_DR0); 241 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 242 waitfor_idle(card); 243 spin_unlock_irqrestore(&card->cmd_lock, flags); 244} 245 246#ifdef HAVE_EEPROM 247static u32 rdsrtab[] = 248{ 249 SAR_GP_EECS | SAR_GP_EESCLK, 250 0, 251 SAR_GP_EESCLK, /* 0 */ 252 0, 253 SAR_GP_EESCLK, /* 0 */ 254 0, 255 SAR_GP_EESCLK, /* 0 */ 256 0, 257 SAR_GP_EESCLK, /* 0 */ 258 0, 259 SAR_GP_EESCLK, /* 0 */ 260 SAR_GP_EEDO, 261 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 262 0, 263 SAR_GP_EESCLK, /* 0 */ 264 SAR_GP_EEDO, 265 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 266}; 267 268static u32 wrentab[] = 269{ 270 SAR_GP_EECS | SAR_GP_EESCLK, 271 0, 272 SAR_GP_EESCLK, /* 0 */ 273 0, 274 SAR_GP_EESCLK, /* 0 */ 275 0, 276 SAR_GP_EESCLK, /* 0 */ 277 0, 278 SAR_GP_EESCLK, /* 0 */ 279 SAR_GP_EEDO, 280 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 281 SAR_GP_EEDO, 282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 283 0, 284 SAR_GP_EESCLK, /* 0 */ 285 0, 286 SAR_GP_EESCLK /* 0 */ 287}; 288 289static u32 rdtab[] = 290{ 291 SAR_GP_EECS | SAR_GP_EESCLK, 292 0, 293 SAR_GP_EESCLK, /* 0 */ 294 0, 295 SAR_GP_EESCLK, /* 0 */ 296 0, 297 SAR_GP_EESCLK, /* 0 */ 298 0, 299 SAR_GP_EESCLK, /* 0 */ 300 0, 301 SAR_GP_EESCLK, /* 0 */ 302 0, 303 SAR_GP_EESCLK, /* 0 */ 304 SAR_GP_EEDO, 305 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 306 SAR_GP_EEDO, 307 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 308}; 309 310static u32 wrtab[] = 311{ 312 SAR_GP_EECS | SAR_GP_EESCLK, 313 0, 314 SAR_GP_EESCLK, /* 0 */ 315 0, 316 SAR_GP_EESCLK, /* 0 */ 317 0, 318 SAR_GP_EESCLK, /* 0 */ 319 0, 320 SAR_GP_EESCLK, /* 0 */ 321 0, 322 SAR_GP_EESCLK, /* 0 */ 323 0, 324 SAR_GP_EESCLK, /* 0 */ 325 SAR_GP_EEDO, 326 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 327 0, 328 SAR_GP_EESCLK /* 0 */ 329}; 330 331static u32 clktab[] = 332{ 333 0, 334 SAR_GP_EESCLK, 335 0, 336 SAR_GP_EESCLK, 337 0, 338 SAR_GP_EESCLK, 339 0, 340 SAR_GP_EESCLK, 341 0, 342 SAR_GP_EESCLK, 343 0, 344 SAR_GP_EESCLK, 345 0, 346 SAR_GP_EESCLK, 347 0, 348 SAR_GP_EESCLK, 349 0 350}; 351 352static u32 353idt77252_read_gp(struct idt77252_dev *card) 354{ 355 u32 gp; 356 357 gp = readl(SAR_REG_GP); 358#if 0 359 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 360#endif 361 return gp; 362} 363 364static void 365idt77252_write_gp(struct idt77252_dev *card, u32 value) 366{ 367 unsigned long flags; 368 369#if 0 370 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 371 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 372 value & SAR_GP_EEDO ? "1" : "0"); 373#endif 374 375 spin_lock_irqsave(&card->cmd_lock, flags); 376 waitfor_idle(card); 377 writel(value, SAR_REG_GP); 378 spin_unlock_irqrestore(&card->cmd_lock, flags); 379} 380 381static u8 382idt77252_eeprom_read_status(struct idt77252_dev *card) 383{ 384 u8 byte; 385 u32 gp; 386 int i, j; 387 388 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 389 390 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) { 391 idt77252_write_gp(card, gp | rdsrtab[i]); 392 udelay(5); 393 } 394 idt77252_write_gp(card, gp | SAR_GP_EECS); 395 udelay(5); 396 397 byte = 0; 398 for (i = 0, j = 0; i < 8; i++) { 399 byte <<= 1; 400 401 idt77252_write_gp(card, gp | clktab[j++]); 402 udelay(5); 403 404 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 405 406 idt77252_write_gp(card, gp | clktab[j++]); 407 udelay(5); 408 } 409 idt77252_write_gp(card, gp | SAR_GP_EECS); 410 udelay(5); 411 412 return byte; 413} 414 415static u8 416idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 417{ 418 u8 byte; 419 u32 gp; 420 int i, j; 421 422 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 423 424 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) { 425 idt77252_write_gp(card, gp | rdtab[i]); 426 udelay(5); 427 } 428 idt77252_write_gp(card, gp | SAR_GP_EECS); 429 udelay(5); 430 431 for (i = 0, j = 0; i < 8; i++) { 432 idt77252_write_gp(card, gp | clktab[j++] | 433 (offset & 1 ? SAR_GP_EEDO : 0)); 434 udelay(5); 435 436 idt77252_write_gp(card, gp | clktab[j++] | 437 (offset & 1 ? SAR_GP_EEDO : 0)); 438 udelay(5); 439 440 offset >>= 1; 441 } 442 idt77252_write_gp(card, gp | SAR_GP_EECS); 443 udelay(5); 444 445 byte = 0; 446 for (i = 0, j = 0; i < 8; i++) { 447 byte <<= 1; 448 449 idt77252_write_gp(card, gp | clktab[j++]); 450 udelay(5); 451 452 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 453 454 idt77252_write_gp(card, gp | clktab[j++]); 455 udelay(5); 456 } 457 idt77252_write_gp(card, gp | SAR_GP_EECS); 458 udelay(5); 459 460 return byte; 461} 462 463static void 464idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 465{ 466 u32 gp; 467 int i, j; 468 469 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 470 471 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) { 472 idt77252_write_gp(card, gp | wrentab[i]); 473 udelay(5); 474 } 475 idt77252_write_gp(card, gp | SAR_GP_EECS); 476 udelay(5); 477 478 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) { 479 idt77252_write_gp(card, gp | wrtab[i]); 480 udelay(5); 481 } 482 idt77252_write_gp(card, gp | SAR_GP_EECS); 483 udelay(5); 484 485 for (i = 0, j = 0; i < 8; i++) { 486 idt77252_write_gp(card, gp | clktab[j++] | 487 (offset & 1 ? SAR_GP_EEDO : 0)); 488 udelay(5); 489 490 idt77252_write_gp(card, gp | clktab[j++] | 491 (offset & 1 ? SAR_GP_EEDO : 0)); 492 udelay(5); 493 494 offset >>= 1; 495 } 496 idt77252_write_gp(card, gp | SAR_GP_EECS); 497 udelay(5); 498 499 for (i = 0, j = 0; i < 8; i++) { 500 idt77252_write_gp(card, gp | clktab[j++] | 501 (data & 1 ? SAR_GP_EEDO : 0)); 502 udelay(5); 503 504 idt77252_write_gp(card, gp | clktab[j++] | 505 (data & 1 ? SAR_GP_EEDO : 0)); 506 udelay(5); 507 508 data >>= 1; 509 } 510 idt77252_write_gp(card, gp | SAR_GP_EECS); 511 udelay(5); 512} 513 514static void 515idt77252_eeprom_init(struct idt77252_dev *card) 516{ 517 u32 gp; 518 519 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 520 521 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 522 udelay(5); 523 idt77252_write_gp(card, gp | SAR_GP_EECS); 524 udelay(5); 525 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 526 udelay(5); 527 idt77252_write_gp(card, gp | SAR_GP_EECS); 528 udelay(5); 529} 530#endif /* HAVE_EEPROM */ 531 532 533#ifdef CONFIG_ATM_IDT77252_DEBUG 534static void 535dump_tct(struct idt77252_dev *card, int index) 536{ 537 unsigned long tct; 538 int i; 539 540 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 541 542 printk("%s: TCT %x:", card->name, index); 543 for (i = 0; i < 8; i++) { 544 printk(" %08x", read_sram(card, tct + i)); 545 } 546 printk("\n"); 547} 548 549static void 550idt77252_tx_dump(struct idt77252_dev *card) 551{ 552 struct atm_vcc *vcc; 553 struct vc_map *vc; 554 int i; 555 556 printk("%s\n", __FUNCTION__); 557 for (i = 0; i < card->tct_size; i++) { 558 vc = card->vcs[i]; 559 if (!vc) 560 continue; 561 562 vcc = NULL; 563 if (vc->rx_vcc) 564 vcc = vc->rx_vcc; 565 else if (vc->tx_vcc) 566 vcc = vc->tx_vcc; 567 568 if (!vcc) 569 continue; 570 571 printk("%s: Connection %d:\n", card->name, vc->index); 572 dump_tct(card, vc->index); 573 } 574} 575#endif 576 577 578/*****************************************************************************/ 579/* */ 580/* SCQ Handling */ 581/* */ 582/*****************************************************************************/ 583 584static int 585sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 586{ 587 struct sb_pool *pool = &card->sbpool[queue]; 588 int index; 589 590 index = pool->index; 591 while (pool->skb[index]) { 592 index = (index + 1) & FBQ_MASK; 593 if (index == pool->index) 594 return -ENOBUFS; 595 } 596 597 pool->skb[index] = skb; 598 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 599 600 pool->index = (index + 1) & FBQ_MASK; 601 return 0; 602} 603 604static void 605sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 606{ 607 unsigned int queue, index; 608 u32 handle; 609 610 handle = IDT77252_PRV_POOL(skb); 611 612 queue = POOL_QUEUE(handle); 613 if (queue > 3) 614 return; 615 616 index = POOL_INDEX(handle); 617 if (index > FBQ_SIZE - 1) 618 return; 619 620 card->sbpool[queue].skb[index] = NULL; 621} 622 623static struct sk_buff * 624sb_pool_skb(struct idt77252_dev *card, u32 handle) 625{ 626 unsigned int queue, index; 627 628 queue = POOL_QUEUE(handle); 629 if (queue > 3) 630 return NULL; 631 632 index = POOL_INDEX(handle); 633 if (index > FBQ_SIZE - 1) 634 return NULL; 635 636 return card->sbpool[queue].skb[index]; 637} 638 639static struct scq_info * 640alloc_scq(struct idt77252_dev *card, int class) 641{ 642 struct scq_info *scq; 643 644 scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL); 645 if (!scq) 646 return NULL; 647 memset(scq, 0, sizeof(struct scq_info)); 648 649 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 650 &scq->paddr); 651 if (scq->base == NULL) { 652 kfree(scq); 653 return NULL; 654 } 655 memset(scq->base, 0, SCQ_SIZE); 656 657 scq->next = scq->base; 658 scq->last = scq->base + (SCQ_ENTRIES - 1); 659 atomic_set(&scq->used, 0); 660 661 spin_lock_init(&scq->lock); 662 spin_lock_init(&scq->skblock); 663 664 skb_queue_head_init(&scq->transmit); 665 skb_queue_head_init(&scq->pending); 666 667 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 668 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 669 670 return scq; 671} 672 673static void 674free_scq(struct idt77252_dev *card, struct scq_info *scq) 675{ 676 struct sk_buff *skb; 677 struct atm_vcc *vcc; 678 679 pci_free_consistent(card->pcidev, SCQ_SIZE, 680 scq->base, scq->paddr); 681 682 while ((skb = skb_dequeue(&scq->transmit))) { 683 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 684 skb->len, PCI_DMA_TODEVICE); 685 686 vcc = ATM_SKB(skb)->vcc; 687 if (vcc->pop) 688 vcc->pop(vcc, skb); 689 else 690 dev_kfree_skb(skb); 691 } 692 693 while ((skb = skb_dequeue(&scq->pending))) { 694 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 695 skb->len, PCI_DMA_TODEVICE); 696 697 vcc = ATM_SKB(skb)->vcc; 698 if (vcc->pop) 699 vcc->pop(vcc, skb); 700 else 701 dev_kfree_skb(skb); 702 } 703 704 kfree(scq); 705} 706 707 708static int 709push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 710{ 711 struct scq_info *scq = vc->scq; 712 unsigned long flags; 713 struct scqe *tbd; 714 int entries; 715 716 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 717 718 atomic_inc(&scq->used); 719 entries = atomic_read(&scq->used); 720 if (entries > (SCQ_ENTRIES - 1)) { 721 atomic_dec(&scq->used); 722 goto out; 723 } 724 725 skb_queue_tail(&scq->transmit, skb); 726 727 spin_lock_irqsave(&vc->lock, flags); 728 if (vc->estimator) { 729 struct atm_vcc *vcc = vc->tx_vcc; 730 struct sock *sk = sk_atm(vcc); 731 732 vc->estimator->cells += (skb->len + 47) / 48; 733 if (atomic_read(&sk->sk_wmem_alloc) > 734 (sk->sk_sndbuf >> 1)) { 735 u32 cps = vc->estimator->maxcps; 736 737 vc->estimator->cps = cps; 738 vc->estimator->avcps = cps << 5; 739 if (vc->lacr < vc->init_er) { 740 vc->lacr = vc->init_er; 741 writel(TCMDQ_LACR | (vc->lacr << 16) | 742 vc->index, SAR_REG_TCMDQ); 743 } 744 } 745 } 746 spin_unlock_irqrestore(&vc->lock, flags); 747 748 tbd = &IDT77252_PRV_TBD(skb); 749 750 spin_lock_irqsave(&scq->lock, flags); 751 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 752 SAR_TBD_TSIF | SAR_TBD_GTSI); 753 scq->next->word_2 = cpu_to_le32(tbd->word_2); 754 scq->next->word_3 = cpu_to_le32(tbd->word_3); 755 scq->next->word_4 = cpu_to_le32(tbd->word_4); 756 757 if (scq->next == scq->last) 758 scq->next = scq->base; 759 else 760 scq->next++; 761 762 write_sram(card, scq->scd, 763 scq->paddr + 764 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 765 spin_unlock_irqrestore(&scq->lock, flags); 766 767 scq->trans_start = jiffies; 768 769 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 770 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 771 SAR_REG_TCMDQ); 772 } 773 774 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 775 776 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 777 card->name, atomic_read(&scq->used), 778 read_sram(card, scq->scd + 1), scq->next); 779 780 return 0; 781 782out: 783 if (time_after(jiffies, scq->trans_start + HZ)) { 784 printk("%s: Error pushing TBD for %d.%d\n", 785 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 786#ifdef CONFIG_ATM_IDT77252_DEBUG 787 idt77252_tx_dump(card); 788#endif 789 scq->trans_start = jiffies; 790 } 791 792 return -ENOBUFS; 793} 794 795 796static void 797drain_scq(struct idt77252_dev *card, struct vc_map *vc) 798{ 799 struct scq_info *scq = vc->scq; 800 struct sk_buff *skb; 801 struct atm_vcc *vcc; 802 803 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 804 card->name, atomic_read(&scq->used), scq->next); 805 806 skb = skb_dequeue(&scq->transmit); 807 if (skb) { 808 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 809 810 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 811 skb->len, PCI_DMA_TODEVICE); 812 813 vcc = ATM_SKB(skb)->vcc; 814 815 if (vcc->pop) 816 vcc->pop(vcc, skb); 817 else 818 dev_kfree_skb(skb); 819 820 atomic_inc(&vcc->stats->tx); 821 } 822 823 atomic_dec(&scq->used); 824 825 spin_lock(&scq->skblock); 826 while ((skb = skb_dequeue(&scq->pending))) { 827 if (push_on_scq(card, vc, skb)) { 828 skb_queue_head(&vc->scq->pending, skb); 829 break; 830 } 831 } 832 spin_unlock(&scq->skblock); 833} 834 835static int 836queue_skb(struct idt77252_dev *card, struct vc_map *vc, 837 struct sk_buff *skb, int oam) 838{ 839 struct atm_vcc *vcc; 840 struct scqe *tbd; 841 unsigned long flags; 842 int error; 843 int aal; 844 845 if (skb->len == 0) { 846 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 847 return -EINVAL; 848 } 849 850 TXPRINTK("%s: Sending %d bytes of data.\n", 851 card->name, skb->len); 852 853 tbd = &IDT77252_PRV_TBD(skb); 854 vcc = ATM_SKB(skb)->vcc; 855 856 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 857 skb->len, PCI_DMA_TODEVICE); 858 859 error = -EINVAL; 860 861 if (oam) { 862 if (skb->len != 52) 863 goto errout; 864 865 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 866 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 867 tbd->word_3 = 0x00000000; 868 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 869 (skb->data[2] << 8) | (skb->data[3] << 0); 870 871 if (test_bit(VCF_RSV, &vc->flags)) 872 vc = card->vcs[0]; 873 874 goto done; 875 } 876 877 if (test_bit(VCF_RSV, &vc->flags)) { 878 printk("%s: Trying to transmit on reserved VC\n", card->name); 879 goto errout; 880 } 881 882 aal = vcc->qos.aal; 883 884 switch (aal) { 885 case ATM_AAL0: 886 case ATM_AAL34: 887 if (skb->len > 52) 888 goto errout; 889 890 if (aal == ATM_AAL0) 891 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 892 ATM_CELL_PAYLOAD; 893 else 894 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 895 ATM_CELL_PAYLOAD; 896 897 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 898 tbd->word_3 = 0x00000000; 899 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 900 (skb->data[2] << 8) | (skb->data[3] << 0); 901 break; 902 903 case ATM_AAL5: 904 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 905 tbd->word_2 = IDT77252_PRV_PADDR(skb); 906 tbd->word_3 = skb->len; 907 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 908 (vcc->vci << SAR_TBD_VCI_SHIFT); 909 break; 910 911 case ATM_AAL1: 912 case ATM_AAL2: 913 default: 914 printk("%s: Traffic type not supported.\n", card->name); 915 error = -EPROTONOSUPPORT; 916 goto errout; 917 } 918 919done: 920 spin_lock_irqsave(&vc->scq->skblock, flags); 921 skb_queue_tail(&vc->scq->pending, skb); 922 923 while ((skb = skb_dequeue(&vc->scq->pending))) { 924 if (push_on_scq(card, vc, skb)) { 925 skb_queue_head(&vc->scq->pending, skb); 926 break; 927 } 928 } 929 spin_unlock_irqrestore(&vc->scq->skblock, flags); 930 931 return 0; 932 933errout: 934 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 935 skb->len, PCI_DMA_TODEVICE); 936 return error; 937} 938 939static unsigned long 940get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 941{ 942 int i; 943 944 for (i = 0; i < card->scd_size; i++) { 945 if (!card->scd2vc[i]) { 946 card->scd2vc[i] = vc; 947 vc->scd_index = i; 948 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 949 } 950 } 951 return 0; 952} 953 954static void 955fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 956{ 957 write_sram(card, scq->scd, scq->paddr); 958 write_sram(card, scq->scd + 1, 0x00000000); 959 write_sram(card, scq->scd + 2, 0xffffffff); 960 write_sram(card, scq->scd + 3, 0x00000000); 961} 962 963static void 964clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 965{ 966 return; 967} 968 969/*****************************************************************************/ 970/* */ 971/* RSQ Handling */ 972/* */ 973/*****************************************************************************/ 974 975static int 976init_rsq(struct idt77252_dev *card) 977{ 978 struct rsq_entry *rsqe; 979 980 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 981 &card->rsq.paddr); 982 if (card->rsq.base == NULL) { 983 printk("%s: can't allocate RSQ.\n", card->name); 984 return -1; 985 } 986 memset(card->rsq.base, 0, RSQSIZE); 987 988 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 989 card->rsq.next = card->rsq.last; 990 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 991 rsqe->word_4 = 0; 992 993 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 994 SAR_REG_RSQH); 995 writel(card->rsq.paddr, SAR_REG_RSQB); 996 997 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 998 (unsigned long) card->rsq.base, 999 readl(SAR_REG_RSQB)); 1000 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 1001 card->name, 1002 readl(SAR_REG_RSQH), 1003 readl(SAR_REG_RSQB), 1004 readl(SAR_REG_RSQT)); 1005 1006 return 0; 1007} 1008 1009static void 1010deinit_rsq(struct idt77252_dev *card) 1011{ 1012 pci_free_consistent(card->pcidev, RSQSIZE, 1013 card->rsq.base, card->rsq.paddr); 1014} 1015 1016static void 1017dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1018{ 1019 struct atm_vcc *vcc; 1020 struct sk_buff *skb; 1021 struct rx_pool *rpp; 1022 struct vc_map *vc; 1023 u32 header, vpi, vci; 1024 u32 stat; 1025 int i; 1026 1027 stat = le32_to_cpu(rsqe->word_4); 1028 1029 if (stat & SAR_RSQE_IDLE) { 1030 RXPRINTK("%s: message about inactive connection.\n", 1031 card->name); 1032 return; 1033 } 1034 1035 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1036 if (skb == NULL) { 1037 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1038 card->name, __FUNCTION__, 1039 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1040 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1041 return; 1042 } 1043 1044 header = le32_to_cpu(rsqe->word_1); 1045 vpi = (header >> 16) & 0x00ff; 1046 vci = (header >> 0) & 0xffff; 1047 1048 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1049 card->name, vpi, vci, skb, skb->data); 1050 1051 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1052 printk("%s: SDU received for out-of-range vc %u.%u\n", 1053 card->name, vpi, vci); 1054 recycle_rx_skb(card, skb); 1055 return; 1056 } 1057 1058 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1059 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1060 printk("%s: SDU received on non RX vc %u.%u\n", 1061 card->name, vpi, vci); 1062 recycle_rx_skb(card, skb); 1063 return; 1064 } 1065 1066 vcc = vc->rx_vcc; 1067 1068 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1069 skb->end - skb->data, PCI_DMA_FROMDEVICE); 1070 1071 if ((vcc->qos.aal == ATM_AAL0) || 1072 (vcc->qos.aal == ATM_AAL34)) { 1073 struct sk_buff *sb; 1074 unsigned char *cell; 1075 u32 aal0; 1076 1077 cell = skb->data; 1078 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1079 if ((sb = dev_alloc_skb(64)) == NULL) { 1080 printk("%s: Can't allocate buffers for aal0.\n", 1081 card->name); 1082 atomic_add(i, &vcc->stats->rx_drop); 1083 break; 1084 } 1085 if (!atm_charge(vcc, sb->truesize)) { 1086 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1087 card->name); 1088 atomic_add(i - 1, &vcc->stats->rx_drop); 1089 dev_kfree_skb(sb); 1090 break; 1091 } 1092 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1093 (vci << ATM_HDR_VCI_SHIFT); 1094 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1095 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1096 1097 *((u32 *) sb->data) = aal0; 1098 skb_put(sb, sizeof(u32)); 1099 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1100 cell, ATM_CELL_PAYLOAD); 1101 1102 ATM_SKB(sb)->vcc = vcc; 1103 __net_timestamp(sb); 1104 vcc->push(vcc, sb); 1105 atomic_inc(&vcc->stats->rx); 1106 1107 cell += ATM_CELL_PAYLOAD; 1108 } 1109 1110 recycle_rx_skb(card, skb); 1111 return; 1112 } 1113 if (vcc->qos.aal != ATM_AAL5) { 1114 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1115 card->name, vcc->qos.aal); 1116 recycle_rx_skb(card, skb); 1117 return; 1118 } 1119 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1120 1121 rpp = &vc->rcv.rx_pool; 1122 1123 rpp->len += skb->len; 1124 if (!rpp->count++) 1125 rpp->first = skb; 1126 *rpp->last = skb; 1127 rpp->last = &skb->next; 1128 1129 if (stat & SAR_RSQE_EPDU) { 1130 unsigned char *l1l2; 1131 unsigned int len; 1132 1133 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1134 1135 len = (l1l2[0] << 8) | l1l2[1]; 1136 len = len ? len : 0x10000; 1137 1138 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1139 1140 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1141 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1142 "(CDC: %08x)\n", 1143 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1144 recycle_rx_pool_skb(card, rpp); 1145 atomic_inc(&vcc->stats->rx_err); 1146 return; 1147 } 1148 if (stat & SAR_RSQE_CRC) { 1149 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1150 recycle_rx_pool_skb(card, rpp); 1151 atomic_inc(&vcc->stats->rx_err); 1152 return; 1153 } 1154 if (rpp->count > 1) { 1155 struct sk_buff *sb; 1156 1157 skb = dev_alloc_skb(rpp->len); 1158 if (!skb) { 1159 RXPRINTK("%s: Can't alloc RX skb.\n", 1160 card->name); 1161 recycle_rx_pool_skb(card, rpp); 1162 atomic_inc(&vcc->stats->rx_err); 1163 return; 1164 } 1165 if (!atm_charge(vcc, skb->truesize)) { 1166 recycle_rx_pool_skb(card, rpp); 1167 dev_kfree_skb(skb); 1168 return; 1169 } 1170 sb = rpp->first; 1171 for (i = 0; i < rpp->count; i++) { 1172 memcpy(skb_put(skb, sb->len), 1173 sb->data, sb->len); 1174 sb = sb->next; 1175 } 1176 1177 recycle_rx_pool_skb(card, rpp); 1178 1179 skb_trim(skb, len); 1180 ATM_SKB(skb)->vcc = vcc; 1181 __net_timestamp(skb); 1182 1183 vcc->push(vcc, skb); 1184 atomic_inc(&vcc->stats->rx); 1185 1186 return; 1187 } 1188 1189 skb->next = NULL; 1190 flush_rx_pool(card, rpp); 1191 1192 if (!atm_charge(vcc, skb->truesize)) { 1193 recycle_rx_skb(card, skb); 1194 return; 1195 } 1196 1197 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1198 skb->end - skb->data, PCI_DMA_FROMDEVICE); 1199 sb_pool_remove(card, skb); 1200 1201 skb_trim(skb, len); 1202 ATM_SKB(skb)->vcc = vcc; 1203 __net_timestamp(skb); 1204 1205 vcc->push(vcc, skb); 1206 atomic_inc(&vcc->stats->rx); 1207 1208 if (skb->truesize > SAR_FB_SIZE_3) 1209 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1210 else if (skb->truesize > SAR_FB_SIZE_2) 1211 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1212 else if (skb->truesize > SAR_FB_SIZE_1) 1213 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1214 else 1215 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1216 return; 1217 } 1218} 1219 1220static void 1221idt77252_rx(struct idt77252_dev *card) 1222{ 1223 struct rsq_entry *rsqe; 1224 1225 if (card->rsq.next == card->rsq.last) 1226 rsqe = card->rsq.base; 1227 else 1228 rsqe = card->rsq.next + 1; 1229 1230 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1231 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1232 return; 1233 } 1234 1235 do { 1236 dequeue_rx(card, rsqe); 1237 rsqe->word_4 = 0; 1238 card->rsq.next = rsqe; 1239 if (card->rsq.next == card->rsq.last) 1240 rsqe = card->rsq.base; 1241 else 1242 rsqe = card->rsq.next + 1; 1243 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1244 1245 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1246 SAR_REG_RSQH); 1247} 1248 1249static void 1250idt77252_rx_raw(struct idt77252_dev *card) 1251{ 1252 struct sk_buff *queue; 1253 u32 head, tail; 1254 struct atm_vcc *vcc; 1255 struct vc_map *vc; 1256 struct sk_buff *sb; 1257 1258 if (card->raw_cell_head == NULL) { 1259 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1260 card->raw_cell_head = sb_pool_skb(card, handle); 1261 } 1262 1263 queue = card->raw_cell_head; 1264 if (!queue) 1265 return; 1266 1267 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1268 tail = readl(SAR_REG_RAWCT); 1269 1270 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1271 queue->end - queue->head - 16, 1272 PCI_DMA_FROMDEVICE); 1273 1274 while (head != tail) { 1275 unsigned int vpi, vci, pti; 1276 u32 header; 1277 1278 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1279 1280 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1281 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1282 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1283 1284#ifdef CONFIG_ATM_IDT77252_DEBUG 1285 if (debug & DBG_RAW_CELL) { 1286 int i; 1287 1288 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1289 card->name, (header >> 28) & 0x000f, 1290 (header >> 20) & 0x00ff, 1291 (header >> 4) & 0xffff, 1292 (header >> 1) & 0x0007, 1293 (header >> 0) & 0x0001); 1294 for (i = 16; i < 64; i++) 1295 printk(" %02x", queue->data[i]); 1296 printk("\n"); 1297 } 1298#endif 1299 1300 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1301 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1302 card->name, vpi, vci); 1303 goto drop; 1304 } 1305 1306 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1307 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1308 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1309 card->name, vpi, vci); 1310 goto drop; 1311 } 1312 1313 vcc = vc->rx_vcc; 1314 1315 if (vcc->qos.aal != ATM_AAL0) { 1316 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1317 card->name, vpi, vci); 1318 atomic_inc(&vcc->stats->rx_drop); 1319 goto drop; 1320 } 1321 1322 if ((sb = dev_alloc_skb(64)) == NULL) { 1323 printk("%s: Can't allocate buffers for AAL0.\n", 1324 card->name); 1325 atomic_inc(&vcc->stats->rx_err); 1326 goto drop; 1327 } 1328 1329 if (!atm_charge(vcc, sb->truesize)) { 1330 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1331 card->name); 1332 dev_kfree_skb(sb); 1333 goto drop; 1334 } 1335 1336 *((u32 *) sb->data) = header; 1337 skb_put(sb, sizeof(u32)); 1338 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1339 ATM_CELL_PAYLOAD); 1340 1341 ATM_SKB(sb)->vcc = vcc; 1342 __net_timestamp(sb); 1343 vcc->push(vcc, sb); 1344 atomic_inc(&vcc->stats->rx); 1345 1346drop: 1347 skb_pull(queue, 64); 1348 1349 head = IDT77252_PRV_PADDR(queue) 1350 + (queue->data - queue->head - 16); 1351 1352 if (queue->len < 128) { 1353 struct sk_buff *next; 1354 u32 handle; 1355 1356 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1357 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1358 1359 next = sb_pool_skb(card, handle); 1360 recycle_rx_skb(card, queue); 1361 1362 if (next) { 1363 card->raw_cell_head = next; 1364 queue = card->raw_cell_head; 1365 pci_dma_sync_single_for_cpu(card->pcidev, 1366 IDT77252_PRV_PADDR(queue), 1367 queue->end - queue->data, 1368 PCI_DMA_FROMDEVICE); 1369 } else { 1370 card->raw_cell_head = NULL; 1371 printk("%s: raw cell queue overrun\n", 1372 card->name); 1373 break; 1374 } 1375 } 1376 } 1377} 1378 1379 1380/*****************************************************************************/ 1381/* */ 1382/* TSQ Handling */ 1383/* */ 1384/*****************************************************************************/ 1385 1386static int 1387init_tsq(struct idt77252_dev *card) 1388{ 1389 struct tsq_entry *tsqe; 1390 1391 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1392 &card->tsq.paddr); 1393 if (card->tsq.base == NULL) { 1394 printk("%s: can't allocate TSQ.\n", card->name); 1395 return -1; 1396 } 1397 memset(card->tsq.base, 0, TSQSIZE); 1398 1399 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1400 card->tsq.next = card->tsq.last; 1401 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1402 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1403 1404 writel(card->tsq.paddr, SAR_REG_TSQB); 1405 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1406 SAR_REG_TSQH); 1407 1408 return 0; 1409} 1410 1411static void 1412deinit_tsq(struct idt77252_dev *card) 1413{ 1414 pci_free_consistent(card->pcidev, TSQSIZE, 1415 card->tsq.base, card->tsq.paddr); 1416} 1417 1418static void 1419idt77252_tx(struct idt77252_dev *card) 1420{ 1421 struct tsq_entry *tsqe; 1422 unsigned int vpi, vci; 1423 struct vc_map *vc; 1424 u32 conn, stat; 1425 1426 if (card->tsq.next == card->tsq.last) 1427 tsqe = card->tsq.base; 1428 else 1429 tsqe = card->tsq.next + 1; 1430 1431 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1432 card->tsq.base, card->tsq.next, card->tsq.last); 1433 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1434 readl(SAR_REG_TSQB), 1435 readl(SAR_REG_TSQT), 1436 readl(SAR_REG_TSQH)); 1437 1438 stat = le32_to_cpu(tsqe->word_2); 1439 1440 if (stat & SAR_TSQE_INVALID) 1441 return; 1442 1443 do { 1444 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1445 le32_to_cpu(tsqe->word_1), 1446 le32_to_cpu(tsqe->word_2)); 1447 1448 switch (stat & SAR_TSQE_TYPE) { 1449 case SAR_TSQE_TYPE_TIMER: 1450 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1451 break; 1452 1453 case SAR_TSQE_TYPE_IDLE: 1454 1455 conn = le32_to_cpu(tsqe->word_1); 1456 1457 if (SAR_TSQE_TAG(stat) == 0x10) { 1458#ifdef NOTDEF 1459 printk("%s: Connection %d halted.\n", 1460 card->name, 1461 le32_to_cpu(tsqe->word_1) & 0x1fff); 1462#endif 1463 break; 1464 } 1465 1466 vc = card->vcs[conn & 0x1fff]; 1467 if (!vc) { 1468 printk("%s: could not find VC from conn %d\n", 1469 card->name, conn & 0x1fff); 1470 break; 1471 } 1472 1473 printk("%s: Connection %d IDLE.\n", 1474 card->name, vc->index); 1475 1476 set_bit(VCF_IDLE, &vc->flags); 1477 break; 1478 1479 case SAR_TSQE_TYPE_TSR: 1480 1481 conn = le32_to_cpu(tsqe->word_1); 1482 1483 vc = card->vcs[conn & 0x1fff]; 1484 if (!vc) { 1485 printk("%s: no VC at index %d\n", 1486 card->name, 1487 le32_to_cpu(tsqe->word_1) & 0x1fff); 1488 break; 1489 } 1490 1491 drain_scq(card, vc); 1492 break; 1493 1494 case SAR_TSQE_TYPE_TBD_COMP: 1495 1496 conn = le32_to_cpu(tsqe->word_1); 1497 1498 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1499 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1500 1501 if (vpi >= (1 << card->vpibits) || 1502 vci >= (1 << card->vcibits)) { 1503 printk("%s: TBD complete: " 1504 "out of range VPI.VCI %u.%u\n", 1505 card->name, vpi, vci); 1506 break; 1507 } 1508 1509 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1510 if (!vc) { 1511 printk("%s: TBD complete: " 1512 "no VC at VPI.VCI %u.%u\n", 1513 card->name, vpi, vci); 1514 break; 1515 } 1516 1517 drain_scq(card, vc); 1518 break; 1519 } 1520 1521 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1522 1523 card->tsq.next = tsqe; 1524 if (card->tsq.next == card->tsq.last) 1525 tsqe = card->tsq.base; 1526 else 1527 tsqe = card->tsq.next + 1; 1528 1529 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1530 card->tsq.base, card->tsq.next, card->tsq.last); 1531 1532 stat = le32_to_cpu(tsqe->word_2); 1533 1534 } while (!(stat & SAR_TSQE_INVALID)); 1535 1536 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1537 SAR_REG_TSQH); 1538 1539 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1540 card->index, readl(SAR_REG_TSQH), 1541 readl(SAR_REG_TSQT), card->tsq.next); 1542} 1543 1544 1545static void 1546tst_timer(unsigned long data) 1547{ 1548 struct idt77252_dev *card = (struct idt77252_dev *)data; 1549 unsigned long base, idle, jump; 1550 unsigned long flags; 1551 u32 pc; 1552 int e; 1553 1554 spin_lock_irqsave(&card->tst_lock, flags); 1555 1556 base = card->tst[card->tst_index]; 1557 idle = card->tst[card->tst_index ^ 1]; 1558 1559 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1560 jump = base + card->tst_size - 2; 1561 1562 pc = readl(SAR_REG_NOW) >> 2; 1563 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1564 mod_timer(&card->tst_timer, jiffies + 1); 1565 goto out; 1566 } 1567 1568 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1569 1570 card->tst_index ^= 1; 1571 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1572 1573 base = card->tst[card->tst_index]; 1574 idle = card->tst[card->tst_index ^ 1]; 1575 1576 for (e = 0; e < card->tst_size - 2; e++) { 1577 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1578 write_sram(card, idle + e, 1579 card->soft_tst[e].tste & TSTE_MASK); 1580 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1581 } 1582 } 1583 } 1584 1585 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1586 1587 for (e = 0; e < card->tst_size - 2; e++) { 1588 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1589 write_sram(card, idle + e, 1590 card->soft_tst[e].tste & TSTE_MASK); 1591 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1592 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1593 } 1594 } 1595 1596 jump = base + card->tst_size - 2; 1597 1598 write_sram(card, jump, TSTE_OPC_NULL); 1599 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1600 1601 mod_timer(&card->tst_timer, jiffies + 1); 1602 } 1603 1604out: 1605 spin_unlock_irqrestore(&card->tst_lock, flags); 1606} 1607 1608static int 1609__fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1610 int n, unsigned int opc) 1611{ 1612 unsigned long cl, avail; 1613 unsigned long idle; 1614 int e, r; 1615 u32 data; 1616 1617 avail = card->tst_size - 2; 1618 for (e = 0; e < avail; e++) { 1619 if (card->soft_tst[e].vc == NULL) 1620 break; 1621 } 1622 if (e >= avail) { 1623 printk("%s: No free TST entries found\n", card->name); 1624 return -1; 1625 } 1626 1627 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1628 card->name, vc ? vc->index : -1, e); 1629 1630 r = n; 1631 cl = avail; 1632 data = opc & TSTE_OPC_MASK; 1633 if (vc && (opc != TSTE_OPC_NULL)) 1634 data = opc | vc->index; 1635 1636 idle = card->tst[card->tst_index ^ 1]; 1637 1638 /* 1639 * Fill Soft TST. 1640 */ 1641 while (r > 0) { 1642 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1643 if (vc) 1644 card->soft_tst[e].vc = vc; 1645 else 1646 card->soft_tst[e].vc = (void *)-1; 1647 1648 card->soft_tst[e].tste = data; 1649 if (timer_pending(&card->tst_timer)) 1650 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1651 else { 1652 write_sram(card, idle + e, data); 1653 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1654 } 1655 1656 cl -= card->tst_size; 1657 r--; 1658 } 1659 1660 if (++e == avail) 1661 e = 0; 1662 cl += n; 1663 } 1664 1665 return 0; 1666} 1667 1668static int 1669fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1670{ 1671 unsigned long flags; 1672 int res; 1673 1674 spin_lock_irqsave(&card->tst_lock, flags); 1675 1676 res = __fill_tst(card, vc, n, opc); 1677 1678 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1679 if (!timer_pending(&card->tst_timer)) 1680 mod_timer(&card->tst_timer, jiffies + 1); 1681 1682 spin_unlock_irqrestore(&card->tst_lock, flags); 1683 return res; 1684} 1685 1686static int 1687__clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1688{ 1689 unsigned long idle; 1690 int e; 1691 1692 idle = card->tst[card->tst_index ^ 1]; 1693 1694 for (e = 0; e < card->tst_size - 2; e++) { 1695 if (card->soft_tst[e].vc == vc) { 1696 card->soft_tst[e].vc = NULL; 1697 1698 card->soft_tst[e].tste = TSTE_OPC_VAR; 1699 if (timer_pending(&card->tst_timer)) 1700 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1701 else { 1702 write_sram(card, idle + e, TSTE_OPC_VAR); 1703 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1704 } 1705 } 1706 } 1707 1708 return 0; 1709} 1710 1711static int 1712clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1713{ 1714 unsigned long flags; 1715 int res; 1716 1717 spin_lock_irqsave(&card->tst_lock, flags); 1718 1719 res = __clear_tst(card, vc); 1720 1721 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1722 if (!timer_pending(&card->tst_timer)) 1723 mod_timer(&card->tst_timer, jiffies + 1); 1724 1725 spin_unlock_irqrestore(&card->tst_lock, flags); 1726 return res; 1727} 1728 1729static int 1730change_tst(struct idt77252_dev *card, struct vc_map *vc, 1731 int n, unsigned int opc) 1732{ 1733 unsigned long flags; 1734 int res; 1735 1736 spin_lock_irqsave(&card->tst_lock, flags); 1737 1738 __clear_tst(card, vc); 1739 res = __fill_tst(card, vc, n, opc); 1740 1741 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1742 if (!timer_pending(&card->tst_timer)) 1743 mod_timer(&card->tst_timer, jiffies + 1); 1744 1745 spin_unlock_irqrestore(&card->tst_lock, flags); 1746 return res; 1747} 1748 1749 1750static int 1751set_tct(struct idt77252_dev *card, struct vc_map *vc) 1752{ 1753 unsigned long tct; 1754 1755 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1756 1757 switch (vc->class) { 1758 case SCHED_CBR: 1759 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1760 card->name, tct, vc->scq->scd); 1761 1762 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1763 write_sram(card, tct + 1, 0); 1764 write_sram(card, tct + 2, 0); 1765 write_sram(card, tct + 3, 0); 1766 write_sram(card, tct + 4, 0); 1767 write_sram(card, tct + 5, 0); 1768 write_sram(card, tct + 6, 0); 1769 write_sram(card, tct + 7, 0); 1770 break; 1771 1772 case SCHED_UBR: 1773 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1774 card->name, tct, vc->scq->scd); 1775 1776 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1777 write_sram(card, tct + 1, 0); 1778 write_sram(card, tct + 2, TCT_TSIF); 1779 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1780 write_sram(card, tct + 4, 0); 1781 write_sram(card, tct + 5, vc->init_er); 1782 write_sram(card, tct + 6, 0); 1783 write_sram(card, tct + 7, TCT_FLAG_UBR); 1784 break; 1785 1786 case SCHED_VBR: 1787 case SCHED_ABR: 1788 default: 1789 return -ENOSYS; 1790 } 1791 1792 return 0; 1793} 1794 1795/*****************************************************************************/ 1796/* */ 1797/* FBQ Handling */ 1798/* */ 1799/*****************************************************************************/ 1800 1801static __inline__ int 1802idt77252_fbq_level(struct idt77252_dev *card, int queue) 1803{ 1804 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1805} 1806 1807static __inline__ int 1808idt77252_fbq_full(struct idt77252_dev *card, int queue) 1809{ 1810 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1811} 1812 1813static int 1814push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1815{ 1816 unsigned long flags; 1817 u32 handle; 1818 u32 addr; 1819 1820 skb->data = skb->tail = skb->head; 1821 skb->len = 0; 1822 1823 skb_reserve(skb, 16); 1824 1825 switch (queue) { 1826 case 0: 1827 skb_put(skb, SAR_FB_SIZE_0); 1828 break; 1829 case 1: 1830 skb_put(skb, SAR_FB_SIZE_1); 1831 break; 1832 case 2: 1833 skb_put(skb, SAR_FB_SIZE_2); 1834 break; 1835 case 3: 1836 skb_put(skb, SAR_FB_SIZE_3); 1837 break; 1838 default: 1839 dev_kfree_skb(skb); 1840 return -1; 1841 } 1842 1843 if (idt77252_fbq_full(card, queue)) 1844 return -1; 1845 1846 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1847 1848 handle = IDT77252_PRV_POOL(skb); 1849 addr = IDT77252_PRV_PADDR(skb); 1850 1851 spin_lock_irqsave(&card->cmd_lock, flags); 1852 writel(handle, card->fbq[queue]); 1853 writel(addr, card->fbq[queue]); 1854 spin_unlock_irqrestore(&card->cmd_lock, flags); 1855 1856 return 0; 1857} 1858 1859static void 1860add_rx_skb(struct idt77252_dev *card, int queue, 1861 unsigned int size, unsigned int count) 1862{ 1863 struct sk_buff *skb; 1864 dma_addr_t paddr; 1865 u32 handle; 1866 1867 while (count--) { 1868 skb = dev_alloc_skb(size); 1869 if (!skb) 1870 return; 1871 1872 if (sb_pool_add(card, skb, queue)) { 1873 printk("%s: SB POOL full\n", __FUNCTION__); 1874 goto outfree; 1875 } 1876 1877 paddr = pci_map_single(card->pcidev, skb->data, 1878 skb->end - skb->data, 1879 PCI_DMA_FROMDEVICE); 1880 IDT77252_PRV_PADDR(skb) = paddr; 1881 1882 if (push_rx_skb(card, skb, queue)) { 1883 printk("%s: FB QUEUE full\n", __FUNCTION__); 1884 goto outunmap; 1885 } 1886 } 1887 1888 return; 1889 1890outunmap: 1891 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1892 skb->end - skb->data, PCI_DMA_FROMDEVICE); 1893 1894 handle = IDT77252_PRV_POOL(skb); 1895 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1896 1897outfree: 1898 dev_kfree_skb(skb); 1899} 1900 1901 1902static void 1903recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1904{ 1905 u32 handle = IDT77252_PRV_POOL(skb); 1906 int err; 1907 1908 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1909 skb->end - skb->data, PCI_DMA_FROMDEVICE); 1910 1911 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1912 if (err) { 1913 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1914 skb->end - skb->data, PCI_DMA_FROMDEVICE); 1915 sb_pool_remove(card, skb); 1916 dev_kfree_skb(skb); 1917 } 1918} 1919 1920static void 1921flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1922{ 1923 rpp->len = 0; 1924 rpp->count = 0; 1925 rpp->first = NULL; 1926 rpp->last = &rpp->first; 1927} 1928 1929static void 1930recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1931{ 1932 struct sk_buff *skb, *next; 1933 int i; 1934 1935 skb = rpp->first; 1936 for (i = 0; i < rpp->count; i++) { 1937 next = skb->next; 1938 skb->next = NULL; 1939 recycle_rx_skb(card, skb); 1940 skb = next; 1941 } 1942 flush_rx_pool(card, rpp); 1943} 1944 1945/*****************************************************************************/ 1946/* */ 1947/* ATM Interface */ 1948/* */ 1949/*****************************************************************************/ 1950 1951static void 1952idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1953{ 1954 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1955} 1956 1957static unsigned char 1958idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1959{ 1960 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1961} 1962 1963static inline int 1964idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1965{ 1966 struct atm_dev *dev = vcc->dev; 1967 struct idt77252_dev *card = dev->dev_data; 1968 struct vc_map *vc = vcc->dev_data; 1969 int err; 1970 1971 if (vc == NULL) { 1972 printk("%s: NULL connection in send().\n", card->name); 1973 atomic_inc(&vcc->stats->tx_err); 1974 dev_kfree_skb(skb); 1975 return -EINVAL; 1976 } 1977 if (!test_bit(VCF_TX, &vc->flags)) { 1978 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1979 atomic_inc(&vcc->stats->tx_err); 1980 dev_kfree_skb(skb); 1981 return -EINVAL; 1982 } 1983 1984 switch (vcc->qos.aal) { 1985 case ATM_AAL0: 1986 case ATM_AAL1: 1987 case ATM_AAL5: 1988 break; 1989 default: 1990 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1991 atomic_inc(&vcc->stats->tx_err); 1992 dev_kfree_skb(skb); 1993 return -EINVAL; 1994 } 1995 1996 if (skb_shinfo(skb)->nr_frags != 0) { 1997 printk("%s: No scatter-gather yet.\n", card->name); 1998 atomic_inc(&vcc->stats->tx_err); 1999 dev_kfree_skb(skb); 2000 return -EINVAL; 2001 } 2002 ATM_SKB(skb)->vcc = vcc; 2003 2004 err = queue_skb(card, vc, skb, oam); 2005 if (err) { 2006 atomic_inc(&vcc->stats->tx_err); 2007 dev_kfree_skb(skb); 2008 return err; 2009 } 2010 2011 return 0; 2012} 2013 2014int 2015idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2016{ 2017 return idt77252_send_skb(vcc, skb, 0); 2018} 2019 2020static int 2021idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2022{ 2023 struct atm_dev *dev = vcc->dev; 2024 struct idt77252_dev *card = dev->dev_data; 2025 struct sk_buff *skb; 2026 2027 skb = dev_alloc_skb(64); 2028 if (!skb) { 2029 printk("%s: Out of memory in send_oam().\n", card->name); 2030 atomic_inc(&vcc->stats->tx_err); 2031 return -ENOMEM; 2032 } 2033 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2034 2035 memcpy(skb_put(skb, 52), cell, 52); 2036 2037 return idt77252_send_skb(vcc, skb, 1); 2038} 2039 2040static __inline__ unsigned int 2041idt77252_fls(unsigned int x) 2042{ 2043 int r = 1; 2044 2045 if (x == 0) 2046 return 0; 2047 if (x & 0xffff0000) { 2048 x >>= 16; 2049 r += 16; 2050 } 2051 if (x & 0xff00) { 2052 x >>= 8; 2053 r += 8; 2054 } 2055 if (x & 0xf0) { 2056 x >>= 4; 2057 r += 4; 2058 } 2059 if (x & 0xc) { 2060 x >>= 2; 2061 r += 2; 2062 } 2063 if (x & 0x2) 2064 r += 1; 2065 return r; 2066} 2067 2068static u16 2069idt77252_int_to_atmfp(unsigned int rate) 2070{ 2071 u16 m, e; 2072 2073 if (rate == 0) 2074 return 0; 2075 e = idt77252_fls(rate) - 1; 2076 if (e < 9) 2077 m = (rate - (1 << e)) << (9 - e); 2078 else if (e == 9) 2079 m = (rate - (1 << e)); 2080 else /* e > 9 */ 2081 m = (rate - (1 << e)) >> (e - 9); 2082 return 0x4000 | (e << 9) | m; 2083} 2084 2085static u8 2086idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2087{ 2088 u16 afp; 2089 2090 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2091 if (pcr < 0) 2092 return rate_to_log[(afp >> 5) & 0x1ff]; 2093 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2094} 2095 2096static void 2097idt77252_est_timer(unsigned long data) 2098{ 2099 struct vc_map *vc = (struct vc_map *)data; 2100 struct idt77252_dev *card = vc->card; 2101 struct rate_estimator *est; 2102 unsigned long flags; 2103 u32 rate, cps; 2104 u64 ncells; 2105 u8 lacr; 2106 2107 spin_lock_irqsave(&vc->lock, flags); 2108 est = vc->estimator; 2109 if (!est) 2110 goto out; 2111 2112 ncells = est->cells; 2113 2114 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2115 est->last_cells = ncells; 2116 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2117 est->cps = (est->avcps + 0x1f) >> 5; 2118 2119 cps = est->cps; 2120 if (cps < (est->maxcps >> 4)) 2121 cps = est->maxcps >> 4; 2122 2123 lacr = idt77252_rate_logindex(card, cps); 2124 if (lacr > vc->max_er) 2125 lacr = vc->max_er; 2126 2127 if (lacr != vc->lacr) { 2128 vc->lacr = lacr; 2129 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2130 } 2131 2132 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2133 add_timer(&est->timer); 2134 2135out: 2136 spin_unlock_irqrestore(&vc->lock, flags); 2137} 2138 2139static struct rate_estimator * 2140idt77252_init_est(struct vc_map *vc, int pcr) 2141{ 2142 struct rate_estimator *est; 2143 2144 est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2145 if (!est) 2146 return NULL; 2147 memset(est, 0, sizeof(*est)); 2148 2149 est->maxcps = pcr < 0 ? -pcr : pcr; 2150 est->cps = est->maxcps; 2151 est->avcps = est->cps << 5; 2152 2153 est->interval = 2; /* XXX: make this configurable */ 2154 est->ewma_log = 2; /* XXX: make this configurable */ 2155 init_timer(&est->timer); 2156 est->timer.data = (unsigned long)vc; 2157 est->timer.function = idt77252_est_timer; 2158 2159 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2160 add_timer(&est->timer); 2161 2162 return est; 2163} 2164 2165static int 2166idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2167 struct atm_vcc *vcc, struct atm_qos *qos) 2168{ 2169 int tst_free, tst_used, tst_entries; 2170 unsigned long tmpl, modl; 2171 int tcr, tcra; 2172 2173 if ((qos->txtp.max_pcr == 0) && 2174 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2175 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2176 card->name); 2177 return -EINVAL; 2178 } 2179 2180 tst_used = 0; 2181 tst_free = card->tst_free; 2182 if (test_bit(VCF_TX, &vc->flags)) 2183 tst_used = vc->ntste; 2184 tst_free += tst_used; 2185 2186 tcr = atm_pcr_goal(&qos->txtp); 2187 tcra = tcr >= 0 ? tcr : -tcr; 2188 2189 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2190 2191 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2192 modl = tmpl % (unsigned long)card->utopia_pcr; 2193 2194 tst_entries = (int) (tmpl / card->utopia_pcr); 2195 if (tcr > 0) { 2196 if (modl > 0) 2197 tst_entries++; 2198 } else if (tcr == 0) { 2199 tst_entries = tst_free - SAR_TST_RESERVED; 2200 if (tst_entries <= 0) { 2201 printk("%s: no CBR bandwidth free.\n", card->name); 2202 return -ENOSR; 2203 } 2204 } 2205 2206 if (tst_entries == 0) { 2207 printk("%s: selected CBR bandwidth < granularity.\n", 2208 card->name); 2209 return -EINVAL; 2210 } 2211 2212 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2213 printk("%s: not enough CBR bandwidth free.\n", card->name); 2214 return -ENOSR; 2215 } 2216 2217 vc->ntste = tst_entries; 2218 2219 card->tst_free = tst_free - tst_entries; 2220 if (test_bit(VCF_TX, &vc->flags)) { 2221 if (tst_used == tst_entries) 2222 return 0; 2223 2224 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2225 card->name, tst_used, tst_entries); 2226 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2227 return 0; 2228 } 2229 2230 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2231 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2232 return 0; 2233} 2234 2235static int 2236idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2237 struct atm_vcc *vcc, struct atm_qos *qos) 2238{ 2239 unsigned long flags; 2240 int tcr; 2241 2242 spin_lock_irqsave(&vc->lock, flags); 2243 if (vc->estimator) { 2244 del_timer(&vc->estimator->timer); 2245 kfree(vc->estimator); 2246 vc->estimator = NULL; 2247 } 2248 spin_unlock_irqrestore(&vc->lock, flags); 2249 2250 tcr = atm_pcr_goal(&qos->txtp); 2251 if (tcr == 0) 2252 tcr = card->link_pcr; 2253 2254 vc->estimator = idt77252_init_est(vc, tcr); 2255 2256 vc->class = SCHED_UBR; 2257 vc->init_er = idt77252_rate_logindex(card, tcr); 2258 vc->lacr = vc->init_er; 2259 if (tcr < 0) 2260 vc->max_er = vc->init_er; 2261 else 2262 vc->max_er = 0xff; 2263 2264 return 0; 2265} 2266 2267static int 2268idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2269 struct atm_vcc *vcc, struct atm_qos *qos) 2270{ 2271 int error; 2272 2273 if (test_bit(VCF_TX, &vc->flags)) 2274 return -EBUSY; 2275 2276 switch (qos->txtp.traffic_class) { 2277 case ATM_CBR: 2278 vc->class = SCHED_CBR; 2279 break; 2280 2281 case ATM_UBR: 2282 vc->class = SCHED_UBR; 2283 break; 2284 2285 case ATM_VBR: 2286 case ATM_ABR: 2287 default: 2288 return -EPROTONOSUPPORT; 2289 } 2290 2291 vc->scq = alloc_scq(card, vc->class); 2292 if (!vc->scq) { 2293 printk("%s: can't get SCQ.\n", card->name); 2294 return -ENOMEM; 2295 } 2296 2297 vc->scq->scd = get_free_scd(card, vc); 2298 if (vc->scq->scd == 0) { 2299 printk("%s: no SCD available.\n", card->name); 2300 free_scq(card, vc->scq); 2301 return -ENOMEM; 2302 } 2303 2304 fill_scd(card, vc->scq, vc->class); 2305 2306 if (set_tct(card, vc)) { 2307 printk("%s: class %d not supported.\n", 2308 card->name, qos->txtp.traffic_class); 2309 2310 card->scd2vc[vc->scd_index] = NULL; 2311 free_scq(card, vc->scq); 2312 return -EPROTONOSUPPORT; 2313 } 2314 2315 switch (vc->class) { 2316 case SCHED_CBR: 2317 error = idt77252_init_cbr(card, vc, vcc, qos); 2318 if (error) { 2319 card->scd2vc[vc->scd_index] = NULL; 2320 free_scq(card, vc->scq); 2321 return error; 2322 } 2323 2324 clear_bit(VCF_IDLE, &vc->flags); 2325 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2326 break; 2327 2328 case SCHED_UBR: 2329 error = idt77252_init_ubr(card, vc, vcc, qos); 2330 if (error) { 2331 card->scd2vc[vc->scd_index] = NULL; 2332 free_scq(card, vc->scq); 2333 return error; 2334 } 2335 2336 set_bit(VCF_IDLE, &vc->flags); 2337 break; 2338 } 2339 2340 vc->tx_vcc = vcc; 2341 set_bit(VCF_TX, &vc->flags); 2342 return 0; 2343} 2344 2345static int 2346idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2347 struct atm_vcc *vcc, struct atm_qos *qos) 2348{ 2349 unsigned long flags; 2350 unsigned long addr; 2351 u32 rcte = 0; 2352 2353 if (test_bit(VCF_RX, &vc->flags)) 2354 return -EBUSY; 2355 2356 vc->rx_vcc = vcc; 2357 set_bit(VCF_RX, &vc->flags); 2358 2359 if ((vcc->vci == 3) || (vcc->vci == 4)) 2360 return 0; 2361 2362 flush_rx_pool(card, &vc->rcv.rx_pool); 2363 2364 rcte |= SAR_RCTE_CONNECTOPEN; 2365 rcte |= SAR_RCTE_RAWCELLINTEN; 2366 2367 switch (qos->aal) { 2368 case ATM_AAL0: 2369 rcte |= SAR_RCTE_RCQ; 2370 break; 2371 case ATM_AAL1: 2372 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2373 break; 2374 case ATM_AAL34: 2375 rcte |= SAR_RCTE_AAL34; 2376 break; 2377 case ATM_AAL5: 2378 rcte |= SAR_RCTE_AAL5; 2379 break; 2380 default: 2381 rcte |= SAR_RCTE_RCQ; 2382 break; 2383 } 2384 2385 if (qos->aal != ATM_AAL5) 2386 rcte |= SAR_RCTE_FBP_1; 2387 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2388 rcte |= SAR_RCTE_FBP_3; 2389 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2390 rcte |= SAR_RCTE_FBP_2; 2391 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2392 rcte |= SAR_RCTE_FBP_1; 2393 else 2394 rcte |= SAR_RCTE_FBP_01; 2395 2396 addr = card->rct_base + (vc->index << 2); 2397 2398 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2399 write_sram(card, addr, rcte); 2400 2401 spin_lock_irqsave(&card->cmd_lock, flags); 2402 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2403 waitfor_idle(card); 2404 spin_unlock_irqrestore(&card->cmd_lock, flags); 2405 2406 return 0; 2407} 2408 2409static int 2410idt77252_open(struct atm_vcc *vcc) 2411{ 2412 struct atm_dev *dev = vcc->dev; 2413 struct idt77252_dev *card = dev->dev_data; 2414 struct vc_map *vc; 2415 unsigned int index; 2416 unsigned int inuse; 2417 int error; 2418 int vci = vcc->vci; 2419 short vpi = vcc->vpi; 2420 2421 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2422 return 0; 2423 2424 if (vpi >= (1 << card->vpibits)) { 2425 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2426 return -EINVAL; 2427 } 2428 2429 if (vci >= (1 << card->vcibits)) { 2430 printk("%s: unsupported VCI: %d\n", card->name, vci); 2431 return -EINVAL; 2432 } 2433 2434 set_bit(ATM_VF_ADDR, &vcc->flags); 2435 2436 down(&card->mutex); 2437 2438 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2439 2440 switch (vcc->qos.aal) { 2441 case ATM_AAL0: 2442 case ATM_AAL1: 2443 case ATM_AAL5: 2444 break; 2445 default: 2446 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2447 up(&card->mutex); 2448 return -EPROTONOSUPPORT; 2449 } 2450 2451 index = VPCI2VC(card, vpi, vci); 2452 if (!card->vcs[index]) { 2453 card->vcs[index] = kmalloc(sizeof(struct vc_map), GFP_KERNEL); 2454 if (!card->vcs[index]) { 2455 printk("%s: can't alloc vc in open()\n", card->name); 2456 up(&card->mutex); 2457 return -ENOMEM; 2458 } 2459 memset(card->vcs[index], 0, sizeof(struct vc_map)); 2460 2461 card->vcs[index]->card = card; 2462 card->vcs[index]->index = index; 2463 2464 spin_lock_init(&card->vcs[index]->lock); 2465 } 2466 vc = card->vcs[index]; 2467 2468 vcc->dev_data = vc; 2469 2470 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2471 card->name, vc->index, vcc->vpi, vcc->vci, 2472 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2473 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2474 vcc->qos.rxtp.max_sdu); 2475 2476 inuse = 0; 2477 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2478 test_bit(VCF_TX, &vc->flags)) 2479 inuse = 1; 2480 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2481 test_bit(VCF_RX, &vc->flags)) 2482 inuse += 2; 2483 2484 if (inuse) { 2485 printk("%s: %s vci already in use.\n", card->name, 2486 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2487 up(&card->mutex); 2488 return -EADDRINUSE; 2489 } 2490 2491 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2492 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2493 if (error) { 2494 up(&card->mutex); 2495 return error; 2496 } 2497 } 2498 2499 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2500 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2501 if (error) { 2502 up(&card->mutex); 2503 return error; 2504 } 2505 } 2506 2507 set_bit(ATM_VF_READY, &vcc->flags); 2508 2509 up(&card->mutex); 2510 return 0; 2511} 2512 2513static void 2514idt77252_close(struct atm_vcc *vcc) 2515{ 2516 struct atm_dev *dev = vcc->dev; 2517 struct idt77252_dev *card = dev->dev_data; 2518 struct vc_map *vc = vcc->dev_data; 2519 unsigned long flags; 2520 unsigned long addr; 2521 unsigned long timeout; 2522 2523 down(&card->mutex); 2524 2525 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2526 card->name, vc->index, vcc->vpi, vcc->vci); 2527 2528 clear_bit(ATM_VF_READY, &vcc->flags); 2529 2530 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2531 2532 spin_lock_irqsave(&vc->lock, flags); 2533 clear_bit(VCF_RX, &vc->flags); 2534 vc->rx_vcc = NULL; 2535 spin_unlock_irqrestore(&vc->lock, flags); 2536 2537 if ((vcc->vci == 3) || (vcc->vci == 4)) 2538 goto done; 2539 2540 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2541 2542 spin_lock_irqsave(&card->cmd_lock, flags); 2543 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2544 waitfor_idle(card); 2545 spin_unlock_irqrestore(&card->cmd_lock, flags); 2546 2547 if (vc->rcv.rx_pool.count) { 2548 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2549 card->name); 2550 2551 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2552 } 2553 } 2554 2555done: 2556 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2557 2558 spin_lock_irqsave(&vc->lock, flags); 2559 clear_bit(VCF_TX, &vc->flags); 2560 clear_bit(VCF_IDLE, &vc->flags); 2561 clear_bit(VCF_RSV, &vc->flags); 2562 vc->tx_vcc = NULL; 2563 2564 if (vc->estimator) { 2565 del_timer(&vc->estimator->timer); 2566 kfree(vc->estimator); 2567 vc->estimator = NULL; 2568 } 2569 spin_unlock_irqrestore(&vc->lock, flags); 2570 2571 timeout = 5 * 1000; 2572 while (atomic_read(&vc->scq->used) > 0) { 2573 timeout = msleep_interruptible(timeout); 2574 if (!timeout) 2575 break; 2576 } 2577 if (!timeout) 2578 printk("%s: SCQ drain timeout: %u used\n", 2579 card->name, atomic_read(&vc->scq->used)); 2580 2581 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2582 clear_scd(card, vc->scq, vc->class); 2583 2584 if (vc->class == SCHED_CBR) { 2585 clear_tst(card, vc); 2586 card->tst_free += vc->ntste; 2587 vc->ntste = 0; 2588 } 2589 2590 card->scd2vc[vc->scd_index] = NULL; 2591 free_scq(card, vc->scq); 2592 } 2593 2594 up(&card->mutex); 2595} 2596 2597static int 2598idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2599{ 2600 struct atm_dev *dev = vcc->dev; 2601 struct idt77252_dev *card = dev->dev_data; 2602 struct vc_map *vc = vcc->dev_data; 2603 int error = 0; 2604 2605 down(&card->mutex); 2606 2607 if (qos->txtp.traffic_class != ATM_NONE) { 2608 if (!test_bit(VCF_TX, &vc->flags)) { 2609 error = idt77252_init_tx(card, vc, vcc, qos); 2610 if (error) 2611 goto out; 2612 } else { 2613 switch (qos->txtp.traffic_class) { 2614 case ATM_CBR: 2615 error = idt77252_init_cbr(card, vc, vcc, qos); 2616 if (error) 2617 goto out; 2618 break; 2619 2620 case ATM_UBR: 2621 error = idt77252_init_ubr(card, vc, vcc, qos); 2622 if (error) 2623 goto out; 2624 2625 if (!test_bit(VCF_IDLE, &vc->flags)) { 2626 writel(TCMDQ_LACR | (vc->lacr << 16) | 2627 vc->index, SAR_REG_TCMDQ); 2628 } 2629 break; 2630 2631 case ATM_VBR: 2632 case ATM_ABR: 2633 error = -EOPNOTSUPP; 2634 goto out; 2635 } 2636 } 2637 } 2638 2639 if ((qos->rxtp.traffic_class != ATM_NONE) && 2640 !test_bit(VCF_RX, &vc->flags)) { 2641 error = idt77252_init_rx(card, vc, vcc, qos); 2642 if (error) 2643 goto out; 2644 } 2645 2646 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2647 2648 set_bit(ATM_VF_HASQOS, &vcc->flags); 2649 2650out: 2651 up(&card->mutex); 2652 return error; 2653} 2654 2655static int 2656idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2657{ 2658 struct idt77252_dev *card = dev->dev_data; 2659 int i, left; 2660 2661 left = (int) *pos; 2662 if (!left--) 2663 return sprintf(page, "IDT77252 Interrupts:\n"); 2664 if (!left--) 2665 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2666 if (!left--) 2667 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2668 if (!left--) 2669 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2670 if (!left--) 2671 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2672 if (!left--) 2673 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2674 if (!left--) 2675 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2676 if (!left--) 2677 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2678 if (!left--) 2679 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2680 if (!left--) 2681 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2682 if (!left--) 2683 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2684 if (!left--) 2685 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2686 if (!left--) 2687 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2688 if (!left--) 2689 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2690 if (!left--) 2691 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2692 2693 for (i = 0; i < card->tct_size; i++) { 2694 unsigned long tct; 2695 struct atm_vcc *vcc; 2696 struct vc_map *vc; 2697 char *p; 2698 2699 vc = card->vcs[i]; 2700 if (!vc) 2701 continue; 2702 2703 vcc = NULL; 2704 if (vc->tx_vcc) 2705 vcc = vc->tx_vcc; 2706 if (!vcc) 2707 continue; 2708 if (left--) 2709 continue; 2710 2711 p = page; 2712 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2713 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2714 2715 for (i = 0; i < 8; i++) 2716 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2717 p += sprintf(p, "\n"); 2718 return p - page; 2719 } 2720 return 0; 2721} 2722 2723/*****************************************************************************/ 2724/* */ 2725/* Interrupt handler */ 2726/* */ 2727/*****************************************************************************/ 2728 2729static void 2730idt77252_collect_stat(struct idt77252_dev *card) 2731{ 2732 u32 cdc, vpec, icc; 2733 2734 cdc = readl(SAR_REG_CDC); 2735 vpec = readl(SAR_REG_VPEC); 2736 icc = readl(SAR_REG_ICC); 2737 2738#ifdef NOTDEF 2739 printk("%s:", card->name); 2740 2741 if (cdc & 0x7f0000) { 2742 char *s = ""; 2743 2744 printk(" ["); 2745 if (cdc & (1 << 22)) { 2746 printk("%sRM ID", s); 2747 s = " | "; 2748 } 2749 if (cdc & (1 << 21)) { 2750 printk("%sCON TAB", s); 2751 s = " | "; 2752 } 2753 if (cdc & (1 << 20)) { 2754 printk("%sNO FB", s); 2755 s = " | "; 2756 } 2757 if (cdc & (1 << 19)) { 2758 printk("%sOAM CRC", s); 2759 s = " | "; 2760 } 2761 if (cdc & (1 << 18)) { 2762 printk("%sRM CRC", s); 2763 s = " | "; 2764 } 2765 if (cdc & (1 << 17)) { 2766 printk("%sRM FIFO", s); 2767 s = " | "; 2768 } 2769 if (cdc & (1 << 16)) { 2770 printk("%sRX FIFO", s); 2771 s = " | "; 2772 } 2773 printk("]"); 2774 } 2775 2776 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2777 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2778#endif 2779} 2780 2781static irqreturn_t 2782idt77252_interrupt(int irq, void *dev_id, struct pt_regs *ptregs) 2783{ 2784 struct idt77252_dev *card = dev_id; 2785 u32 stat; 2786 2787 stat = readl(SAR_REG_STAT) & 0xffff; 2788 if (!stat) /* no interrupt for us */ 2789 return IRQ_NONE; 2790 2791 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2792 printk("%s: Re-entering irq_handler()\n", card->name); 2793 goto out; 2794 } 2795 2796 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2797 2798 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2799 INTPRINTK("%s: TSIF\n", card->name); 2800 card->irqstat[15]++; 2801 idt77252_tx(card); 2802 } 2803 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2804 INTPRINTK("%s: TXICP\n", card->name); 2805 card->irqstat[14]++; 2806#ifdef CONFIG_ATM_IDT77252_DEBUG 2807 idt77252_tx_dump(card); 2808#endif 2809 } 2810 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2811 INTPRINTK("%s: TSQF\n", card->name); 2812 card->irqstat[12]++; 2813 idt77252_tx(card); 2814 } 2815 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2816 INTPRINTK("%s: TMROF\n", card->name); 2817 card->irqstat[11]++; 2818 idt77252_collect_stat(card); 2819 } 2820 2821 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2822 INTPRINTK("%s: EPDU\n", card->name); 2823 card->irqstat[5]++; 2824 idt77252_rx(card); 2825 } 2826 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2827 INTPRINTK("%s: RSQAF\n", card->name); 2828 card->irqstat[1]++; 2829 idt77252_rx(card); 2830 } 2831 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2832 INTPRINTK("%s: RSQF\n", card->name); 2833 card->irqstat[6]++; 2834 idt77252_rx(card); 2835 } 2836 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2837 INTPRINTK("%s: RAWCF\n", card->name); 2838 card->irqstat[4]++; 2839 idt77252_rx_raw(card); 2840 } 2841 2842 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2843 INTPRINTK("%s: PHYI", card->name); 2844 card->irqstat[10]++; 2845 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2846 card->atmdev->phy->interrupt(card->atmdev); 2847 } 2848 2849 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2850 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2851 2852 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2853 2854 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2855 2856 if (stat & SAR_STAT_FBQ0A) 2857 card->irqstat[2]++; 2858 if (stat & SAR_STAT_FBQ1A) 2859 card->irqstat[3]++; 2860 if (stat & SAR_STAT_FBQ2A) 2861 card->irqstat[7]++; 2862 if (stat & SAR_STAT_FBQ3A) 2863 card->irqstat[8]++; 2864 2865 schedule_work(&card->tqueue); 2866 } 2867 2868out: 2869 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2870 return IRQ_HANDLED; 2871} 2872 2873static void 2874idt77252_softint(void *dev_id) 2875{ 2876 struct idt77252_dev *card = dev_id; 2877 u32 stat; 2878 int done; 2879 2880 for (done = 1; ; done = 1) { 2881 stat = readl(SAR_REG_STAT) >> 16; 2882 2883 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2884 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2885 done = 0; 2886 } 2887 2888 stat >>= 4; 2889 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2890 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2891 done = 0; 2892 } 2893 2894 stat >>= 4; 2895 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2896 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2897 done = 0; 2898 } 2899 2900 stat >>= 4; 2901 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2902 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2903 done = 0; 2904 } 2905 2906 if (done) 2907 break; 2908 } 2909 2910 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2911} 2912 2913 2914static int 2915open_card_oam(struct idt77252_dev *card) 2916{ 2917 unsigned long flags; 2918 unsigned long addr; 2919 struct vc_map *vc; 2920 int vpi, vci; 2921 int index; 2922 u32 rcte; 2923 2924 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2925 for (vci = 3; vci < 5; vci++) { 2926 index = VPCI2VC(card, vpi, vci); 2927 2928 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL); 2929 if (!vc) { 2930 printk("%s: can't alloc vc\n", card->name); 2931 return -ENOMEM; 2932 } 2933 memset(vc, 0, sizeof(struct vc_map)); 2934 2935 vc->index = index; 2936 card->vcs[index] = vc; 2937 2938 flush_rx_pool(card, &vc->rcv.rx_pool); 2939 2940 rcte = SAR_RCTE_CONNECTOPEN | 2941 SAR_RCTE_RAWCELLINTEN | 2942 SAR_RCTE_RCQ | 2943 SAR_RCTE_FBP_1; 2944 2945 addr = card->rct_base + (vc->index << 2); 2946 write_sram(card, addr, rcte); 2947 2948 spin_lock_irqsave(&card->cmd_lock, flags); 2949 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2950 SAR_REG_CMD); 2951 waitfor_idle(card); 2952 spin_unlock_irqrestore(&card->cmd_lock, flags); 2953 } 2954 } 2955 2956 return 0; 2957} 2958 2959static void 2960close_card_oam(struct idt77252_dev *card) 2961{ 2962 unsigned long flags; 2963 unsigned long addr; 2964 struct vc_map *vc; 2965 int vpi, vci; 2966 int index; 2967 2968 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2969 for (vci = 3; vci < 5; vci++) { 2970 index = VPCI2VC(card, vpi, vci); 2971 vc = card->vcs[index]; 2972 2973 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2974 2975 spin_lock_irqsave(&card->cmd_lock, flags); 2976 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2977 SAR_REG_CMD); 2978 waitfor_idle(card); 2979 spin_unlock_irqrestore(&card->cmd_lock, flags); 2980 2981 if (vc->rcv.rx_pool.count) { 2982 DPRINTK("%s: closing a VC " 2983 "with pending rx buffers.\n", 2984 card->name); 2985 2986 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2987 } 2988 } 2989 } 2990} 2991 2992static int 2993open_card_ubr0(struct idt77252_dev *card) 2994{ 2995 struct vc_map *vc; 2996 2997 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL); 2998 if (!vc) { 2999 printk("%s: can't alloc vc\n", card->name); 3000 return -ENOMEM; 3001 } 3002 memset(vc, 0, sizeof(struct vc_map)); 3003 card->vcs[0] = vc; 3004 vc->class = SCHED_UBR0; 3005 3006 vc->scq = alloc_scq(card, vc->class); 3007 if (!vc->scq) { 3008 printk("%s: can't get SCQ.\n", card->name); 3009 return -ENOMEM; 3010 } 3011 3012 card->scd2vc[0] = vc; 3013 vc->scd_index = 0; 3014 vc->scq->scd = card->scd_base; 3015 3016 fill_scd(card, vc->scq, vc->class); 3017 3018 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 3019 write_sram(card, card->tct_base + 1, 0); 3020 write_sram(card, card->tct_base + 2, 0); 3021 write_sram(card, card->tct_base + 3, 0); 3022 write_sram(card, card->tct_base + 4, 0); 3023 write_sram(card, card->tct_base + 5, 0); 3024 write_sram(card, card->tct_base + 6, 0); 3025 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3026 3027 clear_bit(VCF_IDLE, &vc->flags); 3028 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3029 return 0; 3030} 3031 3032static int 3033idt77252_dev_open(struct idt77252_dev *card) 3034{ 3035 u32 conf; 3036 3037 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3038 printk("%s: SAR not yet initialized.\n", card->name); 3039 return -1; 3040 } 3041 3042 conf = SAR_CFG_RXPTH| /* enable receive path */ 3043 SAR_RX_DELAY | /* interrupt on complete PDU */ 3044 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3045 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3046 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3047 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3048 SAR_CFG_TXEN | /* transmit operation enable */ 3049 SAR_CFG_TXINT | /* interrupt on transmit status */ 3050 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3051 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3052 SAR_CFG_PHYIE /* enable PHY interrupts */ 3053 ; 3054 3055#ifdef CONFIG_ATM_IDT77252_RCV_ALL 3056 /* Test RAW cell receive. */ 3057 conf |= SAR_CFG_VPECA; 3058#endif 3059 3060 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3061 3062 if (open_card_oam(card)) { 3063 printk("%s: Error initializing OAM.\n", card->name); 3064 return -1; 3065 } 3066 3067 if (open_card_ubr0(card)) { 3068 printk("%s: Error initializing UBR0.\n", card->name); 3069 return -1; 3070 } 3071 3072 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3073 return 0; 3074} 3075 3076void 3077idt77252_dev_close(struct atm_dev *dev) 3078{ 3079 struct idt77252_dev *card = dev->dev_data; 3080 u32 conf; 3081 3082 close_card_oam(card); 3083 3084 conf = SAR_CFG_RXPTH | /* enable receive path */ 3085 SAR_RX_DELAY | /* interrupt on complete PDU */ 3086 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3087 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3088 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3089 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3090 SAR_CFG_TXEN | /* transmit operation enable */ 3091 SAR_CFG_TXINT | /* interrupt on transmit status */ 3092 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3093 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3094 ; 3095 3096 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3097 3098 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3099} 3100 3101 3102/*****************************************************************************/ 3103/* */ 3104/* Initialisation and Deinitialization of IDT77252 */ 3105/* */ 3106/*****************************************************************************/ 3107 3108 3109static void 3110deinit_card(struct idt77252_dev *card) 3111{ 3112 struct sk_buff *skb; 3113 int i, j; 3114 3115 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3116 printk("%s: SAR not yet initialized.\n", card->name); 3117 return; 3118 } 3119 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3120 3121 writel(0, SAR_REG_CFG); 3122 3123 if (card->atmdev) 3124 atm_dev_deregister(card->atmdev); 3125 3126 for (i = 0; i < 4; i++) { 3127 for (j = 0; j < FBQ_SIZE; j++) { 3128 skb = card->sbpool[i].skb[j]; 3129 if (skb) { 3130 pci_unmap_single(card->pcidev, 3131 IDT77252_PRV_PADDR(skb), 3132 skb->end - skb->data, 3133 PCI_DMA_FROMDEVICE); 3134 card->sbpool[i].skb[j] = NULL; 3135 dev_kfree_skb(skb); 3136 } 3137 } 3138 } 3139 3140 vfree(card->soft_tst); 3141 3142 vfree(card->scd2vc); 3143 3144 vfree(card->vcs); 3145 3146 if (card->raw_cell_hnd) { 3147 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3148 card->raw_cell_hnd, card->raw_cell_paddr); 3149 } 3150 3151 if (card->rsq.base) { 3152 DIPRINTK("%s: Release RSQ ...\n", card->name); 3153 deinit_rsq(card); 3154 } 3155 3156 if (card->tsq.base) { 3157 DIPRINTK("%s: Release TSQ ...\n", card->name); 3158 deinit_tsq(card); 3159 } 3160 3161 DIPRINTK("idt77252: Release IRQ.\n"); 3162 free_irq(card->pcidev->irq, card); 3163 3164 for (i = 0; i < 4; i++) { 3165 if (card->fbq[i]) 3166 iounmap(card->fbq[i]); 3167 } 3168 3169 if (card->membase) 3170 iounmap(card->membase); 3171 3172 clear_bit(IDT77252_BIT_INIT, &card->flags); 3173 DIPRINTK("%s: Card deinitialized.\n", card->name); 3174} 3175 3176 3177static int __devinit 3178init_sram(struct idt77252_dev *card) 3179{ 3180 int i; 3181 3182 for (i = 0; i < card->sramsize; i += 4) 3183 write_sram(card, (i >> 2), 0); 3184 3185 /* set SRAM layout for THIS card */ 3186 if (card->sramsize == (512 * 1024)) { 3187 card->tct_base = SAR_SRAM_TCT_128_BASE; 3188 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3189 / SAR_SRAM_TCT_SIZE; 3190 card->rct_base = SAR_SRAM_RCT_128_BASE; 3191 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3192 / SAR_SRAM_RCT_SIZE; 3193 card->rt_base = SAR_SRAM_RT_128_BASE; 3194 card->scd_base = SAR_SRAM_SCD_128_BASE; 3195 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3196 / SAR_SRAM_SCD_SIZE; 3197 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3198 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3199 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3200 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3201 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3202 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3203 card->fifo_size = SAR_RXFD_SIZE_32K; 3204 } else { 3205 card->tct_base = SAR_SRAM_TCT_32_BASE; 3206 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3207 / SAR_SRAM_TCT_SIZE; 3208 card->rct_base = SAR_SRAM_RCT_32_BASE; 3209 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3210 / SAR_SRAM_RCT_SIZE; 3211 card->rt_base = SAR_SRAM_RT_32_BASE; 3212 card->scd_base = SAR_SRAM_SCD_32_BASE; 3213 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3214 / SAR_SRAM_SCD_SIZE; 3215 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3216 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3217 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3218 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3219 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3220 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3221 card->fifo_size = SAR_RXFD_SIZE_4K; 3222 } 3223 3224 /* Initialize TCT */ 3225 for (i = 0; i < card->tct_size; i++) { 3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3233 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3234 } 3235 3236 /* Initialize RCT */ 3237 for (i = 0; i < card->rct_size; i++) { 3238 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3239 (u32) SAR_RCTE_RAWCELLINTEN); 3240 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3241 (u32) 0); 3242 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3243 (u32) 0); 3244 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3245 (u32) 0xffffffff); 3246 } 3247 3248 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3249 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3250 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3251 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3252 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3253 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3254 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3255 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3256 3257 /* Initialize rate table */ 3258 for (i = 0; i < 256; i++) { 3259 write_sram(card, card->rt_base + i, log_to_rate[i]); 3260 } 3261 3262 for (i = 0; i < 128; i++) { 3263 unsigned int tmp; 3264 3265 tmp = rate_to_log[(i << 2) + 0] << 0; 3266 tmp |= rate_to_log[(i << 2) + 1] << 8; 3267 tmp |= rate_to_log[(i << 2) + 2] << 16; 3268 tmp |= rate_to_log[(i << 2) + 3] << 24; 3269 write_sram(card, card->rt_base + 256 + i, tmp); 3270 } 3271 3272#if 0 /* Fill RDF and AIR tables. */ 3273 for (i = 0; i < 128; i++) { 3274 unsigned int tmp; 3275 3276 tmp = RDF[0][(i << 1) + 0] << 16; 3277 tmp |= RDF[0][(i << 1) + 1] << 0; 3278 write_sram(card, card->rt_base + 512 + i, tmp); 3279 } 3280 3281 for (i = 0; i < 128; i++) { 3282 unsigned int tmp; 3283 3284 tmp = AIR[0][(i << 1) + 0] << 16; 3285 tmp |= AIR[0][(i << 1) + 1] << 0; 3286 write_sram(card, card->rt_base + 640 + i, tmp); 3287 } 3288#endif 3289 3290 IPRINTK("%s: initialize rate table ...\n", card->name); 3291 writel(card->rt_base << 2, SAR_REG_RTBL); 3292 3293 /* Initialize TSTs */ 3294 IPRINTK("%s: initialize TST ...\n", card->name); 3295 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3296 3297 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3298 write_sram(card, i, TSTE_OPC_VAR); 3299 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3300 idt77252_sram_write_errors = 1; 3301 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3302 idt77252_sram_write_errors = 0; 3303 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3304 write_sram(card, i, TSTE_OPC_VAR); 3305 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3306 idt77252_sram_write_errors = 1; 3307 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3308 idt77252_sram_write_errors = 0; 3309 3310 card->tst_index = 0; 3311 writel(card->tst[0] << 2, SAR_REG_TSTB); 3312 3313 /* Initialize ABRSTD and Receive FIFO */ 3314 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3315 writel(card->abrst_size | (card->abrst_base << 2), 3316 SAR_REG_ABRSTD); 3317 3318 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3319 writel(card->fifo_size | (card->fifo_base << 2), 3320 SAR_REG_RXFD); 3321 3322 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3323 return 0; 3324} 3325 3326static int __devinit 3327init_card(struct atm_dev *dev) 3328{ 3329 struct idt77252_dev *card = dev->dev_data; 3330 struct pci_dev *pcidev = card->pcidev; 3331 unsigned long tmpl, modl; 3332 unsigned int linkrate, rsvdcr; 3333 unsigned int tst_entries; 3334 struct net_device *tmp; 3335 char tname[10]; 3336 3337 u32 size; 3338 u_char pci_byte; 3339 u32 conf; 3340 int i, k; 3341 3342 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3343 printk("Error: SAR already initialized.\n"); 3344 return -1; 3345 } 3346 3347/*****************************************************************/ 3348/* P C I C O N F I G U R A T I O N */ 3349/*****************************************************************/ 3350 3351 /* Set PCI Retry-Timeout and TRDY timeout */ 3352 IPRINTK("%s: Checking PCI retries.\n", card->name); 3353 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3354 printk("%s: can't read PCI retry timeout.\n", card->name); 3355 deinit_card(card); 3356 return -1; 3357 } 3358 if (pci_byte != 0) { 3359 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3360 card->name, pci_byte); 3361 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3362 printk("%s: can't set PCI retry timeout.\n", 3363 card->name); 3364 deinit_card(card); 3365 return -1; 3366 } 3367 } 3368 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3369 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3370 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3371 deinit_card(card); 3372 return -1; 3373 } 3374 if (pci_byte != 0) { 3375 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3376 card->name, pci_byte); 3377 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3378 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3379 deinit_card(card); 3380 return -1; 3381 } 3382 } 3383 /* Reset Timer register */ 3384 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3385 printk("%s: resetting timer overflow.\n", card->name); 3386 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3387 } 3388 IPRINTK("%s: Request IRQ ... ", card->name); 3389 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3390 card->name, card) != 0) { 3391 printk("%s: can't allocate IRQ.\n", card->name); 3392 deinit_card(card); 3393 return -1; 3394 } 3395 IPRINTK("got %d.\n", pcidev->irq); 3396 3397/*****************************************************************/ 3398/* C H E C K A N D I N I T S R A M */ 3399/*****************************************************************/ 3400 3401 IPRINTK("%s: Initializing SRAM\n", card->name); 3402 3403 /* preset size of connecton table, so that init_sram() knows about it */ 3404 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3405 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3406 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3407#ifndef CONFIG_ATM_IDT77252_SEND_IDLE 3408 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3409#endif 3410 0; 3411 3412 if (card->sramsize == (512 * 1024)) 3413 conf |= SAR_CFG_CNTBL_1k; 3414 else 3415 conf |= SAR_CFG_CNTBL_512; 3416 3417 switch (vpibits) { 3418 case 0: 3419 conf |= SAR_CFG_VPVCS_0; 3420 break; 3421 default: 3422 case 1: 3423 conf |= SAR_CFG_VPVCS_1; 3424 break; 3425 case 2: 3426 conf |= SAR_CFG_VPVCS_2; 3427 break; 3428 case 8: 3429 conf |= SAR_CFG_VPVCS_8; 3430 break; 3431 } 3432 3433 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3434 3435 if (init_sram(card) < 0) 3436 return -1; 3437 3438/********************************************************************/ 3439/* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3440/********************************************************************/ 3441 /* Initialize TSQ */ 3442 if (0 != init_tsq(card)) { 3443 deinit_card(card); 3444 return -1; 3445 } 3446 /* Initialize RSQ */ 3447 if (0 != init_rsq(card)) { 3448 deinit_card(card); 3449 return -1; 3450 } 3451 3452 card->vpibits = vpibits; 3453 if (card->sramsize == (512 * 1024)) { 3454 card->vcibits = 10 - card->vpibits; 3455 } else { 3456 card->vcibits = 9 - card->vpibits; 3457 } 3458 3459 card->vcimask = 0; 3460 for (k = 0, i = 1; k < card->vcibits; k++) { 3461 card->vcimask |= i; 3462 i <<= 1; 3463 } 3464 3465 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3466 writel(0, SAR_REG_VPM); 3467 3468 /* Little Endian Order */ 3469 writel(0, SAR_REG_GP); 3470 3471 /* Initialize RAW Cell Handle Register */ 3472 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3473 &card->raw_cell_paddr); 3474 if (!card->raw_cell_hnd) { 3475 printk("%s: memory allocation failure.\n", card->name); 3476 deinit_card(card); 3477 return -1; 3478 } 3479 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3480 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3481 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3482 card->raw_cell_hnd); 3483 3484 size = sizeof(struct vc_map *) * card->tct_size; 3485 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3486 if (NULL == (card->vcs = vmalloc(size))) { 3487 printk("%s: memory allocation failure.\n", card->name); 3488 deinit_card(card); 3489 return -1; 3490 } 3491 memset(card->vcs, 0, size); 3492 3493 size = sizeof(struct vc_map *) * card->scd_size; 3494 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3495 card->name, size); 3496 if (NULL == (card->scd2vc = vmalloc(size))) { 3497 printk("%s: memory allocation failure.\n", card->name); 3498 deinit_card(card); 3499 return -1; 3500 } 3501 memset(card->scd2vc, 0, size); 3502 3503 size = sizeof(struct tst_info) * (card->tst_size - 2); 3504 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3505 card->name, size); 3506 if (NULL == (card->soft_tst = vmalloc(size))) { 3507 printk("%s: memory allocation failure.\n", card->name); 3508 deinit_card(card); 3509 return -1; 3510 } 3511 for (i = 0; i < card->tst_size - 2; i++) { 3512 card->soft_tst[i].tste = TSTE_OPC_VAR; 3513 card->soft_tst[i].vc = NULL; 3514 } 3515 3516 if (dev->phy == NULL) { 3517 printk("%s: No LT device defined.\n", card->name); 3518 deinit_card(card); 3519 return -1; 3520 } 3521 if (dev->phy->ioctl == NULL) { 3522 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3523 deinit_card(card); 3524 return -1; 3525 } 3526 3527#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3528 /* 3529 * this is a jhs hack to get around special functionality in the 3530 * phy driver for the atecom hardware; the functionality doesn't 3531 * exist in the linux atm suni driver 3532 * 3533 * it isn't the right way to do things, but as the guy from NIST 3534 * said, talking about their measurement of the fine structure 3535 * constant, "it's good enough for government work." 3536 */ 3537 linkrate = 149760000; 3538#endif 3539 3540 card->link_pcr = (linkrate / 8 / 53); 3541 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3542 card->name, linkrate, card->link_pcr); 3543 3544#ifdef CONFIG_ATM_IDT77252_SEND_IDLE 3545 card->utopia_pcr = card->link_pcr; 3546#else 3547 card->utopia_pcr = (160000000 / 8 / 54); 3548#endif 3549 3550 rsvdcr = 0; 3551 if (card->utopia_pcr > card->link_pcr) 3552 rsvdcr = card->utopia_pcr - card->link_pcr; 3553 3554 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3555 modl = tmpl % (unsigned long)card->utopia_pcr; 3556 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3557 if (modl) 3558 tst_entries++; 3559 card->tst_free -= tst_entries; 3560 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3561 3562#ifdef HAVE_EEPROM 3563 idt77252_eeprom_init(card); 3564 printk("%s: EEPROM: %02x:", card->name, 3565 idt77252_eeprom_read_status(card)); 3566 3567 for (i = 0; i < 0x80; i++) { 3568 printk(" %02x", 3569 idt77252_eeprom_read_byte(card, i) 3570 ); 3571 } 3572 printk("\n"); 3573#endif /* HAVE_EEPROM */ 3574 3575 /* 3576 * XXX: <hack> 3577 */ 3578 sprintf(tname, "eth%d", card->index); 3579 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */ 3580 if (tmp) { 3581 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3582 3583 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3584 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3585 card->atmdev->esi[2], card->atmdev->esi[3], 3586 card->atmdev->esi[4], card->atmdev->esi[5]); 3587 } 3588 /* 3589 * XXX: </hack> 3590 */ 3591 3592 /* Set Maximum Deficit Count for now. */ 3593 writel(0xffff, SAR_REG_MDFCT); 3594 3595 set_bit(IDT77252_BIT_INIT, &card->flags); 3596 3597 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3598 return 0; 3599} 3600 3601 3602/*****************************************************************************/ 3603/* */ 3604/* Probing of IDT77252 ABR SAR */ 3605/* */ 3606/*****************************************************************************/ 3607 3608 3609static int __devinit 3610idt77252_preset(struct idt77252_dev *card) 3611{ 3612 u16 pci_command; 3613 3614/*****************************************************************/ 3615/* P C I C O N F I G U R A T I O N */ 3616/*****************************************************************/ 3617 3618 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3619 card->name); 3620 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3621 printk("%s: can't read PCI_COMMAND.\n", card->name); 3622 deinit_card(card); 3623 return -1; 3624 } 3625 if (!(pci_command & PCI_COMMAND_IO)) { 3626 printk("%s: PCI_COMMAND: %04x (???)\n", 3627 card->name, pci_command); 3628 deinit_card(card); 3629 return (-1); 3630 } 3631 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3632 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3633 printk("%s: can't write PCI_COMMAND.\n", card->name); 3634 deinit_card(card); 3635 return -1; 3636 } 3637/*****************************************************************/ 3638/* G E N E R I C R E S E T */ 3639/*****************************************************************/ 3640 3641 /* Software reset */ 3642 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3643 mdelay(1); 3644 writel(0, SAR_REG_CFG); 3645 3646 IPRINTK("%s: Software resetted.\n", card->name); 3647 return 0; 3648} 3649 3650 3651static unsigned long __devinit 3652probe_sram(struct idt77252_dev *card) 3653{ 3654 u32 data, addr; 3655 3656 writel(0, SAR_REG_DR0); 3657 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3658 3659 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3660 writel(0xdeadbeef, SAR_REG_DR0); 3661 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3662 3663 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3664 data = readl(SAR_REG_DR0); 3665 3666 if (data != 0) 3667 break; 3668 } 3669 3670 return addr * sizeof(u32); 3671} 3672 3673static int __devinit 3674idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3675{ 3676 static struct idt77252_dev **last = &idt77252_chain; 3677 static int index = 0; 3678 3679 unsigned long membase, srambase; 3680 struct idt77252_dev *card; 3681 struct atm_dev *dev; 3682 ushort revision = 0; 3683 int i, err; 3684 3685 3686 if ((err = pci_enable_device(pcidev))) { 3687 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3688 return err; 3689 } 3690 3691 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) { 3692 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index); 3693 err = -ENODEV; 3694 goto err_out_disable_pdev; 3695 } 3696 3697 card = kmalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3698 if (!card) { 3699 printk("idt77252-%d: can't allocate private data\n", index); 3700 err = -ENOMEM; 3701 goto err_out_disable_pdev; 3702 } 3703 memset(card, 0, sizeof(struct idt77252_dev)); 3704 3705 card->revision = revision; 3706 card->index = index; 3707 card->pcidev = pcidev; 3708 sprintf(card->name, "idt77252-%d", card->index); 3709 3710 INIT_WORK(&card->tqueue, idt77252_softint, (void *)card); 3711 3712 membase = pci_resource_start(pcidev, 1); 3713 srambase = pci_resource_start(pcidev, 2); 3714 3715 init_MUTEX(&card->mutex); 3716 spin_lock_init(&card->cmd_lock); 3717 spin_lock_init(&card->tst_lock); 3718 3719 init_timer(&card->tst_timer); 3720 card->tst_timer.data = (unsigned long)card; 3721 card->tst_timer.function = tst_timer; 3722 3723 /* Do the I/O remapping... */ 3724 card->membase = ioremap(membase, 1024); 3725 if (!card->membase) { 3726 printk("%s: can't ioremap() membase\n", card->name); 3727 err = -EIO; 3728 goto err_out_free_card; 3729 } 3730 3731 if (idt77252_preset(card)) { 3732 printk("%s: preset failed\n", card->name); 3733 err = -EIO; 3734 goto err_out_iounmap; 3735 } 3736 3737 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3738 if (!dev) { 3739 printk("%s: can't register atm device\n", card->name); 3740 err = -EIO; 3741 goto err_out_iounmap; 3742 } 3743 dev->dev_data = card; 3744 card->atmdev = dev; 3745 3746#ifdef CONFIG_ATM_IDT77252_USE_SUNI 3747 suni_init(dev); 3748 if (!dev->phy) { 3749 printk("%s: can't init SUNI\n", card->name); 3750 err = -EIO; 3751 goto err_out_deinit_card; 3752 } 3753#endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3754 3755 card->sramsize = probe_sram(card); 3756 3757 for (i = 0; i < 4; i++) { 3758 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3759 if (!card->fbq[i]) { 3760 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3761 err = -EIO; 3762 goto err_out_deinit_card; 3763 } 3764 } 3765 3766 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3767 card->name, ((revision > 1) && (revision < 25)) ? 3768 'A' + revision - 1 : '?', membase, srambase, 3769 card->sramsize / 1024); 3770 3771 if (init_card(dev)) { 3772 printk("%s: init_card failed\n", card->name); 3773 err = -EIO; 3774 goto err_out_deinit_card; 3775 } 3776 3777 dev->ci_range.vpi_bits = card->vpibits; 3778 dev->ci_range.vci_bits = card->vcibits; 3779 dev->link_rate = card->link_pcr; 3780 3781 if (dev->phy->start) 3782 dev->phy->start(dev); 3783 3784 if (idt77252_dev_open(card)) { 3785 printk("%s: dev_open failed\n", card->name); 3786 err = -EIO; 3787 goto err_out_stop; 3788 } 3789 3790 *last = card; 3791 last = &card->next; 3792 index++; 3793 3794 return 0; 3795 3796err_out_stop: 3797 if (dev->phy->stop) 3798 dev->phy->stop(dev); 3799 3800err_out_deinit_card: 3801 deinit_card(card); 3802 3803err_out_iounmap: 3804 iounmap(card->membase); 3805 3806err_out_free_card: 3807 kfree(card); 3808 3809err_out_disable_pdev: 3810 pci_disable_device(pcidev); 3811 return err; 3812} 3813 3814static struct pci_device_id idt77252_pci_tbl[] = 3815{ 3816 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3818 { 0, } 3819}; 3820 3821MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3822 3823static struct pci_driver idt77252_driver = { 3824 .name = "idt77252", 3825 .id_table = idt77252_pci_tbl, 3826 .probe = idt77252_init_one, 3827}; 3828 3829static int __init idt77252_init(void) 3830{ 3831 struct sk_buff *skb; 3832 3833 printk("%s: at %p\n", __FUNCTION__, idt77252_init); 3834 3835 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3836 sizeof(struct idt77252_skb_prv)) { 3837 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3838 __FUNCTION__, (unsigned long) sizeof(skb->cb), 3839 (unsigned long) sizeof(struct atm_skb_data) + 3840 sizeof(struct idt77252_skb_prv)); 3841 return -EIO; 3842 } 3843 3844 return pci_register_driver(&idt77252_driver); 3845} 3846 3847static void __exit idt77252_exit(void) 3848{ 3849 struct idt77252_dev *card; 3850 struct atm_dev *dev; 3851 3852 pci_unregister_driver(&idt77252_driver); 3853 3854 while (idt77252_chain) { 3855 card = idt77252_chain; 3856 dev = card->atmdev; 3857 idt77252_chain = card->next; 3858 3859 if (dev->phy->stop) 3860 dev->phy->stop(dev); 3861 deinit_card(card); 3862 pci_disable_device(card->pcidev); 3863 kfree(card); 3864 } 3865 3866 DIPRINTK("idt77252: finished cleanup-module().\n"); 3867} 3868 3869module_init(idt77252_init); 3870module_exit(idt77252_exit); 3871 3872MODULE_LICENSE("GPL"); 3873 3874module_param(vpibits, uint, 0); 3875MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3876#ifdef CONFIG_ATM_IDT77252_DEBUG 3877module_param(debug, ulong, 0644); 3878MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3879#endif 3880 3881MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3882MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3883