11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This file contains defines for the 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Micro Memory MM5415 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * family PCI Memory Module with Battery Backup. 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright Micro Memory INC 2001. All rights reserved. 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Release under the terms of the GNU GENERAL PUBLIC LICENSE version 2. 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * See the file COPYING. 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _DRIVERS_BLOCK_MM_H 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _DRIVERS_BLOCK_MM_H 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define IRQ_TIMEOUT (1 * HZ) 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* CSR register definition */ 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLSTATUS_MAGIC 0x00 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MM_MAGIC_VALUE (unsigned char)0x59 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLSTATUS_BATTERY 0x04 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BATTERY_1_DISABLED 0x01 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BATTERY_1_FAILURE 0x02 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BATTERY_2_DISABLED 0x04 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define BATTERY_2_FAILURE 0x08 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLSTATUS_MEMORY 0x07 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEM_128_MB 0xfe 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEM_256_MB 0xfc 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEM_512_MB 0xf8 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEM_1_GB 0xf0 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEM_2_GB 0xe0 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLCMD_LEDCTRL 0x08 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_REMOVE 2 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_FAULT 4 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_POWER 6 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_FLIP 255 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_OFF 0x00 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_ON 0x01 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_FLASH_3_5 0x02 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_FLASH_7_0 0x03 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_POWER_ON 0x00 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define LED_POWER_OFF 0x01 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define USER_BIT1 0x01 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define USER_BIT2 0x02 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMORY_INITIALIZED USER_BIT1 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLCMD_ERRCTRL 0x0C 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EDC_NONE_DEFAULT 0x00 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EDC_NONE 0x01 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EDC_STORE_READ 0x02 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define EDC_STORE_CORRECT 0x03 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLCMD_ERRCNT 0x0D 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define MEMCTRLCMD_ERRSTATUS 0x0E 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ERROR_DATA_LOG 0x20 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ERROR_ADDR_LOG 0x28 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ERROR_COUNT 0x3D 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ERROR_SYNDROME 0x3E 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define ERROR_CHECK 0x3F 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_PCI_ADDR 0x40 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_LOCAL_ADDR 0x48 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_TRANSFER_SIZE 0x50 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_DESCRIPTOR_ADDR 0x58 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_SEMAPHORE_ADDR 0x60 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_STATUS_CTRL 0x68 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_GO 0x00001 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_TRANSFER_READ 0x00002 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_CHAIN_EN 0x00004 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_SEM_EN 0x00010 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_DMA_COMP_EN 0x00020 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_CHAIN_COMP_EN 0x00040 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_ERR_INT_EN 0x00080 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_PARITY_INT_EN 0x00100 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_ANY_ERR 0x00800 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_MBE_ERR 0x01000 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_PARITY_ERR_REP 0x02000 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_PARITY_ERR_DET 0x04000 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_SYSTEM_ERR_SIG 0x08000 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_TARGET_ABT 0x10000 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_MASTER_ABT 0x20000 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_DMA_COMPLETE 0x40000 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_CHAIN_COMPLETE 0x80000 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 904e953a216265f8646360fa909bdc87ea4bf446b3Jeff Garzik/* 914e953a216265f8646360fa909bdc87ea4bf446b3Jeff Garzik3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE 924e953a216265f8646360fa909bdc87ea4bf446b3Jeff GarzikREAD-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA 934e953a216265f8646360fa909bdc87ea4bf446b3Jeff GarzikTRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE 944e953a216265f8646360fa909bdc87ea4bf446b3Jeff GarzikTO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS 954e953a216265f8646360fa909bdc87ea4bf446b3Jeff Garzik(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, 964e953a216265f8646360fa909bdc87ea4bf446b3Jeff GarzikAN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsDMA READ OPERATIONS. 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*/ 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_READ 0x60000000 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_READLINE 0xE0000000 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_READMULTI 0xC0000000 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define WINDOWMAP_WINNUM 0x7B 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_READ_FROM_HOST 0 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DMA_WRITE_TO_HOST 1 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct mm_dma_desc { 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le64 pci_addr; 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le64 local_addr; 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le32 transfer_size; 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 zero1; 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le64 next_desc_addr; 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le64 sem_addr; 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le32 control_bits; 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 zero2; 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dma_addr_t data_dma_handle; 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Copy of the bits */ 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds __le64 sem_control_bits; 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} __attribute__((aligned(8))); 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* bits for card->flags */ 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define UM_FLAG_DMA_IN_REGS 1 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define UM_FLAG_NO_BYTE_STATUS 2 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define UM_FLAG_NO_BATTREG 4 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define UM_FLAG_NO_BATT 8 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 134