clk-nomadik.c revision 6e2b07a172b6ed98c7cdc301333b2d9f86c11880
14a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij#include <linux/clk.h>
24a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij#include <linux/clkdev.h>
34a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij#include <linux/err.h>
44a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij#include <linux/io.h>
54a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij#include <linux/clk-provider.h>
66e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleij#include <linux/of.h>
74a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij
84a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij/*
94a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij * The Nomadik clock tree is described in the STN8815A12 DB V4.2
104a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij * reference manual for the chip, page 94 ff.
114a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij */
124a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij
136e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleijstatic const __initconst struct of_device_id cpu8815_clk_match[] = {
146e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleij	{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
156e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleij	{ /* sentinel */ }
166e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleij};
176e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleij
184a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleijvoid __init nomadik_clk_init(void)
194a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij{
204a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	struct clk *clk;
214a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij
224a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
234a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	clk_register_clkdev(clk, "apb_pclk", NULL);
244a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij
254a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	/*
264a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	 * The 2.4 MHz TIMCLK reference clock is active at boot time, this is
274a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	 * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
284a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	 * by the timers and watchdog. See page 105 ff.
294a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	 */
304a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
314a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij				      2400000);
324a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	clk_register_clkdev(clk, NULL, "mtu0");
334a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij	clk_register_clkdev(clk, NULL, "mtu1");
344a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij
356e2b07a172b6ed98c7cdc301333b2d9f86c11880Linus Walleij	of_clk_init(cpu8815_clk_match);
364a31bd28e86ac50eb620f6b5b36464c45b5fa38fLinus Walleij}
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