1b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/* 2b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * PLL clock driver for Keystone devices 3b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * 4b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * Copyright (C) 2013 Texas Instruments Inc. 5b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * Murali Karicheri <m-karicheri2@ti.com> 6b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * Santosh Shilimkar <santosh.shilimkar@ti.com> 7b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * 8b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * This program is free software; you can redistribute it and/or modify 9b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * it under the terms of the GNU General Public License as published by 10b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * the Free Software Foundation; either version 2 of the License, or 11b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * (at your option) any later version. 12b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 13b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/clk.h> 14b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/clk-provider.h> 15b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/err.h> 16b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/io.h> 17b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/slab.h> 18b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/of_address.h> 19b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/of.h> 20b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#include <linux/module.h> 21b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 22b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#define PLLM_LOW_MASK 0x3f 23b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#define PLLM_HIGH_MASK 0x7ffc0 24b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#define MAIN_PLLM_HIGH_MASK 0x7f000 25b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#define PLLM_HIGH_SHIFT 6 26b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#define PLLD_MASK 0x3f 27dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri#define CLKOD_MASK 0x780000 28dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri#define CLKOD_SHIFT 19 29b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 30b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 31b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * struct clk_pll_data - pll data structure 32b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm 33b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * register of pll controller, else it is in the pll_ctrl0((bit 11-6) 34b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @phy_pllm: Physical address of PLLM in pll controller. Used when 35b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * has_pllctrl is non zero. 36b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of 37b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL 38b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * or PA PLL available on keystone2. These PLLs are controlled by 39b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * this register. Main PLL is controlled by a PLL controller. 40b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pllm: PLL register map address 41b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pll_ctl0: PLL controller map address 42b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pllm_lower_mask: multiplier lower mask 43b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pllm_upper_mask: multiplier upper mask 44b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pllm_upper_shift: multiplier upper shift 45b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @plld_mask: divider mask 46dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri * @clkod_mask: output divider mask 47dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri * @clkod_shift: output divider shift 48dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri * @plld_mask: divider mask 49dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri * @postdiv: Fixed post divider 50b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 51b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstruct clk_pll_data { 52b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar bool has_pllctrl; 53b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 phy_pllm; 54b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 phy_pll_ctl0; 55b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar void __iomem *pllm; 56b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar void __iomem *pll_ctl0; 57b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 pllm_lower_mask; 58b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 pllm_upper_mask; 59b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 pllm_upper_shift; 60b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 plld_mask; 61dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri u32 clkod_mask; 62dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri u32 clkod_shift; 63b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 postdiv; 64b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar}; 65b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 66b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 67b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * struct clk_pll - Main pll clock 68b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @hw: clk_hw for the pll 69b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pll_data: PLL driver specific data 70b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 71b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstruct clk_pll { 72b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_hw hw; 73b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_pll_data *pll_data; 74b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar}; 75b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 76b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) 77b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 78b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic unsigned long clk_pllclk_recalc(struct clk_hw *hw, 79b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar unsigned long parent_rate) 80b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 81b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_pll *pll = to_clk_pll(hw); 82b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_pll_data *pll_data = pll->pll_data; 83b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar unsigned long rate = parent_rate; 84b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 mult = 0, prediv, postdiv, val; 85b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 86b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar /* 87b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * get bits 0-5 of multiplier from pllctrl PLLM register 88b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * if has_pllctrl is non zero 89b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 90b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (pll_data->has_pllctrl) { 91b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar val = readl(pll_data->pllm); 92b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar mult = (val & pll_data->pllm_lower_mask); 93b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 94b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 95b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar /* bit6-12 of PLLM is in Main PLL control register */ 96b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar val = readl(pll_data->pll_ctl0); 97b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar mult |= ((val & pll_data->pllm_upper_mask) 98b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar >> pll_data->pllm_upper_shift); 99b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar prediv = (val & pll_data->plld_mask); 100dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri 101dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri if (!pll_data->has_pllctrl) 102dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri /* read post divider from od bits*/ 103dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri postdiv = ((val & pll_data->clkod_mask) >> 104dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri pll_data->clkod_shift) + 1; 105dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri else 106dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri postdiv = pll_data->postdiv; 107b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 108b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar rate /= (prediv + 1); 109b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar rate = (rate * (mult + 1)); 110b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar rate /= postdiv; 111b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 112b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return rate; 113b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 114b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 115b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic const struct clk_ops clk_pll_ops = { 116b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar .recalc_rate = clk_pllclk_recalc, 117b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar}; 118b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 119b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic struct clk *clk_register_pll(struct device *dev, 120b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *name, 121b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *parent_name, 122b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_pll_data *pll_data) 123b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 124b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_init_data init; 125b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_pll *pll; 126b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk *clk; 127b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 128b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll = kzalloc(sizeof(*pll), GFP_KERNEL); 129b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!pll) 130b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return ERR_PTR(-ENOMEM); 131b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 132b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar init.name = name; 133b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar init.ops = &clk_pll_ops; 134b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar init.flags = 0; 135b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar init.parent_names = (parent_name ? &parent_name : NULL); 136b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar init.num_parents = (parent_name ? 1 : 0); 137b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 138b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll->pll_data = pll_data; 139b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll->hw.init = &init; 140b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 141b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar clk = clk_register(NULL, &pll->hw); 142b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (IS_ERR(clk)) 143b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar goto out; 144b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 145b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return clk; 146b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarout: 147b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar kfree(pll); 148b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return NULL; 149b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 150b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 151b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 152b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * _of_clk_init - PLL initialisation via DT 153b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @node: device tree node for this clock 154b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of 155b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * pll controller, else it is in the control regsiter0(bit 11-6) 156b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 157b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) 158b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 159b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk_pll_data *pll_data; 160b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *parent_name; 161b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk *clk; 162b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar int i; 163b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 164b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL); 165b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!pll_data) { 166b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: Out of memory\n", __func__); 167b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 168b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 169b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 170b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar parent_name = of_clk_get_parent_name(node, 0); 171dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { 172dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri /* assume the PLL has output divider register bits */ 173dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri pll_data->clkod_mask = CLKOD_MASK; 174dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri pll_data->clkod_shift = CLKOD_SHIFT; 175dbb4e67fe7088f963007453ee07e453c4e1fab28Murali Karicheri } 176b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 177b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar i = of_property_match_string(node, "reg-names", "control"); 178b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->pll_ctl0 = of_iomap(node, i); 179b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!pll_data->pll_ctl0) { 180b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: ioremap failed\n", __func__); 181b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar goto out; 182b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 183b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 184b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->pllm_lower_mask = PLLM_LOW_MASK; 185b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->pllm_upper_shift = PLLM_HIGH_SHIFT; 186b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->plld_mask = PLLD_MASK; 187b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->has_pllctrl = pllctrl; 188b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!pll_data->has_pllctrl) { 189b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->pllm_upper_mask = PLLM_HIGH_MASK; 190b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } else { 191b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->pllm_upper_mask = MAIN_PLLM_HIGH_MASK; 192b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar i = of_property_match_string(node, "reg-names", "multiplier"); 193b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pll_data->pllm = of_iomap(node, i); 194b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!pll_data->pllm) { 195b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar iounmap(pll_data->pll_ctl0); 196b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar goto out; 197b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 198b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 199b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 200b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar clk = clk_register_pll(NULL, node->name, parent_name, pll_data); 201b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (clk) { 202b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_clk_add_provider(node, of_clk_src_simple_get, clk); 203b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 204b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 205b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 206b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarout: 207b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: error initializing pll %s\n", __func__, node->name); 208b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar kfree(pll_data); 209b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 210b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 211b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 212b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * of_keystone_pll_clk_init - PLL initialisation DT wrapper 213b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @node: device tree node for this clock 214b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 215b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic void __init of_keystone_pll_clk_init(struct device_node *node) 216b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 217b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar _of_pll_clk_init(node, false); 218b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 219b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh ShilimkarCLK_OF_DECLARE(keystone_pll_clock, "ti,keystone,pll-clock", 220b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_keystone_pll_clk_init); 221b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 222b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 223b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * of_keystone_pll_main_clk_init - Main PLL initialisation DT wrapper 224b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @node: device tree node for this clock 225b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 226b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic void __init of_keystone_main_pll_clk_init(struct device_node *node) 227b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 228b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar _of_pll_clk_init(node, true); 229b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 230b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh ShilimkarCLK_OF_DECLARE(keystone_main_pll_clock, "ti,keystone,main-pll-clock", 231b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_keystone_main_pll_clk_init); 232b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 233b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 234b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * of_pll_div_clk_init - PLL divider setup function 235b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @node: device tree node for this clock 236b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 237b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic void __init of_pll_div_clk_init(struct device_node *node) 238b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 239b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *parent_name; 240b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar void __iomem *reg; 241b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 shift, mask; 242b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk *clk; 243b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *clk_name = node->name; 244b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 245b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_property_read_string(node, "clock-output-names", &clk_name); 246b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar reg = of_iomap(node, 0); 247b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!reg) { 248b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: ioremap failed\n", __func__); 249b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 250b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 251b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 252b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar parent_name = of_clk_get_parent_name(node, 0); 253b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!parent_name) { 254b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: missing parent clock\n", __func__); 255b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 256b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 257b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 258b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (of_property_read_u32(node, "bit-shift", &shift)) { 259b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: missing 'shift' property\n", __func__); 260b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 261b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 262b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 263b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (of_property_read_u32(node, "bit-mask", &mask)) { 264b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: missing 'bit-mask' property\n", __func__); 265b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 266b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 267b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 268b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, 269b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar mask, 0, NULL); 270b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (clk) 271b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_clk_add_provider(node, of_clk_src_simple_get, clk); 272b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar else 273b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: error registering divider %s\n", __func__, clk_name); 274b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 275b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh ShilimkarCLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); 276b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 277b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar/** 278b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * of_pll_mux_clk_init - PLL mux setup function 279b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar * @node: device tree node for this clock 280b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar */ 281b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkarstatic void __init of_pll_mux_clk_init(struct device_node *node) 282b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar{ 283b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar void __iomem *reg; 284b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar u32 shift, mask; 285b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar struct clk *clk; 286b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *parents[2]; 287b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar const char *clk_name = node->name; 288b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 289b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_property_read_string(node, "clock-output-names", &clk_name); 290b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar reg = of_iomap(node, 0); 291b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!reg) { 292b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: ioremap failed\n", __func__); 293b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 294b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 295b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 296b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar parents[0] = of_clk_get_parent_name(node, 0); 297b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar parents[1] = of_clk_get_parent_name(node, 1); 298b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (!parents[0] || !parents[1]) { 299b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: missing parent clocks\n", __func__); 300b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 301b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 302b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 303b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (of_property_read_u32(node, "bit-shift", &shift)) { 304b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: missing 'shift' property\n", __func__); 305b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 306b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 307b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 308b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (of_property_read_u32(node, "bit-mask", &mask)) { 309b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: missing 'bit-mask' property\n", __func__); 310b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar return; 311b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar } 312b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 313b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar clk = clk_register_mux(NULL, clk_name, (const char **)&parents, 314b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar ARRAY_SIZE(parents) , 0, reg, shift, mask, 315b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar 0, NULL); 316b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar if (clk) 317b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar of_clk_add_provider(node, of_clk_src_simple_get, clk); 318b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar else 319b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar pr_err("%s: error registering mux %s\n", __func__, clk_name); 320b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh Shilimkar} 321b9e0d40c0d83805bc6feb86d602e73f2cdcb17f9Santosh ShilimkarCLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); 322