123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo/* 223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * Copyright 2012 Freescale Semiconductor, Inc. 323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * 423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * The code contained herein is licensed under the GNU General Public 523b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * License. You may obtain a copy of the GNU General Public License 623b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * Version 2 or later at the following locations: 723b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * 823b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * http://www.opensource.org/licenses/gpl-license.html 923b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo * http://www.gnu.org/copyleft/gpl.html 1023b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo */ 1123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 1223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#ifndef __MXS_CLK_H 1323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#define __MXS_CLK_H 1423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 1523b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#include <linux/clk.h> 1623b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#include <linux/clk-provider.h> 1723b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#include <linux/spinlock.h> 1823b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 1923b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#define SET 0x4 2023b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#define CLR 0x8 2123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 2223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guoextern spinlock_t mxs_lock; 2323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 2423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guoint mxs_clk_wait(void __iomem *reg, u8 shift); 2523b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 2623b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostruct clk *mxs_clk_pll(const char *name, const char *parent_name, 2723b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo void __iomem *base, u8 power, unsigned long rate); 2823b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 2923b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostruct clk *mxs_clk_ref(const char *name, const char *parent_name, 3023b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo void __iomem *reg, u8 idx); 3123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 3223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostruct clk *mxs_clk_div(const char *name, const char *parent_name, 3323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo void __iomem *reg, u8 shift, u8 width, u8 busy); 3423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 3523b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostruct clk *mxs_clk_frac(const char *name, const char *parent_name, 3623b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo void __iomem *reg, u8 shift, u8 width, u8 busy); 3723b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 3823b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostatic inline struct clk *mxs_clk_fixed(const char *name, int rate) 3923b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo{ 4023b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); 4123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo} 4223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 4323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostatic inline struct clk *mxs_clk_gate(const char *name, 4423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo const char *parent_name, void __iomem *reg, u8 shift) 4523b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo{ 4623b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT, 4723b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo reg, shift, CLK_GATE_SET_TO_DISABLE, 4823b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo &mxs_lock); 4923b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo} 5023b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 5123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostatic inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, 5223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo u8 shift, u8 width, const char **parent_names, int num_parents) 5323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo{ 5423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo return clk_register_mux(NULL, name, parent_names, num_parents, 55819c1de344c5b8350bffd35be9a0fa74541292d3James Hogan CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 56819c1de344c5b8350bffd35be9a0fa74541292d3James Hogan reg, shift, width, 0, &mxs_lock); 5723b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo} 5823b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 5923b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guostatic inline struct clk *mxs_clk_fixed_factor(const char *name, 6023b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo const char *parent_name, unsigned int mult, unsigned int div) 6123b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo{ 6223b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo return clk_register_fixed_factor(NULL, name, parent_name, 6323b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo CLK_SET_RATE_PARENT, mult, div); 6423b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo} 6523b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo 6623b5e15a2994fb0c1444f92b76f09a482f32843cShawn Guo#endif /* __MXS_CLK_H */ 67