clk-pll.c revision aa6fefde62401a84154161a8026872874a70e4c1
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/slab.h> 18#include <linux/io.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/clk-provider.h> 22#include <linux/clk.h> 23 24#include "clk.h" 25 26#define PLL_BASE_BYPASS BIT(31) 27#define PLL_BASE_ENABLE BIT(30) 28#define PLL_BASE_REF_ENABLE BIT(29) 29#define PLL_BASE_OVERRIDE BIT(28) 30 31#define PLL_BASE_DIVP_SHIFT 20 32#define PLL_BASE_DIVP_WIDTH 3 33#define PLL_BASE_DIVN_SHIFT 8 34#define PLL_BASE_DIVN_WIDTH 10 35#define PLL_BASE_DIVM_SHIFT 0 36#define PLL_BASE_DIVM_WIDTH 5 37#define PLLU_POST_DIVP_MASK 0x1 38 39#define PLL_MISC_DCCON_SHIFT 20 40#define PLL_MISC_CPCON_SHIFT 8 41#define PLL_MISC_CPCON_WIDTH 4 42#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1) 43#define PLL_MISC_LFCON_SHIFT 4 44#define PLL_MISC_LFCON_WIDTH 4 45#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1) 46#define PLL_MISC_VCOCON_SHIFT 0 47#define PLL_MISC_VCOCON_WIDTH 4 48#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1) 49 50#define OUT_OF_TABLE_CPCON 8 51 52#define PMC_PLLP_WB0_OVERRIDE 0xf8 53#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) 54#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) 55 56#define PLL_POST_LOCK_DELAY 50 57 58#define PLLDU_LFCON_SET_DIVN 600 59 60#define PLLE_BASE_DIVCML_SHIFT 24 61#define PLLE_BASE_DIVCML_WIDTH 4 62#define PLLE_BASE_DIVP_SHIFT 16 63#define PLLE_BASE_DIVP_WIDTH 7 64#define PLLE_BASE_DIVN_SHIFT 8 65#define PLLE_BASE_DIVN_WIDTH 8 66#define PLLE_BASE_DIVM_SHIFT 0 67#define PLLE_BASE_DIVM_WIDTH 8 68 69#define PLLE_MISC_SETUP_BASE_SHIFT 16 70#define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT) 71#define PLLE_MISC_LOCK_ENABLE BIT(9) 72#define PLLE_MISC_READY BIT(15) 73#define PLLE_MISC_SETUP_EX_SHIFT 2 74#define PLLE_MISC_SETUP_EX_MASK (3 << PLLE_MISC_SETUP_EX_SHIFT) 75#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | \ 76 PLLE_MISC_SETUP_EX_MASK) 77#define PLLE_MISC_SETUP_VALUE (7 << PLLE_MISC_SETUP_BASE_SHIFT) 78 79#define PLLE_SS_CTRL 0x68 80#define PLLE_SS_DISABLE (7 << 10) 81 82#define PLLE_AUX_PLLP_SEL BIT(2) 83#define PLLE_AUX_ENABLE_SWCTL BIT(4) 84#define PLLE_AUX_SEQ_ENABLE BIT(24) 85#define PLLE_AUX_PLLRE_SEL BIT(28) 86 87#define PLLE_MISC_PLLE_PTS BIT(8) 88#define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 89#define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 90#define PLLE_MISC_VREG_BG_CTRL_SHIFT 4 91#define PLLE_MISC_VREG_BG_CTRL_MASK (3 << PLLE_MISC_VREG_BG_CTRL_SHIFT) 92#define PLLE_MISC_VREG_CTRL_SHIFT 2 93#define PLLE_MISC_VREG_CTRL_MASK (2 << PLLE_MISC_VREG_CTRL_SHIFT) 94 95#define PLLCX_MISC_STROBE BIT(31) 96#define PLLCX_MISC_RESET BIT(30) 97#define PLLCX_MISC_SDM_DIV_SHIFT 28 98#define PLLCX_MISC_SDM_DIV_MASK (0x3 << PLLCX_MISC_SDM_DIV_SHIFT) 99#define PLLCX_MISC_FILT_DIV_SHIFT 26 100#define PLLCX_MISC_FILT_DIV_MASK (0x3 << PLLCX_MISC_FILT_DIV_SHIFT) 101#define PLLCX_MISC_ALPHA_SHIFT 18 102#define PLLCX_MISC_DIV_LOW_RANGE \ 103 ((0x1 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 104 (0x1 << PLLCX_MISC_FILT_DIV_SHIFT)) 105#define PLLCX_MISC_DIV_HIGH_RANGE \ 106 ((0x2 << PLLCX_MISC_SDM_DIV_SHIFT) | \ 107 (0x2 << PLLCX_MISC_FILT_DIV_SHIFT)) 108#define PLLCX_MISC_COEF_LOW_RANGE \ 109 ((0x14 << PLLCX_MISC_KA_SHIFT) | (0x38 << PLLCX_MISC_KB_SHIFT)) 110#define PLLCX_MISC_KA_SHIFT 2 111#define PLLCX_MISC_KB_SHIFT 9 112#define PLLCX_MISC_DEFAULT (PLLCX_MISC_COEF_LOW_RANGE | \ 113 (0x19 << PLLCX_MISC_ALPHA_SHIFT) | \ 114 PLLCX_MISC_DIV_LOW_RANGE | \ 115 PLLCX_MISC_RESET) 116#define PLLCX_MISC1_DEFAULT 0x000d2308 117#define PLLCX_MISC2_DEFAULT 0x30211200 118#define PLLCX_MISC3_DEFAULT 0x200 119 120#define PMC_PLLM_WB0_OVERRIDE 0x1dc 121#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 122#define PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK BIT(27) 123 124#define PMC_SATA_PWRGT 0x1ac 125#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE BIT(5) 126#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL BIT(4) 127 128#define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) 129#define pll_readl_base(p) pll_readl(p->params->base_reg, p) 130#define pll_readl_misc(p) pll_readl(p->params->misc_reg, p) 131 132#define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset) 133#define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p) 134#define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p) 135 136#define mask(w) ((1 << (w)) - 1) 137#define divm_mask(p) mask(p->params->div_nmp->divm_width) 138#define divn_mask(p) mask(p->params->div_nmp->divn_width) 139#define divp_mask(p) (p->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK : \ 140 mask(p->params->div_nmp->divp_width)) 141 142#define divm_max(p) (divm_mask(p)) 143#define divn_max(p) (divn_mask(p)) 144#define divp_max(p) (1 << (divp_mask(p))) 145 146static struct div_nmp default_nmp = { 147 .divn_shift = PLL_BASE_DIVN_SHIFT, 148 .divn_width = PLL_BASE_DIVN_WIDTH, 149 .divm_shift = PLL_BASE_DIVM_SHIFT, 150 .divm_width = PLL_BASE_DIVM_WIDTH, 151 .divp_shift = PLL_BASE_DIVP_SHIFT, 152 .divp_width = PLL_BASE_DIVP_WIDTH, 153}; 154 155static void clk_pll_enable_lock(struct tegra_clk_pll *pll) 156{ 157 u32 val; 158 159 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) 160 return; 161 162 if (!(pll->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) 163 return; 164 165 val = pll_readl_misc(pll); 166 val |= BIT(pll->params->lock_enable_bit_idx); 167 pll_writel_misc(val, pll); 168} 169 170static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) 171{ 172 int i; 173 u32 val, lock_mask; 174 void __iomem *lock_addr; 175 176 if (!(pll->flags & TEGRA_PLL_USE_LOCK)) { 177 udelay(pll->params->lock_delay); 178 return 0; 179 } 180 181 lock_addr = pll->clk_base; 182 if (pll->flags & TEGRA_PLL_LOCK_MISC) 183 lock_addr += pll->params->misc_reg; 184 else 185 lock_addr += pll->params->base_reg; 186 187 lock_mask = pll->params->lock_mask; 188 189 for (i = 0; i < pll->params->lock_delay; i++) { 190 val = readl_relaxed(lock_addr); 191 if ((val & lock_mask) == lock_mask) { 192 udelay(PLL_POST_LOCK_DELAY); 193 return 0; 194 } 195 udelay(2); /* timeout = 2 * lock time */ 196 } 197 198 pr_err("%s: Timed out waiting for pll %s lock\n", __func__, 199 __clk_get_name(pll->hw.clk)); 200 201 return -1; 202} 203 204static int clk_pll_is_enabled(struct clk_hw *hw) 205{ 206 struct tegra_clk_pll *pll = to_clk_pll(hw); 207 u32 val; 208 209 if (pll->flags & TEGRA_PLLM) { 210 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 211 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) 212 return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0; 213 } 214 215 val = pll_readl_base(pll); 216 217 return val & PLL_BASE_ENABLE ? 1 : 0; 218} 219 220static void _clk_pll_enable(struct clk_hw *hw) 221{ 222 struct tegra_clk_pll *pll = to_clk_pll(hw); 223 u32 val; 224 225 clk_pll_enable_lock(pll); 226 227 val = pll_readl_base(pll); 228 if (pll->flags & TEGRA_PLL_BYPASS) 229 val &= ~PLL_BASE_BYPASS; 230 val |= PLL_BASE_ENABLE; 231 pll_writel_base(val, pll); 232 233 if (pll->flags & TEGRA_PLLM) { 234 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 235 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 236 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 237 } 238} 239 240static void _clk_pll_disable(struct clk_hw *hw) 241{ 242 struct tegra_clk_pll *pll = to_clk_pll(hw); 243 u32 val; 244 245 val = pll_readl_base(pll); 246 if (pll->flags & TEGRA_PLL_BYPASS) 247 val &= ~PLL_BASE_BYPASS; 248 val &= ~PLL_BASE_ENABLE; 249 pll_writel_base(val, pll); 250 251 if (pll->flags & TEGRA_PLLM) { 252 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); 253 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; 254 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); 255 } 256} 257 258static int clk_pll_enable(struct clk_hw *hw) 259{ 260 struct tegra_clk_pll *pll = to_clk_pll(hw); 261 unsigned long flags = 0; 262 int ret; 263 264 if (pll->lock) 265 spin_lock_irqsave(pll->lock, flags); 266 267 _clk_pll_enable(hw); 268 269 ret = clk_pll_wait_for_lock(pll); 270 271 if (pll->lock) 272 spin_unlock_irqrestore(pll->lock, flags); 273 274 return ret; 275} 276 277static void clk_pll_disable(struct clk_hw *hw) 278{ 279 struct tegra_clk_pll *pll = to_clk_pll(hw); 280 unsigned long flags = 0; 281 282 if (pll->lock) 283 spin_lock_irqsave(pll->lock, flags); 284 285 _clk_pll_disable(hw); 286 287 if (pll->lock) 288 spin_unlock_irqrestore(pll->lock, flags); 289} 290 291static int _p_div_to_hw(struct clk_hw *hw, u8 p_div) 292{ 293 struct tegra_clk_pll *pll = to_clk_pll(hw); 294 struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 295 296 if (p_tohw) { 297 while (p_tohw->pdiv) { 298 if (p_div <= p_tohw->pdiv) 299 return p_tohw->hw_val; 300 p_tohw++; 301 } 302 return -EINVAL; 303 } 304 return -EINVAL; 305} 306 307static int _hw_to_p_div(struct clk_hw *hw, u8 p_div_hw) 308{ 309 struct tegra_clk_pll *pll = to_clk_pll(hw); 310 struct pdiv_map *p_tohw = pll->params->pdiv_tohw; 311 312 if (p_tohw) { 313 while (p_tohw->pdiv) { 314 if (p_div_hw == p_tohw->hw_val) 315 return p_tohw->pdiv; 316 p_tohw++; 317 } 318 return -EINVAL; 319 } 320 321 return 1 << p_div_hw; 322} 323 324static int _get_table_rate(struct clk_hw *hw, 325 struct tegra_clk_pll_freq_table *cfg, 326 unsigned long rate, unsigned long parent_rate) 327{ 328 struct tegra_clk_pll *pll = to_clk_pll(hw); 329 struct tegra_clk_pll_freq_table *sel; 330 331 for (sel = pll->freq_table; sel->input_rate != 0; sel++) 332 if (sel->input_rate == parent_rate && 333 sel->output_rate == rate) 334 break; 335 336 if (sel->input_rate == 0) 337 return -EINVAL; 338 339 cfg->input_rate = sel->input_rate; 340 cfg->output_rate = sel->output_rate; 341 cfg->m = sel->m; 342 cfg->n = sel->n; 343 cfg->p = sel->p; 344 cfg->cpcon = sel->cpcon; 345 346 return 0; 347} 348 349static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 350 unsigned long rate, unsigned long parent_rate) 351{ 352 struct tegra_clk_pll *pll = to_clk_pll(hw); 353 unsigned long cfreq; 354 u32 p_div = 0; 355 int ret; 356 357 switch (parent_rate) { 358 case 12000000: 359 case 26000000: 360 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; 361 break; 362 case 13000000: 363 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; 364 break; 365 case 16800000: 366 case 19200000: 367 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; 368 break; 369 case 9600000: 370 case 28800000: 371 /* 372 * PLL_P_OUT1 rate is not listed in PLLA table 373 */ 374 cfreq = parent_rate/(parent_rate/1000000); 375 break; 376 default: 377 pr_err("%s Unexpected reference rate %lu\n", 378 __func__, parent_rate); 379 BUG(); 380 } 381 382 /* Raise VCO to guarantee 0.5% accuracy */ 383 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; 384 cfg->output_rate <<= 1) 385 p_div++; 386 387 cfg->m = parent_rate / cfreq; 388 cfg->n = cfg->output_rate / cfreq; 389 cfg->cpcon = OUT_OF_TABLE_CPCON; 390 391 if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) || 392 (1 << p_div) > divp_max(pll) 393 || cfg->output_rate > pll->params->vco_max) { 394 pr_err("%s: Failed to set %s rate %lu\n", 395 __func__, __clk_get_name(hw->clk), rate); 396 WARN_ON(1); 397 return -EINVAL; 398 } 399 400 if (pll->params->pdiv_tohw) { 401 ret = _p_div_to_hw(hw, 1 << p_div); 402 if (ret < 0) 403 return ret; 404 else 405 cfg->p = ret; 406 } else 407 cfg->p = p_div; 408 409 return 0; 410} 411 412static void _update_pll_mnp(struct tegra_clk_pll *pll, 413 struct tegra_clk_pll_freq_table *cfg) 414{ 415 u32 val; 416 417 val = pll_readl_base(pll); 418 419 val &= ~((divm_mask(pll) << pll->params->div_nmp->divm_shift) | 420 (divn_mask(pll) << pll->params->div_nmp->divn_shift) | 421 (divp_mask(pll) << pll->params->div_nmp->divp_shift)); 422 val |= ((cfg->m << pll->params->div_nmp->divm_shift) | 423 (cfg->n << pll->params->div_nmp->divn_shift) | 424 (cfg->p << pll->params->div_nmp->divp_shift)); 425 426 pll_writel_base(val, pll); 427} 428 429static void _get_pll_mnp(struct tegra_clk_pll *pll, 430 struct tegra_clk_pll_freq_table *cfg) 431{ 432 u32 val; 433 434 val = pll_readl_base(pll); 435 436 cfg->m = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 437 cfg->n = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 438 cfg->p = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 439} 440 441static void _update_pll_cpcon(struct tegra_clk_pll *pll, 442 struct tegra_clk_pll_freq_table *cfg, 443 unsigned long rate) 444{ 445 u32 val; 446 447 val = pll_readl_misc(pll); 448 449 val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT); 450 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; 451 452 if (pll->flags & TEGRA_PLL_SET_LFCON) { 453 val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT); 454 if (cfg->n >= PLLDU_LFCON_SET_DIVN) 455 val |= 1 << PLL_MISC_LFCON_SHIFT; 456 } else if (pll->flags & TEGRA_PLL_SET_DCCON) { 457 val &= ~(1 << PLL_MISC_DCCON_SHIFT); 458 if (rate >= (pll->params->vco_max >> 1)) 459 val |= 1 << PLL_MISC_DCCON_SHIFT; 460 } 461 462 pll_writel_misc(val, pll); 463} 464 465static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, 466 unsigned long rate) 467{ 468 struct tegra_clk_pll *pll = to_clk_pll(hw); 469 int state, ret = 0; 470 471 state = clk_pll_is_enabled(hw); 472 473 if (state) 474 _clk_pll_disable(hw); 475 476 _update_pll_mnp(pll, cfg); 477 478 if (pll->flags & TEGRA_PLL_HAS_CPCON) 479 _update_pll_cpcon(pll, cfg, rate); 480 481 if (state) { 482 _clk_pll_enable(hw); 483 ret = clk_pll_wait_for_lock(pll); 484 } 485 486 return ret; 487} 488 489static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 490 unsigned long parent_rate) 491{ 492 struct tegra_clk_pll *pll = to_clk_pll(hw); 493 struct tegra_clk_pll_freq_table cfg, old_cfg; 494 unsigned long flags = 0; 495 int ret = 0; 496 497 if (pll->flags & TEGRA_PLL_FIXED) { 498 if (rate != pll->fixed_rate) { 499 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 500 __func__, __clk_get_name(hw->clk), 501 pll->fixed_rate, rate); 502 return -EINVAL; 503 } 504 return 0; 505 } 506 507 if (_get_table_rate(hw, &cfg, rate, parent_rate) && 508 _calc_rate(hw, &cfg, rate, parent_rate)) { 509 WARN_ON(1); 510 return -EINVAL; 511 } 512 if (pll->lock) 513 spin_lock_irqsave(pll->lock, flags); 514 515 _get_pll_mnp(pll, &old_cfg); 516 517 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 518 ret = _program_pll(hw, &cfg, rate); 519 520 if (pll->lock) 521 spin_unlock_irqrestore(pll->lock, flags); 522 523 return ret; 524} 525 526static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 527 unsigned long *prate) 528{ 529 struct tegra_clk_pll *pll = to_clk_pll(hw); 530 struct tegra_clk_pll_freq_table cfg; 531 532 if (pll->flags & TEGRA_PLL_FIXED) 533 return pll->fixed_rate; 534 535 /* PLLM is used for memory; we do not change rate */ 536 if (pll->flags & TEGRA_PLLM) 537 return __clk_get_rate(hw->clk); 538 539 if (_get_table_rate(hw, &cfg, rate, *prate) && 540 _calc_rate(hw, &cfg, rate, *prate)) { 541 WARN_ON(1); 542 return -EINVAL; 543 } 544 545 return cfg.output_rate; 546} 547 548static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, 549 unsigned long parent_rate) 550{ 551 struct tegra_clk_pll *pll = to_clk_pll(hw); 552 struct tegra_clk_pll_freq_table cfg; 553 u32 val; 554 u64 rate = parent_rate; 555 int pdiv; 556 557 val = pll_readl_base(pll); 558 559 if ((pll->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) 560 return parent_rate; 561 562 if ((pll->flags & TEGRA_PLL_FIXED) && !(val & PLL_BASE_OVERRIDE)) { 563 struct tegra_clk_pll_freq_table sel; 564 if (_get_table_rate(hw, &sel, pll->fixed_rate, parent_rate)) { 565 pr_err("Clock %s has unknown fixed frequency\n", 566 __clk_get_name(hw->clk)); 567 BUG(); 568 } 569 return pll->fixed_rate; 570 } 571 572 _get_pll_mnp(pll, &cfg); 573 574 pdiv = _hw_to_p_div(hw, cfg.p); 575 if (pdiv < 0) { 576 WARN_ON(1); 577 pdiv = 1; 578 } 579 580 cfg.m *= pdiv; 581 582 rate *= cfg.n; 583 do_div(rate, cfg.m); 584 585 return rate; 586} 587 588static int clk_plle_training(struct tegra_clk_pll *pll) 589{ 590 u32 val; 591 unsigned long timeout; 592 593 if (!pll->pmc) 594 return -ENOSYS; 595 596 /* 597 * PLLE is already disabled, and setup cleared; 598 * create falling edge on PLLE IDDQ input. 599 */ 600 val = readl(pll->pmc + PMC_SATA_PWRGT); 601 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 602 writel(val, pll->pmc + PMC_SATA_PWRGT); 603 604 val = readl(pll->pmc + PMC_SATA_PWRGT); 605 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; 606 writel(val, pll->pmc + PMC_SATA_PWRGT); 607 608 val = readl(pll->pmc + PMC_SATA_PWRGT); 609 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; 610 writel(val, pll->pmc + PMC_SATA_PWRGT); 611 612 val = pll_readl_misc(pll); 613 614 timeout = jiffies + msecs_to_jiffies(100); 615 while (1) { 616 val = pll_readl_misc(pll); 617 if (val & PLLE_MISC_READY) 618 break; 619 if (time_after(jiffies, timeout)) { 620 pr_err("%s: timeout waiting for PLLE\n", __func__); 621 return -EBUSY; 622 } 623 udelay(300); 624 } 625 626 return 0; 627} 628 629static int clk_plle_enable(struct clk_hw *hw) 630{ 631 struct tegra_clk_pll *pll = to_clk_pll(hw); 632 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 633 struct tegra_clk_pll_freq_table sel; 634 u32 val; 635 int err; 636 637 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) 638 return -EINVAL; 639 640 clk_pll_disable(hw); 641 642 val = pll_readl_misc(pll); 643 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 644 pll_writel_misc(val, pll); 645 646 val = pll_readl_misc(pll); 647 if (!(val & PLLE_MISC_READY)) { 648 err = clk_plle_training(pll); 649 if (err) 650 return err; 651 } 652 653 if (pll->flags & TEGRA_PLLE_CONFIGURE) { 654 /* configure dividers */ 655 val = pll_readl_base(pll); 656 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); 657 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT); 658 val |= sel.m << pll->params->div_nmp->divm_shift; 659 val |= sel.n << pll->params->div_nmp->divn_shift; 660 val |= sel.p << pll->params->div_nmp->divp_shift; 661 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 662 pll_writel_base(val, pll); 663 } 664 665 val = pll_readl_misc(pll); 666 val |= PLLE_MISC_SETUP_VALUE; 667 val |= PLLE_MISC_LOCK_ENABLE; 668 pll_writel_misc(val, pll); 669 670 val = readl(pll->clk_base + PLLE_SS_CTRL); 671 val |= PLLE_SS_DISABLE; 672 writel(val, pll->clk_base + PLLE_SS_CTRL); 673 674 val |= pll_readl_base(pll); 675 val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); 676 pll_writel_base(val, pll); 677 678 clk_pll_wait_for_lock(pll); 679 680 return 0; 681} 682 683static unsigned long clk_plle_recalc_rate(struct clk_hw *hw, 684 unsigned long parent_rate) 685{ 686 struct tegra_clk_pll *pll = to_clk_pll(hw); 687 u32 val = pll_readl_base(pll); 688 u32 divn = 0, divm = 0, divp = 0; 689 u64 rate = parent_rate; 690 691 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); 692 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); 693 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); 694 divm *= divp; 695 696 rate *= divn; 697 do_div(rate, divm); 698 return rate; 699} 700 701const struct clk_ops tegra_clk_pll_ops = { 702 .is_enabled = clk_pll_is_enabled, 703 .enable = clk_pll_enable, 704 .disable = clk_pll_disable, 705 .recalc_rate = clk_pll_recalc_rate, 706 .round_rate = clk_pll_round_rate, 707 .set_rate = clk_pll_set_rate, 708}; 709 710const struct clk_ops tegra_clk_plle_ops = { 711 .recalc_rate = clk_plle_recalc_rate, 712 .is_enabled = clk_pll_is_enabled, 713 .disable = clk_pll_disable, 714 .enable = clk_plle_enable, 715}; 716 717#ifdef CONFIG_ARCH_TEGRA_114_SOC 718 719static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, 720 unsigned long parent_rate) 721{ 722 if (parent_rate > pll_params->cf_max) 723 return 2; 724 else 725 return 1; 726} 727 728static int clk_pll_iddq_enable(struct clk_hw *hw) 729{ 730 struct tegra_clk_pll *pll = to_clk_pll(hw); 731 unsigned long flags = 0; 732 733 u32 val; 734 int ret; 735 736 if (pll->lock) 737 spin_lock_irqsave(pll->lock, flags); 738 739 val = pll_readl(pll->params->iddq_reg, pll); 740 val &= ~BIT(pll->params->iddq_bit_idx); 741 pll_writel(val, pll->params->iddq_reg, pll); 742 udelay(2); 743 744 _clk_pll_enable(hw); 745 746 ret = clk_pll_wait_for_lock(pll); 747 748 if (pll->lock) 749 spin_unlock_irqrestore(pll->lock, flags); 750 751 return 0; 752} 753 754static void clk_pll_iddq_disable(struct clk_hw *hw) 755{ 756 struct tegra_clk_pll *pll = to_clk_pll(hw); 757 unsigned long flags = 0; 758 u32 val; 759 760 if (pll->lock) 761 spin_lock_irqsave(pll->lock, flags); 762 763 _clk_pll_disable(hw); 764 765 val = pll_readl(pll->params->iddq_reg, pll); 766 val |= BIT(pll->params->iddq_bit_idx); 767 pll_writel(val, pll->params->iddq_reg, pll); 768 udelay(2); 769 770 if (pll->lock) 771 spin_unlock_irqrestore(pll->lock, flags); 772} 773 774static int _calc_dynamic_ramp_rate(struct clk_hw *hw, 775 struct tegra_clk_pll_freq_table *cfg, 776 unsigned long rate, unsigned long parent_rate) 777{ 778 struct tegra_clk_pll *pll = to_clk_pll(hw); 779 unsigned int p; 780 int p_div; 781 782 if (!rate) 783 return -EINVAL; 784 785 p = DIV_ROUND_UP(pll->params->vco_min, rate); 786 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); 787 cfg->output_rate = rate * p; 788 cfg->n = cfg->output_rate * cfg->m / parent_rate; 789 790 p_div = _p_div_to_hw(hw, p); 791 if (p_div < 0) 792 return p_div; 793 else 794 cfg->p = p_div; 795 796 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) 797 return -EINVAL; 798 799 return 0; 800} 801 802static int _pll_ramp_calc_pll(struct clk_hw *hw, 803 struct tegra_clk_pll_freq_table *cfg, 804 unsigned long rate, unsigned long parent_rate) 805{ 806 struct tegra_clk_pll *pll = to_clk_pll(hw); 807 int err = 0, p_div; 808 809 err = _get_table_rate(hw, cfg, rate, parent_rate); 810 if (err < 0) 811 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate); 812 else { 813 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { 814 WARN_ON(1); 815 err = -EINVAL; 816 goto out; 817 } 818 p_div = _p_div_to_hw(hw, cfg->p); 819 if (p_div < 0) 820 return p_div; 821 else 822 cfg->p = p_div; 823 } 824 825 if (cfg->p > pll->params->max_p) 826 err = -EINVAL; 827 828out: 829 return err; 830} 831 832static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, 833 unsigned long parent_rate) 834{ 835 struct tegra_clk_pll *pll = to_clk_pll(hw); 836 struct tegra_clk_pll_freq_table cfg, old_cfg; 837 unsigned long flags = 0; 838 int ret = 0; 839 840 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 841 if (ret < 0) 842 return ret; 843 844 if (pll->lock) 845 spin_lock_irqsave(pll->lock, flags); 846 847 _get_pll_mnp(pll, &old_cfg); 848 849 if (old_cfg.m != cfg.m || old_cfg.n != cfg.n || old_cfg.p != cfg.p) 850 ret = _program_pll(hw, &cfg, rate); 851 852 if (pll->lock) 853 spin_unlock_irqrestore(pll->lock, flags); 854 855 return ret; 856} 857 858static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, 859 unsigned long *prate) 860{ 861 struct tegra_clk_pll_freq_table cfg; 862 int ret = 0, p_div; 863 u64 output_rate = *prate; 864 865 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate); 866 if (ret < 0) 867 return ret; 868 869 p_div = _hw_to_p_div(hw, cfg.p); 870 if (p_div < 0) 871 return p_div; 872 873 output_rate *= cfg.n; 874 do_div(output_rate, cfg.m * p_div); 875 876 return output_rate; 877} 878 879static int clk_pllm_set_rate(struct clk_hw *hw, unsigned long rate, 880 unsigned long parent_rate) 881{ 882 struct tegra_clk_pll_freq_table cfg; 883 struct tegra_clk_pll *pll = to_clk_pll(hw); 884 unsigned long flags = 0; 885 int state, ret = 0; 886 u32 val; 887 888 if (pll->lock) 889 spin_lock_irqsave(pll->lock, flags); 890 891 state = clk_pll_is_enabled(hw); 892 if (state) { 893 if (rate != clk_get_rate(hw->clk)) { 894 pr_err("%s: Cannot change active PLLM\n", __func__); 895 ret = -EINVAL; 896 goto out; 897 } 898 goto out; 899 } 900 901 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 902 if (ret < 0) 903 goto out; 904 905 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE); 906 if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) { 907 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE_2); 908 val = cfg.p ? (val | PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK) : 909 (val & ~PMC_PLLM_WB0_OVERRIDE_2_DIVP_MASK); 910 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE_2); 911 912 val = readl_relaxed(pll->pmc + PMC_PLLM_WB0_OVERRIDE); 913 val &= ~(divn_mask(pll) | divm_mask(pll)); 914 val |= (cfg.m << pll->params->div_nmp->divm_shift) | 915 (cfg.n << pll->params->div_nmp->divn_shift); 916 writel_relaxed(val, pll->pmc + PMC_PLLM_WB0_OVERRIDE); 917 } else 918 _update_pll_mnp(pll, &cfg); 919 920 921out: 922 if (pll->lock) 923 spin_unlock_irqrestore(pll->lock, flags); 924 925 return ret; 926} 927 928static void _pllcx_strobe(struct tegra_clk_pll *pll) 929{ 930 u32 val; 931 932 val = pll_readl_misc(pll); 933 val |= PLLCX_MISC_STROBE; 934 pll_writel_misc(val, pll); 935 udelay(2); 936 937 val &= ~PLLCX_MISC_STROBE; 938 pll_writel_misc(val, pll); 939} 940 941static int clk_pllc_enable(struct clk_hw *hw) 942{ 943 struct tegra_clk_pll *pll = to_clk_pll(hw); 944 u32 val; 945 int ret = 0; 946 unsigned long flags = 0; 947 948 if (pll->lock) 949 spin_lock_irqsave(pll->lock, flags); 950 951 _clk_pll_enable(hw); 952 udelay(2); 953 954 val = pll_readl_misc(pll); 955 val &= ~PLLCX_MISC_RESET; 956 pll_writel_misc(val, pll); 957 udelay(2); 958 959 _pllcx_strobe(pll); 960 961 ret = clk_pll_wait_for_lock(pll); 962 963 if (pll->lock) 964 spin_unlock_irqrestore(pll->lock, flags); 965 966 return ret; 967} 968 969static void _clk_pllc_disable(struct clk_hw *hw) 970{ 971 struct tegra_clk_pll *pll = to_clk_pll(hw); 972 u32 val; 973 974 _clk_pll_disable(hw); 975 976 val = pll_readl_misc(pll); 977 val |= PLLCX_MISC_RESET; 978 pll_writel_misc(val, pll); 979 udelay(2); 980} 981 982static void clk_pllc_disable(struct clk_hw *hw) 983{ 984 struct tegra_clk_pll *pll = to_clk_pll(hw); 985 unsigned long flags = 0; 986 987 if (pll->lock) 988 spin_lock_irqsave(pll->lock, flags); 989 990 _clk_pllc_disable(hw); 991 992 if (pll->lock) 993 spin_unlock_irqrestore(pll->lock, flags); 994} 995 996static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll, 997 unsigned long input_rate, u32 n) 998{ 999 u32 val, n_threshold; 1000 1001 switch (input_rate) { 1002 case 12000000: 1003 n_threshold = 70; 1004 break; 1005 case 13000000: 1006 case 26000000: 1007 n_threshold = 71; 1008 break; 1009 case 16800000: 1010 n_threshold = 55; 1011 break; 1012 case 19200000: 1013 n_threshold = 48; 1014 break; 1015 default: 1016 pr_err("%s: Unexpected reference rate %lu\n", 1017 __func__, input_rate); 1018 return -EINVAL; 1019 } 1020 1021 val = pll_readl_misc(pll); 1022 val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK); 1023 val |= n <= n_threshold ? 1024 PLLCX_MISC_DIV_LOW_RANGE : PLLCX_MISC_DIV_HIGH_RANGE; 1025 pll_writel_misc(val, pll); 1026 1027 return 0; 1028} 1029 1030static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, 1031 unsigned long parent_rate) 1032{ 1033 struct tegra_clk_pll_freq_table cfg, old_cfg; 1034 struct tegra_clk_pll *pll = to_clk_pll(hw); 1035 unsigned long flags = 0; 1036 int state, ret = 0; 1037 1038 if (pll->lock) 1039 spin_lock_irqsave(pll->lock, flags); 1040 1041 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate); 1042 if (ret < 0) 1043 goto out; 1044 1045 _get_pll_mnp(pll, &old_cfg); 1046 1047 if (cfg.m != old_cfg.m) { 1048 WARN_ON(1); 1049 goto out; 1050 } 1051 1052 if (old_cfg.n == cfg.n && old_cfg.p == cfg.p) 1053 goto out; 1054 1055 state = clk_pll_is_enabled(hw); 1056 if (state) 1057 _clk_pllc_disable(hw); 1058 1059 ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1060 if (ret < 0) 1061 goto out; 1062 1063 _update_pll_mnp(pll, &cfg); 1064 1065 if (state) 1066 ret = clk_pllc_enable(hw); 1067 1068out: 1069 if (pll->lock) 1070 spin_unlock_irqrestore(pll->lock, flags); 1071 1072 return ret; 1073} 1074 1075static long _pllre_calc_rate(struct tegra_clk_pll *pll, 1076 struct tegra_clk_pll_freq_table *cfg, 1077 unsigned long rate, unsigned long parent_rate) 1078{ 1079 u16 m, n; 1080 u64 output_rate = parent_rate; 1081 1082 m = _pll_fixed_mdiv(pll->params, parent_rate); 1083 n = rate * m / parent_rate; 1084 1085 output_rate *= n; 1086 do_div(output_rate, m); 1087 1088 if (cfg) { 1089 cfg->m = m; 1090 cfg->n = n; 1091 } 1092 1093 return output_rate; 1094} 1095static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, 1096 unsigned long parent_rate) 1097{ 1098 struct tegra_clk_pll_freq_table cfg, old_cfg; 1099 struct tegra_clk_pll *pll = to_clk_pll(hw); 1100 unsigned long flags = 0; 1101 int state, ret = 0; 1102 1103 if (pll->lock) 1104 spin_lock_irqsave(pll->lock, flags); 1105 1106 _pllre_calc_rate(pll, &cfg, rate, parent_rate); 1107 _get_pll_mnp(pll, &old_cfg); 1108 cfg.p = old_cfg.p; 1109 1110 if (cfg.m != old_cfg.m || cfg.n != old_cfg.n) { 1111 state = clk_pll_is_enabled(hw); 1112 if (state) 1113 _clk_pll_disable(hw); 1114 1115 _update_pll_mnp(pll, &cfg); 1116 1117 if (state) { 1118 _clk_pll_enable(hw); 1119 ret = clk_pll_wait_for_lock(pll); 1120 } 1121 } 1122 1123 if (pll->lock) 1124 spin_unlock_irqrestore(pll->lock, flags); 1125 1126 return ret; 1127} 1128 1129static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw, 1130 unsigned long parent_rate) 1131{ 1132 struct tegra_clk_pll_freq_table cfg; 1133 struct tegra_clk_pll *pll = to_clk_pll(hw); 1134 u64 rate = parent_rate; 1135 1136 _get_pll_mnp(pll, &cfg); 1137 1138 rate *= cfg.n; 1139 do_div(rate, cfg.m); 1140 1141 return rate; 1142} 1143 1144static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, 1145 unsigned long *prate) 1146{ 1147 struct tegra_clk_pll *pll = to_clk_pll(hw); 1148 1149 return _pllre_calc_rate(pll, NULL, rate, *prate); 1150} 1151 1152static int clk_plle_tegra114_enable(struct clk_hw *hw) 1153{ 1154 struct tegra_clk_pll *pll = to_clk_pll(hw); 1155 struct tegra_clk_pll_freq_table sel; 1156 u32 val; 1157 int ret; 1158 unsigned long flags = 0; 1159 unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); 1160 1161 if (_get_table_rate(hw, &sel, pll->fixed_rate, input_rate)) 1162 return -EINVAL; 1163 1164 if (pll->lock) 1165 spin_lock_irqsave(pll->lock, flags); 1166 1167 val = pll_readl_base(pll); 1168 val &= ~BIT(29); /* Disable lock override */ 1169 pll_writel_base(val, pll); 1170 1171 val = pll_readl(pll->params->aux_reg, pll); 1172 val |= PLLE_AUX_ENABLE_SWCTL; 1173 val &= ~PLLE_AUX_SEQ_ENABLE; 1174 pll_writel(val, pll->params->aux_reg, pll); 1175 udelay(1); 1176 1177 val = pll_readl_misc(pll); 1178 val |= PLLE_MISC_LOCK_ENABLE; 1179 val |= PLLE_MISC_IDDQ_SW_CTRL; 1180 val &= ~PLLE_MISC_IDDQ_SW_VALUE; 1181 val |= PLLE_MISC_PLLE_PTS; 1182 val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; 1183 pll_writel_misc(val, pll); 1184 udelay(5); 1185 1186 val = pll_readl(PLLE_SS_CTRL, pll); 1187 val |= PLLE_SS_DISABLE; 1188 pll_writel(val, PLLE_SS_CTRL, pll); 1189 1190 val = pll_readl_base(pll); 1191 val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); 1192 val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT); 1193 val |= sel.m << pll->params->div_nmp->divm_shift; 1194 val |= sel.n << pll->params->div_nmp->divn_shift; 1195 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; 1196 pll_writel_base(val, pll); 1197 udelay(1); 1198 1199 _clk_pll_enable(hw); 1200 ret = clk_pll_wait_for_lock(pll); 1201 1202 if (ret < 0) 1203 goto out; 1204 1205 /* TODO: enable hw control of xusb brick pll */ 1206 1207out: 1208 if (pll->lock) 1209 spin_unlock_irqrestore(pll->lock, flags); 1210 1211 return ret; 1212} 1213 1214static void clk_plle_tegra114_disable(struct clk_hw *hw) 1215{ 1216 struct tegra_clk_pll *pll = to_clk_pll(hw); 1217 unsigned long flags = 0; 1218 u32 val; 1219 1220 if (pll->lock) 1221 spin_lock_irqsave(pll->lock, flags); 1222 1223 _clk_pll_disable(hw); 1224 1225 val = pll_readl_misc(pll); 1226 val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE; 1227 pll_writel_misc(val, pll); 1228 udelay(1); 1229 1230 if (pll->lock) 1231 spin_unlock_irqrestore(pll->lock, flags); 1232} 1233#endif 1234 1235static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base, 1236 void __iomem *pmc, unsigned long fixed_rate, 1237 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1238 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1239{ 1240 struct tegra_clk_pll *pll; 1241 1242 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1243 if (!pll) 1244 return ERR_PTR(-ENOMEM); 1245 1246 pll->clk_base = clk_base; 1247 pll->pmc = pmc; 1248 1249 pll->freq_table = freq_table; 1250 pll->params = pll_params; 1251 pll->fixed_rate = fixed_rate; 1252 pll->flags = pll_flags; 1253 pll->lock = lock; 1254 1255 if (!pll_params->div_nmp) 1256 pll_params->div_nmp = &default_nmp; 1257 1258 return pll; 1259} 1260 1261static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, 1262 const char *name, const char *parent_name, unsigned long flags, 1263 const struct clk_ops *ops) 1264{ 1265 struct clk_init_data init; 1266 1267 init.name = name; 1268 init.ops = ops; 1269 init.flags = flags; 1270 init.parent_names = (parent_name ? &parent_name : NULL); 1271 init.num_parents = (parent_name ? 1 : 0); 1272 1273 /* Data in .init is copied by clk_register(), so stack variable OK */ 1274 pll->hw.init = &init; 1275 1276 return clk_register(NULL, &pll->hw); 1277} 1278 1279struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 1280 void __iomem *clk_base, void __iomem *pmc, 1281 unsigned long flags, unsigned long fixed_rate, 1282 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1283 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1284{ 1285 struct tegra_clk_pll *pll; 1286 struct clk *clk; 1287 1288 pll_flags |= TEGRA_PLL_BYPASS; 1289 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1290 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1291 freq_table, lock); 1292 if (IS_ERR(pll)) 1293 return ERR_CAST(pll); 1294 1295 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1296 &tegra_clk_pll_ops); 1297 if (IS_ERR(clk)) 1298 kfree(pll); 1299 1300 return clk; 1301} 1302 1303struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 1304 void __iomem *clk_base, void __iomem *pmc, 1305 unsigned long flags, unsigned long fixed_rate, 1306 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 1307 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock) 1308{ 1309 struct tegra_clk_pll *pll; 1310 struct clk *clk; 1311 1312 pll_flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; 1313 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1314 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1315 freq_table, lock); 1316 if (IS_ERR(pll)) 1317 return ERR_CAST(pll); 1318 1319 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1320 &tegra_clk_plle_ops); 1321 if (IS_ERR(clk)) 1322 kfree(pll); 1323 1324 return clk; 1325} 1326 1327#ifdef CONFIG_ARCH_TEGRA_114_SOC 1328const struct clk_ops tegra_clk_pllxc_ops = { 1329 .is_enabled = clk_pll_is_enabled, 1330 .enable = clk_pll_iddq_enable, 1331 .disable = clk_pll_iddq_disable, 1332 .recalc_rate = clk_pll_recalc_rate, 1333 .round_rate = clk_pll_ramp_round_rate, 1334 .set_rate = clk_pllxc_set_rate, 1335}; 1336 1337const struct clk_ops tegra_clk_pllm_ops = { 1338 .is_enabled = clk_pll_is_enabled, 1339 .enable = clk_pll_iddq_enable, 1340 .disable = clk_pll_iddq_disable, 1341 .recalc_rate = clk_pll_recalc_rate, 1342 .round_rate = clk_pll_ramp_round_rate, 1343 .set_rate = clk_pllm_set_rate, 1344}; 1345 1346const struct clk_ops tegra_clk_pllc_ops = { 1347 .is_enabled = clk_pll_is_enabled, 1348 .enable = clk_pllc_enable, 1349 .disable = clk_pllc_disable, 1350 .recalc_rate = clk_pll_recalc_rate, 1351 .round_rate = clk_pll_ramp_round_rate, 1352 .set_rate = clk_pllc_set_rate, 1353}; 1354 1355const struct clk_ops tegra_clk_pllre_ops = { 1356 .is_enabled = clk_pll_is_enabled, 1357 .enable = clk_pll_iddq_enable, 1358 .disable = clk_pll_iddq_disable, 1359 .recalc_rate = clk_pllre_recalc_rate, 1360 .round_rate = clk_pllre_round_rate, 1361 .set_rate = clk_pllre_set_rate, 1362}; 1363 1364const struct clk_ops tegra_clk_plle_tegra114_ops = { 1365 .is_enabled = clk_pll_is_enabled, 1366 .enable = clk_plle_tegra114_enable, 1367 .disable = clk_plle_tegra114_disable, 1368 .recalc_rate = clk_pll_recalc_rate, 1369}; 1370 1371 1372struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 1373 void __iomem *clk_base, void __iomem *pmc, 1374 unsigned long flags, unsigned long fixed_rate, 1375 struct tegra_clk_pll_params *pll_params, 1376 u32 pll_flags, 1377 struct tegra_clk_pll_freq_table *freq_table, 1378 spinlock_t *lock) 1379{ 1380 struct tegra_clk_pll *pll; 1381 struct clk *clk; 1382 1383 if (!pll_params->pdiv_tohw) 1384 return ERR_PTR(-EINVAL); 1385 1386 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1387 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1388 freq_table, lock); 1389 if (IS_ERR(pll)) 1390 return ERR_CAST(pll); 1391 1392 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1393 &tegra_clk_pllxc_ops); 1394 if (IS_ERR(clk)) 1395 kfree(pll); 1396 1397 return clk; 1398} 1399 1400struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 1401 void __iomem *clk_base, void __iomem *pmc, 1402 unsigned long flags, unsigned long fixed_rate, 1403 struct tegra_clk_pll_params *pll_params, 1404 u32 pll_flags, 1405 struct tegra_clk_pll_freq_table *freq_table, 1406 spinlock_t *lock, unsigned long parent_rate) 1407{ 1408 u32 val; 1409 struct tegra_clk_pll *pll; 1410 struct clk *clk; 1411 1412 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1413 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1414 freq_table, lock); 1415 if (IS_ERR(pll)) 1416 return ERR_CAST(pll); 1417 1418 /* program minimum rate by default */ 1419 1420 val = pll_readl_base(pll); 1421 if (val & PLL_BASE_ENABLE) 1422 WARN_ON(val & pll_params->iddq_bit_idx); 1423 else { 1424 int m; 1425 1426 m = _pll_fixed_mdiv(pll_params, parent_rate); 1427 val = m << PLL_BASE_DIVM_SHIFT; 1428 val |= (pll_params->vco_min / parent_rate) 1429 << PLL_BASE_DIVN_SHIFT; 1430 pll_writel_base(val, pll); 1431 } 1432 1433 /* disable lock override */ 1434 1435 val = pll_readl_misc(pll); 1436 val &= ~BIT(29); 1437 pll_writel_misc(val, pll); 1438 1439 pll_flags |= TEGRA_PLL_LOCK_MISC; 1440 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1441 &tegra_clk_pllre_ops); 1442 if (IS_ERR(clk)) 1443 kfree(pll); 1444 1445 return clk; 1446} 1447 1448struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 1449 void __iomem *clk_base, void __iomem *pmc, 1450 unsigned long flags, unsigned long fixed_rate, 1451 struct tegra_clk_pll_params *pll_params, 1452 u32 pll_flags, 1453 struct tegra_clk_pll_freq_table *freq_table, 1454 spinlock_t *lock) 1455{ 1456 struct tegra_clk_pll *pll; 1457 struct clk *clk; 1458 1459 if (!pll_params->pdiv_tohw) 1460 return ERR_PTR(-EINVAL); 1461 1462 pll_flags |= TEGRA_PLL_BYPASS; 1463 pll_flags |= TEGRA_PLL_HAS_LOCK_ENABLE; 1464 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1465 freq_table, lock); 1466 if (IS_ERR(pll)) 1467 return ERR_CAST(pll); 1468 1469 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1470 &tegra_clk_pllm_ops); 1471 if (IS_ERR(clk)) 1472 kfree(pll); 1473 1474 return clk; 1475} 1476 1477struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, 1478 void __iomem *clk_base, void __iomem *pmc, 1479 unsigned long flags, unsigned long fixed_rate, 1480 struct tegra_clk_pll_params *pll_params, 1481 u32 pll_flags, 1482 struct tegra_clk_pll_freq_table *freq_table, 1483 spinlock_t *lock) 1484{ 1485 struct clk *parent, *clk; 1486 struct pdiv_map *p_tohw = pll_params->pdiv_tohw; 1487 struct tegra_clk_pll *pll; 1488 struct tegra_clk_pll_freq_table cfg; 1489 unsigned long parent_rate; 1490 1491 if (!p_tohw) 1492 return ERR_PTR(-EINVAL); 1493 1494 parent = __clk_lookup(parent_name); 1495 if (IS_ERR(parent)) { 1496 WARN(1, "parent clk %s of %s must be registered first\n", 1497 name, parent_name); 1498 return ERR_PTR(-EINVAL); 1499 } 1500 1501 pll_flags |= TEGRA_PLL_BYPASS; 1502 pll = _tegra_init_pll(clk_base, pmc, fixed_rate, pll_params, pll_flags, 1503 freq_table, lock); 1504 if (IS_ERR(pll)) 1505 return ERR_CAST(pll); 1506 1507 parent_rate = __clk_get_rate(parent); 1508 1509 /* 1510 * Most of PLLC register fields are shadowed, and can not be read 1511 * directly from PLL h/w. Hence, actual PLLC boot state is unknown. 1512 * Initialize PLL to default state: disabled, reset; shadow registers 1513 * loaded with default parameters; dividers are preset for half of 1514 * minimum VCO rate (the latter assured that shadowed divider settings 1515 * are within supported range). 1516 */ 1517 1518 cfg.m = _pll_fixed_mdiv(pll_params, parent_rate); 1519 cfg.n = cfg.m * pll_params->vco_min / parent_rate; 1520 1521 while (p_tohw->pdiv) { 1522 if (p_tohw->pdiv == 2) { 1523 cfg.p = p_tohw->hw_val; 1524 break; 1525 } 1526 p_tohw++; 1527 } 1528 1529 if (!p_tohw->pdiv) { 1530 WARN_ON(1); 1531 return ERR_PTR(-EINVAL); 1532 } 1533 1534 pll_writel_base(0, pll); 1535 _update_pll_mnp(pll, &cfg); 1536 1537 pll_writel_misc(PLLCX_MISC_DEFAULT, pll); 1538 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); 1539 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); 1540 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); 1541 1542 _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n); 1543 1544 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1545 &tegra_clk_pllc_ops); 1546 if (IS_ERR(clk)) 1547 kfree(pll); 1548 1549 return clk; 1550} 1551 1552struct clk *tegra_clk_register_plle_tegra114(const char *name, 1553 const char *parent_name, 1554 void __iomem *clk_base, unsigned long flags, 1555 unsigned long fixed_rate, 1556 struct tegra_clk_pll_params *pll_params, 1557 struct tegra_clk_pll_freq_table *freq_table, 1558 spinlock_t *lock) 1559{ 1560 struct tegra_clk_pll *pll; 1561 struct clk *clk; 1562 u32 val, val_aux; 1563 1564 pll = _tegra_init_pll(clk_base, NULL, fixed_rate, pll_params, 1565 TEGRA_PLL_HAS_LOCK_ENABLE, freq_table, lock); 1566 if (IS_ERR(pll)) 1567 return ERR_CAST(pll); 1568 1569 /* ensure parent is set to pll_re_vco */ 1570 1571 val = pll_readl_base(pll); 1572 val_aux = pll_readl(pll_params->aux_reg, pll); 1573 1574 if (val & PLL_BASE_ENABLE) { 1575 if (!(val_aux & PLLE_AUX_PLLRE_SEL)) 1576 WARN(1, "pll_e enabled with unsupported parent %s\n", 1577 (val & PLLE_AUX_PLLP_SEL) ? "pllp_out0" : "pll_ref"); 1578 } else { 1579 val_aux |= PLLE_AUX_PLLRE_SEL; 1580 pll_writel(val, pll_params->aux_reg, pll); 1581 } 1582 1583 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, 1584 &tegra_clk_plle_tegra114_ops); 1585 if (IS_ERR(clk)) 1586 kfree(pll); 1587 1588 return clk; 1589} 1590#endif 1591