clk-tegra114.c revision 88235988d7ff394f77c0a5a8a9803962d0026ef1
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/clk/tegra.h> 25 26#include "clk.h" 27 28#define RST_DEVICES_L 0x004 29#define RST_DEVICES_H 0x008 30#define RST_DEVICES_U 0x00C 31#define RST_DEVICES_V 0x358 32#define RST_DEVICES_W 0x35C 33#define RST_DEVICES_X 0x28C 34#define RST_DEVICES_SET_L 0x300 35#define RST_DEVICES_CLR_L 0x304 36#define RST_DEVICES_SET_H 0x308 37#define RST_DEVICES_CLR_H 0x30c 38#define RST_DEVICES_SET_U 0x310 39#define RST_DEVICES_CLR_U 0x314 40#define RST_DEVICES_SET_V 0x430 41#define RST_DEVICES_CLR_V 0x434 42#define RST_DEVICES_SET_W 0x438 43#define RST_DEVICES_CLR_W 0x43c 44#define RST_DEVICES_NUM 5 45 46#define CLK_OUT_ENB_L 0x010 47#define CLK_OUT_ENB_H 0x014 48#define CLK_OUT_ENB_U 0x018 49#define CLK_OUT_ENB_V 0x360 50#define CLK_OUT_ENB_W 0x364 51#define CLK_OUT_ENB_X 0x280 52#define CLK_OUT_ENB_SET_L 0x320 53#define CLK_OUT_ENB_CLR_L 0x324 54#define CLK_OUT_ENB_SET_H 0x328 55#define CLK_OUT_ENB_CLR_H 0x32c 56#define CLK_OUT_ENB_SET_U 0x330 57#define CLK_OUT_ENB_CLR_U 0x334 58#define CLK_OUT_ENB_SET_V 0x440 59#define CLK_OUT_ENB_CLR_V 0x444 60#define CLK_OUT_ENB_SET_W 0x448 61#define CLK_OUT_ENB_CLR_W 0x44c 62#define CLK_OUT_ENB_SET_X 0x284 63#define CLK_OUT_ENB_CLR_X 0x288 64#define CLK_OUT_ENB_NUM 6 65 66#define PLLC_BASE 0x80 67#define PLLC_MISC2 0x88 68#define PLLC_MISC 0x8c 69#define PLLC2_BASE 0x4e8 70#define PLLC2_MISC 0x4ec 71#define PLLC3_BASE 0x4fc 72#define PLLC3_MISC 0x500 73#define PLLM_BASE 0x90 74#define PLLM_MISC 0x9c 75#define PLLP_BASE 0xa0 76#define PLLP_MISC 0xac 77#define PLLX_BASE 0xe0 78#define PLLX_MISC 0xe4 79#define PLLX_MISC2 0x514 80#define PLLX_MISC3 0x518 81#define PLLD_BASE 0xd0 82#define PLLD_MISC 0xdc 83#define PLLD2_BASE 0x4b8 84#define PLLD2_MISC 0x4bc 85#define PLLE_BASE 0xe8 86#define PLLE_MISC 0xec 87#define PLLA_BASE 0xb0 88#define PLLA_MISC 0xbc 89#define PLLU_BASE 0xc0 90#define PLLU_MISC 0xcc 91#define PLLRE_BASE 0x4c4 92#define PLLRE_MISC 0x4c8 93 94#define PLL_MISC_LOCK_ENABLE 18 95#define PLLC_MISC_LOCK_ENABLE 24 96#define PLLDU_MISC_LOCK_ENABLE 22 97#define PLLE_MISC_LOCK_ENABLE 9 98#define PLLRE_MISC_LOCK_ENABLE 30 99 100#define PLLC_IDDQ_BIT 26 101#define PLLX_IDDQ_BIT 3 102#define PLLRE_IDDQ_BIT 16 103 104#define PLL_BASE_LOCK BIT(27) 105#define PLLE_MISC_LOCK BIT(11) 106#define PLLRE_MISC_LOCK BIT(24) 107#define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 108 109#define PLLE_AUX 0x48c 110#define PLLC_OUT 0x84 111#define PLLM_OUT 0x94 112#define PLLP_OUTA 0xa4 113#define PLLP_OUTB 0xa8 114#define PLLA_OUT 0xb4 115 116#define AUDIO_SYNC_CLK_I2S0 0x4a0 117#define AUDIO_SYNC_CLK_I2S1 0x4a4 118#define AUDIO_SYNC_CLK_I2S2 0x4a8 119#define AUDIO_SYNC_CLK_I2S3 0x4ac 120#define AUDIO_SYNC_CLK_I2S4 0x4b0 121#define AUDIO_SYNC_CLK_SPDIF 0x4b4 122 123#define AUDIO_SYNC_DOUBLER 0x49c 124 125#define PMC_CLK_OUT_CNTRL 0x1a8 126#define PMC_DPD_PADS_ORIDE 0x1c 127#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 128#define PMC_CTRL 0 129#define PMC_CTRL_BLINK_ENB 7 130#define PMC_BLINK_TIMER 0x40 131 132#define OSC_CTRL 0x50 133#define OSC_CTRL_OSC_FREQ_SHIFT 28 134#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 135 136#define PLLXC_SW_MAX_P 6 137 138#define CCLKG_BURST_POLICY 0x368 139#define CCLKLP_BURST_POLICY 0x370 140#define SCLK_BURST_POLICY 0x028 141#define SYSTEM_CLK_RATE 0x030 142 143#define UTMIP_PLL_CFG2 0x488 144#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 145#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 146#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 147#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 148#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 149 150#define UTMIP_PLL_CFG1 0x484 151#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 152#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 153#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 154#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 155#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 156#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 157#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 158 159#define UTMIPLL_HW_PWRDN_CFG0 0x52c 160#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 161#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 162#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 163#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 164#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 165#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 166#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 167#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 168 169#define CLK_SOURCE_I2S0 0x1d8 170#define CLK_SOURCE_I2S1 0x100 171#define CLK_SOURCE_I2S2 0x104 172#define CLK_SOURCE_NDFLASH 0x160 173#define CLK_SOURCE_I2S3 0x3bc 174#define CLK_SOURCE_I2S4 0x3c0 175#define CLK_SOURCE_SPDIF_OUT 0x108 176#define CLK_SOURCE_SPDIF_IN 0x10c 177#define CLK_SOURCE_PWM 0x110 178#define CLK_SOURCE_ADX 0x638 179#define CLK_SOURCE_AMX 0x63c 180#define CLK_SOURCE_HDA 0x428 181#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 182#define CLK_SOURCE_SBC1 0x134 183#define CLK_SOURCE_SBC2 0x118 184#define CLK_SOURCE_SBC3 0x11c 185#define CLK_SOURCE_SBC4 0x1b4 186#define CLK_SOURCE_SBC5 0x3c8 187#define CLK_SOURCE_SBC6 0x3cc 188#define CLK_SOURCE_SATA_OOB 0x420 189#define CLK_SOURCE_SATA 0x424 190#define CLK_SOURCE_NDSPEED 0x3f8 191#define CLK_SOURCE_VFIR 0x168 192#define CLK_SOURCE_SDMMC1 0x150 193#define CLK_SOURCE_SDMMC2 0x154 194#define CLK_SOURCE_SDMMC3 0x1bc 195#define CLK_SOURCE_SDMMC4 0x164 196#define CLK_SOURCE_VDE 0x1c8 197#define CLK_SOURCE_CSITE 0x1d4 198#define CLK_SOURCE_LA 0x1f8 199#define CLK_SOURCE_TRACE 0x634 200#define CLK_SOURCE_OWR 0x1cc 201#define CLK_SOURCE_NOR 0x1d0 202#define CLK_SOURCE_MIPI 0x174 203#define CLK_SOURCE_I2C1 0x124 204#define CLK_SOURCE_I2C2 0x198 205#define CLK_SOURCE_I2C3 0x1b8 206#define CLK_SOURCE_I2C4 0x3c4 207#define CLK_SOURCE_I2C5 0x128 208#define CLK_SOURCE_UARTA 0x178 209#define CLK_SOURCE_UARTB 0x17c 210#define CLK_SOURCE_UARTC 0x1a0 211#define CLK_SOURCE_UARTD 0x1c0 212#define CLK_SOURCE_UARTE 0x1c4 213#define CLK_SOURCE_UARTA_DBG 0x178 214#define CLK_SOURCE_UARTB_DBG 0x17c 215#define CLK_SOURCE_UARTC_DBG 0x1a0 216#define CLK_SOURCE_UARTD_DBG 0x1c0 217#define CLK_SOURCE_UARTE_DBG 0x1c4 218#define CLK_SOURCE_3D 0x158 219#define CLK_SOURCE_2D 0x15c 220#define CLK_SOURCE_VI_SENSOR 0x1a8 221#define CLK_SOURCE_VI 0x148 222#define CLK_SOURCE_EPP 0x16c 223#define CLK_SOURCE_MSENC 0x1f0 224#define CLK_SOURCE_TSEC 0x1f4 225#define CLK_SOURCE_HOST1X 0x180 226#define CLK_SOURCE_HDMI 0x18c 227#define CLK_SOURCE_DISP1 0x138 228#define CLK_SOURCE_DISP2 0x13c 229#define CLK_SOURCE_CILAB 0x614 230#define CLK_SOURCE_CILCD 0x618 231#define CLK_SOURCE_CILE 0x61c 232#define CLK_SOURCE_DSIALP 0x620 233#define CLK_SOURCE_DSIBLP 0x624 234#define CLK_SOURCE_TSENSOR 0x3b8 235#define CLK_SOURCE_D_AUDIO 0x3d0 236#define CLK_SOURCE_DAM0 0x3d8 237#define CLK_SOURCE_DAM1 0x3dc 238#define CLK_SOURCE_DAM2 0x3e0 239#define CLK_SOURCE_ACTMON 0x3e8 240#define CLK_SOURCE_EXTERN1 0x3ec 241#define CLK_SOURCE_EXTERN2 0x3f0 242#define CLK_SOURCE_EXTERN3 0x3f4 243#define CLK_SOURCE_I2CSLOW 0x3fc 244#define CLK_SOURCE_SE 0x42c 245#define CLK_SOURCE_MSELECT 0x3b4 246#define CLK_SOURCE_SOC_THERM 0x644 247#define CLK_SOURCE_XUSB_HOST_SRC 0x600 248#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 249#define CLK_SOURCE_XUSB_FS_SRC 0x608 250#define CLK_SOURCE_XUSB_SS_SRC 0x610 251#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 252#define CLK_SOURCE_EMC 0x19c 253 254static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 255 256static void __iomem *clk_base; 257static void __iomem *pmc_base; 258 259static DEFINE_SPINLOCK(pll_d_lock); 260static DEFINE_SPINLOCK(pll_d2_lock); 261static DEFINE_SPINLOCK(pll_u_lock); 262static DEFINE_SPINLOCK(pll_div_lock); 263static DEFINE_SPINLOCK(pll_re_lock); 264static DEFINE_SPINLOCK(clk_doubler_lock); 265static DEFINE_SPINLOCK(clk_out_lock); 266static DEFINE_SPINLOCK(sysrate_lock); 267 268static struct pdiv_map pllxc_p[] = { 269 { .pdiv = 1, .hw_val = 0 }, 270 { .pdiv = 2, .hw_val = 1 }, 271 { .pdiv = 3, .hw_val = 2 }, 272 { .pdiv = 4, .hw_val = 3 }, 273 { .pdiv = 5, .hw_val = 4 }, 274 { .pdiv = 6, .hw_val = 5 }, 275 { .pdiv = 8, .hw_val = 6 }, 276 { .pdiv = 10, .hw_val = 7 }, 277 { .pdiv = 12, .hw_val = 8 }, 278 { .pdiv = 16, .hw_val = 9 }, 279 { .pdiv = 12, .hw_val = 10 }, 280 { .pdiv = 16, .hw_val = 11 }, 281 { .pdiv = 20, .hw_val = 12 }, 282 { .pdiv = 24, .hw_val = 13 }, 283 { .pdiv = 32, .hw_val = 14 }, 284 { .pdiv = 0, .hw_val = 0 }, 285}; 286 287static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 288 { 12000000, 624000000, 104, 0, 2}, 289 { 12000000, 600000000, 100, 0, 2}, 290 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 291 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 292 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 293 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 294 { 0, 0, 0, 0, 0, 0 }, 295}; 296 297static struct tegra_clk_pll_params pll_c_params = { 298 .input_min = 12000000, 299 .input_max = 800000000, 300 .cf_min = 12000000, 301 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 302 .vco_min = 600000000, 303 .vco_max = 1400000000, 304 .base_reg = PLLC_BASE, 305 .misc_reg = PLLC_MISC, 306 .lock_mask = PLL_BASE_LOCK, 307 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 308 .lock_delay = 300, 309 .iddq_reg = PLLC_MISC, 310 .iddq_bit_idx = PLLC_IDDQ_BIT, 311 .max_p = PLLXC_SW_MAX_P, 312 .dyn_ramp_reg = PLLC_MISC2, 313 .stepa_shift = 17, 314 .stepb_shift = 9, 315 .pdiv_tohw = pllxc_p, 316}; 317 318static struct pdiv_map pllc_p[] = { 319 { .pdiv = 1, .hw_val = 0 }, 320 { .pdiv = 2, .hw_val = 1 }, 321 { .pdiv = 4, .hw_val = 3 }, 322 { .pdiv = 8, .hw_val = 5 }, 323 { .pdiv = 16, .hw_val = 7 }, 324 { .pdiv = 0, .hw_val = 0 }, 325}; 326 327static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 328 {12000000, 600000000, 100, 0, 2}, 329 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 330 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 331 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 332 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 333 {0, 0, 0, 0, 0, 0}, 334}; 335 336static struct tegra_clk_pll_params pll_c2_params = { 337 .input_min = 12000000, 338 .input_max = 48000000, 339 .cf_min = 12000000, 340 .cf_max = 19200000, 341 .vco_min = 600000000, 342 .vco_max = 1200000000, 343 .base_reg = PLLC2_BASE, 344 .misc_reg = PLLC2_MISC, 345 .lock_mask = PLL_BASE_LOCK, 346 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 347 .lock_delay = 300, 348 .pdiv_tohw = pllc_p, 349 .ext_misc_reg[0] = 0x4f0, 350 .ext_misc_reg[1] = 0x4f4, 351 .ext_misc_reg[2] = 0x4f8, 352}; 353 354static struct tegra_clk_pll_params pll_c3_params = { 355 .input_min = 12000000, 356 .input_max = 48000000, 357 .cf_min = 12000000, 358 .cf_max = 19200000, 359 .vco_min = 600000000, 360 .vco_max = 1200000000, 361 .base_reg = PLLC3_BASE, 362 .misc_reg = PLLC3_MISC, 363 .lock_mask = PLL_BASE_LOCK, 364 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 365 .lock_delay = 300, 366 .pdiv_tohw = pllc_p, 367 .ext_misc_reg[0] = 0x504, 368 .ext_misc_reg[1] = 0x508, 369 .ext_misc_reg[2] = 0x50c, 370}; 371 372static struct pdiv_map pllm_p[] = { 373 { .pdiv = 1, .hw_val = 0 }, 374 { .pdiv = 2, .hw_val = 1 }, 375 { .pdiv = 0, .hw_val = 0 }, 376}; 377 378static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 379 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 380 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 381 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 382 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 383 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 384 {0, 0, 0, 0, 0, 0}, 385}; 386 387static struct tegra_clk_pll_params pll_m_params = { 388 .input_min = 12000000, 389 .input_max = 500000000, 390 .cf_min = 12000000, 391 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 392 .vco_min = 400000000, 393 .vco_max = 1066000000, 394 .base_reg = PLLM_BASE, 395 .misc_reg = PLLM_MISC, 396 .lock_mask = PLL_BASE_LOCK, 397 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 398 .lock_delay = 300, 399 .max_p = 2, 400 .pdiv_tohw = pllm_p, 401}; 402 403static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 404 {12000000, 216000000, 432, 12, 1, 8}, 405 {13000000, 216000000, 432, 13, 1, 8}, 406 {16800000, 216000000, 360, 14, 1, 8}, 407 {19200000, 216000000, 360, 16, 1, 8}, 408 {26000000, 216000000, 432, 26, 1, 8}, 409 {0, 0, 0, 0, 0, 0}, 410}; 411 412static struct tegra_clk_pll_params pll_p_params = { 413 .input_min = 2000000, 414 .input_max = 31000000, 415 .cf_min = 1000000, 416 .cf_max = 6000000, 417 .vco_min = 200000000, 418 .vco_max = 700000000, 419 .base_reg = PLLP_BASE, 420 .misc_reg = PLLP_MISC, 421 .lock_mask = PLL_BASE_LOCK, 422 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 423 .lock_delay = 300, 424}; 425 426static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 427 {9600000, 282240000, 147, 5, 0, 4}, 428 {9600000, 368640000, 192, 5, 0, 4}, 429 {9600000, 240000000, 200, 8, 0, 8}, 430 431 {28800000, 282240000, 245, 25, 0, 8}, 432 {28800000, 368640000, 320, 25, 0, 8}, 433 {28800000, 240000000, 200, 24, 0, 8}, 434 {0, 0, 0, 0, 0, 0}, 435}; 436 437 438static struct tegra_clk_pll_params pll_a_params = { 439 .input_min = 2000000, 440 .input_max = 31000000, 441 .cf_min = 1000000, 442 .cf_max = 6000000, 443 .vco_min = 200000000, 444 .vco_max = 700000000, 445 .base_reg = PLLA_BASE, 446 .misc_reg = PLLA_MISC, 447 .lock_mask = PLL_BASE_LOCK, 448 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 449 .lock_delay = 300, 450}; 451 452static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 453 {12000000, 216000000, 864, 12, 2, 12}, 454 {13000000, 216000000, 864, 13, 2, 12}, 455 {16800000, 216000000, 720, 14, 2, 12}, 456 {19200000, 216000000, 720, 16, 2, 12}, 457 {26000000, 216000000, 864, 26, 2, 12}, 458 459 {12000000, 594000000, 594, 12, 0, 12}, 460 {13000000, 594000000, 594, 13, 0, 12}, 461 {16800000, 594000000, 495, 14, 0, 12}, 462 {19200000, 594000000, 495, 16, 0, 12}, 463 {26000000, 594000000, 594, 26, 0, 12}, 464 465 {12000000, 1000000000, 1000, 12, 0, 12}, 466 {13000000, 1000000000, 1000, 13, 0, 12}, 467 {19200000, 1000000000, 625, 12, 0, 12}, 468 {26000000, 1000000000, 1000, 26, 0, 12}, 469 470 {0, 0, 0, 0, 0, 0}, 471}; 472 473static struct tegra_clk_pll_params pll_d_params = { 474 .input_min = 2000000, 475 .input_max = 40000000, 476 .cf_min = 1000000, 477 .cf_max = 6000000, 478 .vco_min = 500000000, 479 .vco_max = 1000000000, 480 .base_reg = PLLD_BASE, 481 .misc_reg = PLLD_MISC, 482 .lock_mask = PLL_BASE_LOCK, 483 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 484 .lock_delay = 1000, 485}; 486 487static struct tegra_clk_pll_params pll_d2_params = { 488 .input_min = 2000000, 489 .input_max = 40000000, 490 .cf_min = 1000000, 491 .cf_max = 6000000, 492 .vco_min = 500000000, 493 .vco_max = 1000000000, 494 .base_reg = PLLD2_BASE, 495 .misc_reg = PLLD2_MISC, 496 .lock_mask = PLL_BASE_LOCK, 497 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 498 .lock_delay = 1000, 499}; 500 501static struct pdiv_map pllu_p[] = { 502 { .pdiv = 1, .hw_val = 1 }, 503 { .pdiv = 2, .hw_val = 0 }, 504 { .pdiv = 0, .hw_val = 0 }, 505}; 506 507static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 508 {12000000, 480000000, 960, 12, 0, 12}, 509 {13000000, 480000000, 960, 13, 0, 12}, 510 {16800000, 480000000, 400, 7, 0, 5}, 511 {19200000, 480000000, 200, 4, 0, 3}, 512 {26000000, 480000000, 960, 26, 0, 12}, 513 {0, 0, 0, 0, 0, 0}, 514}; 515 516static struct tegra_clk_pll_params pll_u_params = { 517 .input_min = 2000000, 518 .input_max = 40000000, 519 .cf_min = 1000000, 520 .cf_max = 6000000, 521 .vco_min = 480000000, 522 .vco_max = 960000000, 523 .base_reg = PLLU_BASE, 524 .misc_reg = PLLU_MISC, 525 .lock_mask = PLL_BASE_LOCK, 526 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 527 .lock_delay = 1000, 528 .pdiv_tohw = pllu_p, 529}; 530 531static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 532 /* 1 GHz */ 533 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 534 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 535 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 536 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 537 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 538 539 {0, 0, 0, 0, 0, 0}, 540}; 541 542static struct tegra_clk_pll_params pll_x_params = { 543 .input_min = 12000000, 544 .input_max = 800000000, 545 .cf_min = 12000000, 546 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 547 .vco_min = 700000000, 548 .vco_max = 2400000000U, 549 .base_reg = PLLX_BASE, 550 .misc_reg = PLLX_MISC, 551 .lock_mask = PLL_BASE_LOCK, 552 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 553 .lock_delay = 300, 554 .iddq_reg = PLLX_MISC3, 555 .iddq_bit_idx = PLLX_IDDQ_BIT, 556 .max_p = PLLXC_SW_MAX_P, 557 .dyn_ramp_reg = PLLX_MISC2, 558 .stepa_shift = 16, 559 .stepb_shift = 24, 560 .pdiv_tohw = pllxc_p, 561}; 562 563static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 564 /* PLLE special case: use cpcon field to store cml divider value */ 565 {336000000, 100000000, 100, 21, 16, 11}, 566 {312000000, 100000000, 200, 26, 24, 13}, 567 {0, 0, 0, 0, 0, 0}, 568}; 569 570static struct tegra_clk_pll_params pll_e_params = { 571 .input_min = 12000000, 572 .input_max = 1000000000, 573 .cf_min = 12000000, 574 .cf_max = 75000000, 575 .vco_min = 1600000000, 576 .vco_max = 2400000000U, 577 .base_reg = PLLE_BASE, 578 .misc_reg = PLLE_MISC, 579 .aux_reg = PLLE_AUX, 580 .lock_mask = PLLE_MISC_LOCK, 581 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 582 .lock_delay = 300, 583}; 584 585static struct tegra_clk_pll_params pll_re_vco_params = { 586 .input_min = 12000000, 587 .input_max = 1000000000, 588 .cf_min = 12000000, 589 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 590 .vco_min = 300000000, 591 .vco_max = 600000000, 592 .base_reg = PLLRE_BASE, 593 .misc_reg = PLLRE_MISC, 594 .lock_mask = PLLRE_MISC_LOCK, 595 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 596 .lock_delay = 300, 597 .iddq_reg = PLLRE_MISC, 598 .iddq_bit_idx = PLLRE_IDDQ_BIT, 599}; 600 601/* Peripheral clock registers */ 602 603static struct tegra_clk_periph_regs periph_l_regs = { 604 .enb_reg = CLK_OUT_ENB_L, 605 .enb_set_reg = CLK_OUT_ENB_SET_L, 606 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 607 .rst_reg = RST_DEVICES_L, 608 .rst_set_reg = RST_DEVICES_SET_L, 609 .rst_clr_reg = RST_DEVICES_CLR_L, 610}; 611 612static struct tegra_clk_periph_regs periph_h_regs = { 613 .enb_reg = CLK_OUT_ENB_H, 614 .enb_set_reg = CLK_OUT_ENB_SET_H, 615 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 616 .rst_reg = RST_DEVICES_H, 617 .rst_set_reg = RST_DEVICES_SET_H, 618 .rst_clr_reg = RST_DEVICES_CLR_H, 619}; 620 621static struct tegra_clk_periph_regs periph_u_regs = { 622 .enb_reg = CLK_OUT_ENB_U, 623 .enb_set_reg = CLK_OUT_ENB_SET_U, 624 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 625 .rst_reg = RST_DEVICES_U, 626 .rst_set_reg = RST_DEVICES_SET_U, 627 .rst_clr_reg = RST_DEVICES_CLR_U, 628}; 629 630static struct tegra_clk_periph_regs periph_v_regs = { 631 .enb_reg = CLK_OUT_ENB_V, 632 .enb_set_reg = CLK_OUT_ENB_SET_V, 633 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 634 .rst_reg = RST_DEVICES_V, 635 .rst_set_reg = RST_DEVICES_SET_V, 636 .rst_clr_reg = RST_DEVICES_CLR_V, 637}; 638 639static struct tegra_clk_periph_regs periph_w_regs = { 640 .enb_reg = CLK_OUT_ENB_W, 641 .enb_set_reg = CLK_OUT_ENB_SET_W, 642 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 643 .rst_reg = RST_DEVICES_W, 644 .rst_set_reg = RST_DEVICES_SET_W, 645 .rst_clr_reg = RST_DEVICES_CLR_W, 646}; 647 648/* possible OSC frequencies in Hz */ 649static unsigned long tegra114_input_freq[] = { 650 [0] = 13000000, 651 [1] = 16800000, 652 [4] = 19200000, 653 [5] = 38400000, 654 [8] = 12000000, 655 [9] = 48000000, 656 [12] = 260000000, 657}; 658 659#define MASK(x) (BIT(x) - 1) 660 661#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 662 _clk_num, _regs, _gate_flags, _clk_id) \ 663 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 664 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 665 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 666 _parents##_idx, 0) 667 668#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 669 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 670 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 671 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 672 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 673 _parents##_idx, flags) 674 675#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 676 _clk_num, _regs, _gate_flags, _clk_id) \ 677 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 678 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \ 679 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 680 _parents##_idx, 0) 681 682#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 683 _clk_num, _regs, _gate_flags, _clk_id) \ 684 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 685 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 686 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 687 _clk_id, _parents##_idx, 0) 688 689#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 690 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 691 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 692 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 693 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 694 _clk_id, _parents##_idx, flags) 695 696#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 697 _clk_num, _regs, _gate_flags, _clk_id) \ 698 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 699 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 700 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 701 _clk_id, _parents##_idx, 0) 702 703#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 704 _clk_num, _regs, _clk_id) \ 705 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 706 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\ 707 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \ 708 _parents##_idx, 0) 709 710#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 711 _clk_num, _regs, _clk_id) \ 712 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 713 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \ 714 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 715 716#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 717 _mux_shift, _mux_mask, _clk_num, _regs, \ 718 _gate_flags, _clk_id) \ 719 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 720 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 721 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 722 _clk_id, _parents##_idx, 0) 723 724#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 725 _clk_num, _regs, _gate_flags, _clk_id) \ 726 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 727 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 728 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 729 _clk_id, _parents##_idx, 0) 730 731#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 732 _regs, _gate_flags, _clk_id) \ 733 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 734 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \ 735 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 736 mux_d_audio_clk_idx, 0) 737 738enum tegra114_clk { 739 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12, 740 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19, 741 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27, 742 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40, 743 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48, 744 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56, 745 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65, 746 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73, 747 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80, 748 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91, 749 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102, 750 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1, 751 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x, 752 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120, 753 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128, 754 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148, 755 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192, 756 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k, 757 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2, 758 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3, 759 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0, 760 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0, 761 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync, 762 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0, 763 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3, 764 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src, 765 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp, 766 767 /* Mux clocks */ 768 769 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux, 770 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux, 771 dsib_mux, clk_max, 772}; 773 774struct utmi_clk_param { 775 /* Oscillator Frequency in KHz */ 776 u32 osc_frequency; 777 /* UTMIP PLL Enable Delay Count */ 778 u8 enable_delay_count; 779 /* UTMIP PLL Stable count */ 780 u8 stable_count; 781 /* UTMIP PLL Active delay count */ 782 u8 active_delay_count; 783 /* UTMIP PLL Xtal frequency count */ 784 u8 xtal_freq_count; 785}; 786 787static const struct utmi_clk_param utmi_parameters[] = { 788 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 789 .stable_count = 0x33, .active_delay_count = 0x05, 790 .xtal_freq_count = 0x7F}, 791 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 792 .stable_count = 0x4B, .active_delay_count = 0x06, 793 .xtal_freq_count = 0xBB}, 794 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 795 .stable_count = 0x2F, .active_delay_count = 0x04, 796 .xtal_freq_count = 0x76}, 797 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 798 .stable_count = 0x66, .active_delay_count = 0x09, 799 .xtal_freq_count = 0xFE}, 800 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 801 .stable_count = 0x41, .active_delay_count = 0x0A, 802 .xtal_freq_count = 0xA4}, 803}; 804 805/* peripheral mux definitions */ 806 807#define MUX_I2S_SPDIF(_id) \ 808static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 809 #_id, "pll_p",\ 810 "clk_m"}; 811MUX_I2S_SPDIF(audio0) 812MUX_I2S_SPDIF(audio1) 813MUX_I2S_SPDIF(audio2) 814MUX_I2S_SPDIF(audio3) 815MUX_I2S_SPDIF(audio4) 816MUX_I2S_SPDIF(audio) 817 818#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 819#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 820#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 821#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 822#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 823#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 824 825static const char *mux_pllp_pllc_pllm_clkm[] = { 826 "pll_p", "pll_c", "pll_m", "clk_m" 827}; 828#define mux_pllp_pllc_pllm_clkm_idx NULL 829 830static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 831#define mux_pllp_pllc_pllm_idx NULL 832 833static const char *mux_pllp_pllc_clk32_clkm[] = { 834 "pll_p", "pll_c", "clk_32k", "clk_m" 835}; 836#define mux_pllp_pllc_clk32_clkm_idx NULL 837 838static const char *mux_plla_pllc_pllp_clkm[] = { 839 "pll_a_out0", "pll_c", "pll_p", "clk_m" 840}; 841#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 842 843static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 844 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 845}; 846static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 847 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 848}; 849 850static const char *mux_pllp_clkm[] = { 851 "pll_p", "clk_m" 852}; 853static u32 mux_pllp_clkm_idx[] = { 854 [0] = 0, [1] = 3, 855}; 856 857static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 858 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 859}; 860#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 861 862static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 863 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 864 "pll_d2_out0", "clk_m" 865}; 866#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 867 868static const char *mux_pllm_pllc_pllp_plla[] = { 869 "pll_m", "pll_c", "pll_p", "pll_a_out0" 870}; 871#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 872 873static const char *mux_pllp_pllc_clkm[] = { 874 "pll_p", "pll_c", "pll_m" 875}; 876static u32 mux_pllp_pllc_clkm_idx[] = { 877 [0] = 0, [1] = 1, [2] = 3, 878}; 879 880static const char *mux_pllp_pllc_clkm_clk32[] = { 881 "pll_p", "pll_c", "clk_m", "clk_32k" 882}; 883#define mux_pllp_pllc_clkm_clk32_idx NULL 884 885static const char *mux_plla_clk32_pllp_clkm_plle[] = { 886 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 887}; 888#define mux_plla_clk32_pllp_clkm_plle_idx NULL 889 890static const char *mux_clkm_pllp_pllc_pllre[] = { 891 "clk_m", "pll_p", "pll_c", "pll_re_out" 892}; 893static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 894 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 895}; 896 897static const char *mux_clkm_48M_pllp_480M[] = { 898 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 899}; 900#define mux_clkm_48M_pllp_480M_idx NULL 901 902static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 903 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 904}; 905static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 906 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 907}; 908 909static const char *mux_plld_out0_plld2_out0[] = { 910 "pll_d_out0", "pll_d2_out0", 911}; 912#define mux_plld_out0_plld2_out0_idx NULL 913 914static const char *mux_d_audio_clk[] = { 915 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 916 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 917}; 918static u32 mux_d_audio_clk_idx[] = { 919 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 920 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 921}; 922 923static const char *mux_pllmcp_clkm[] = { 924 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 925}; 926 927static const struct clk_div_table pll_re_div_table[] = { 928 { .val = 0, .div = 1 }, 929 { .val = 1, .div = 2 }, 930 { .val = 2, .div = 3 }, 931 { .val = 3, .div = 4 }, 932 { .val = 4, .div = 5 }, 933 { .val = 5, .div = 6 }, 934 { .val = 0, .div = 0 }, 935}; 936 937static struct clk *clks[clk_max]; 938static struct clk_onecell_data clk_data; 939 940static unsigned long osc_freq; 941static unsigned long pll_ref_freq; 942 943static int __init tegra114_osc_clk_init(void __iomem *clk_base) 944{ 945 struct clk *clk; 946 u32 val, pll_ref_div; 947 948 val = readl_relaxed(clk_base + OSC_CTRL); 949 950 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; 951 if (!osc_freq) { 952 WARN_ON(1); 953 return -EINVAL; 954 } 955 956 /* clk_m */ 957 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 958 osc_freq); 959 clk_register_clkdev(clk, "clk_m", NULL); 960 clks[clk_m] = clk; 961 962 /* pll_ref */ 963 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 964 pll_ref_div = 1 << val; 965 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 966 CLK_SET_RATE_PARENT, 1, pll_ref_div); 967 clk_register_clkdev(clk, "pll_ref", NULL); 968 clks[pll_ref] = clk; 969 970 pll_ref_freq = osc_freq / pll_ref_div; 971 972 return 0; 973} 974 975static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 976{ 977 struct clk *clk; 978 979 /* clk_32k */ 980 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 981 32768); 982 clk_register_clkdev(clk, "clk_32k", NULL); 983 clks[clk_32k] = clk; 984 985 /* clk_m_div2 */ 986 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 987 CLK_SET_RATE_PARENT, 1, 2); 988 clk_register_clkdev(clk, "clk_m_div2", NULL); 989 clks[clk_m_div2] = clk; 990 991 /* clk_m_div4 */ 992 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 993 CLK_SET_RATE_PARENT, 1, 4); 994 clk_register_clkdev(clk, "clk_m_div4", NULL); 995 clks[clk_m_div4] = clk; 996 997} 998 999static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 1000{ 1001 u32 reg; 1002 int i; 1003 1004 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1005 if (osc_freq == utmi_parameters[i].osc_frequency) 1006 break; 1007 } 1008 1009 if (i >= ARRAY_SIZE(utmi_parameters)) { 1010 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1011 osc_freq); 1012 return; 1013 } 1014 1015 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1016 1017 /* Program UTMIP PLL stable and active counts */ 1018 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1019 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1020 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1021 1022 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1023 1024 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1025 active_delay_count); 1026 1027 /* Remove power downs from UTMIP PLL control bits */ 1028 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1029 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1030 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1031 1032 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1033 1034 /* Program UTMIP PLL delay and oscillator frequency counts */ 1035 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1036 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1037 1038 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1039 enable_delay_count); 1040 1041 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1042 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1043 xtal_freq_count); 1044 1045 /* Remove power downs from UTMIP PLL control bits */ 1046 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1047 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1048 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1049 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1050 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1051 1052 /* Setup HW control of UTMIPLL */ 1053 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1054 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1055 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1056 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1057 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1058 1059 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1060 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1061 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1062 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1063 1064 udelay(1); 1065 1066 /* Setup SW override of UTMIPLL assuming USB2.0 1067 ports are assigned to USB2 */ 1068 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1069 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1070 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1071 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1072 1073 udelay(1); 1074 1075 /* Enable HW control UTMIPLL */ 1076 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1077 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1078 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1079} 1080 1081static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params) 1082{ 1083 pll_params->vco_min = 1084 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq; 1085} 1086 1087static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1088 void __iomem *clk_base) 1089{ 1090 u32 val; 1091 u32 step_a, step_b; 1092 1093 switch (pll_ref_freq) { 1094 case 12000000: 1095 case 13000000: 1096 case 26000000: 1097 step_a = 0x2B; 1098 step_b = 0x0B; 1099 break; 1100 case 16800000: 1101 step_a = 0x1A; 1102 step_b = 0x09; 1103 break; 1104 case 19200000: 1105 step_a = 0x12; 1106 step_b = 0x08; 1107 break; 1108 default: 1109 pr_err("%s: Unexpected reference rate %lu\n", 1110 __func__, pll_ref_freq); 1111 WARN_ON(1); 1112 return -EINVAL; 1113 } 1114 1115 val = step_a << pll_params->stepa_shift; 1116 val |= step_b << pll_params->stepb_shift; 1117 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1118 1119 return 0; 1120} 1121 1122static void __init _init_iddq(struct tegra_clk_pll_params *pll_params, 1123 void __iomem *clk_base) 1124{ 1125 u32 val, val_iddq; 1126 1127 val = readl_relaxed(clk_base + pll_params->base_reg); 1128 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1129 1130 if (val & BIT(30)) 1131 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1132 else { 1133 val_iddq |= BIT(pll_params->iddq_bit_idx); 1134 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1135 } 1136} 1137 1138static void __init tegra114_pll_init(void __iomem *clk_base, 1139 void __iomem *pmc) 1140{ 1141 u32 val; 1142 struct clk *clk; 1143 1144 /* PLLC */ 1145 _clip_vco_min(&pll_c_params); 1146 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1147 _init_iddq(&pll_c_params, clk_base); 1148 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1149 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1150 pll_c_freq_table, NULL); 1151 clk_register_clkdev(clk, "pll_c", NULL); 1152 clks[pll_c] = clk; 1153 1154 /* PLLC_OUT1 */ 1155 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1156 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1157 8, 8, 1, NULL); 1158 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1159 clk_base + PLLC_OUT, 1, 0, 1160 CLK_SET_RATE_PARENT, 0, NULL); 1161 clk_register_clkdev(clk, "pll_c_out1", NULL); 1162 clks[pll_c_out1] = clk; 1163 } 1164 1165 /* PLLC2 */ 1166 _clip_vco_min(&pll_c2_params); 1167 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1168 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1169 pll_cx_freq_table, NULL); 1170 clk_register_clkdev(clk, "pll_c2", NULL); 1171 clks[pll_c2] = clk; 1172 1173 /* PLLC3 */ 1174 _clip_vco_min(&pll_c3_params); 1175 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1176 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1177 pll_cx_freq_table, NULL); 1178 clk_register_clkdev(clk, "pll_c3", NULL); 1179 clks[pll_c3] = clk; 1180 1181 /* PLLP */ 1182 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, 1183 408000000, &pll_p_params, 1184 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 1185 pll_p_freq_table, NULL); 1186 clk_register_clkdev(clk, "pll_p", NULL); 1187 clks[pll_p] = clk; 1188 1189 /* PLLP_OUT1 */ 1190 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 1191 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1192 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1193 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 1194 clk_base + PLLP_OUTA, 1, 0, 1195 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1196 &pll_div_lock); 1197 clk_register_clkdev(clk, "pll_p_out1", NULL); 1198 clks[pll_p_out1] = clk; 1199 1200 /* PLLP_OUT2 */ 1201 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 1202 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1203 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1204 &pll_div_lock); 1205 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 1206 clk_base + PLLP_OUTA, 17, 16, 1207 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1208 &pll_div_lock); 1209 clk_register_clkdev(clk, "pll_p_out2", NULL); 1210 clks[pll_p_out2] = clk; 1211 1212 /* PLLP_OUT3 */ 1213 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 1214 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1215 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1216 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 1217 clk_base + PLLP_OUTB, 1, 0, 1218 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1219 &pll_div_lock); 1220 clk_register_clkdev(clk, "pll_p_out3", NULL); 1221 clks[pll_p_out3] = clk; 1222 1223 /* PLLP_OUT4 */ 1224 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 1225 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1226 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1227 &pll_div_lock); 1228 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 1229 clk_base + PLLP_OUTB, 17, 16, 1230 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1231 &pll_div_lock); 1232 clk_register_clkdev(clk, "pll_p_out4", NULL); 1233 clks[pll_p_out4] = clk; 1234 1235 /* PLLM */ 1236 _clip_vco_min(&pll_m_params); 1237 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1238 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1239 &pll_m_params, TEGRA_PLL_USE_LOCK, 1240 pll_m_freq_table, NULL); 1241 clk_register_clkdev(clk, "pll_m", NULL); 1242 clks[pll_m] = clk; 1243 1244 /* PLLM_OUT1 */ 1245 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1246 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1247 8, 8, 1, NULL); 1248 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1249 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1250 CLK_SET_RATE_PARENT, 0, NULL); 1251 clk_register_clkdev(clk, "pll_m_out1", NULL); 1252 clks[pll_m_out1] = clk; 1253 1254 /* PLLM_UD */ 1255 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1256 CLK_SET_RATE_PARENT, 1, 1); 1257 1258 /* PLLX */ 1259 _clip_vco_min(&pll_x_params); 1260 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) { 1261 _init_iddq(&pll_x_params, clk_base); 1262 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, 1263 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params, 1264 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL); 1265 clk_register_clkdev(clk, "pll_x", NULL); 1266 clks[pll_x] = clk; 1267 } 1268 1269 /* PLLX_OUT0 */ 1270 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 1271 CLK_SET_RATE_PARENT, 1, 2); 1272 clk_register_clkdev(clk, "pll_x_out0", NULL); 1273 clks[pll_x_out0] = clk; 1274 1275 /* PLLU */ 1276 val = readl(clk_base + pll_u_params.base_reg); 1277 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1278 writel(val, clk_base + pll_u_params.base_reg); 1279 1280 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1281 0, &pll_u_params, TEGRA_PLLU | 1282 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1283 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock); 1284 clk_register_clkdev(clk, "pll_u", NULL); 1285 clks[pll_u] = clk; 1286 1287 tegra114_utmi_param_configure(clk_base); 1288 1289 /* PLLU_480M */ 1290 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1291 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1292 22, 0, &pll_u_lock); 1293 clk_register_clkdev(clk, "pll_u_480M", NULL); 1294 clks[pll_u_480M] = clk; 1295 1296 /* PLLU_60M */ 1297 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1298 CLK_SET_RATE_PARENT, 1, 8); 1299 clk_register_clkdev(clk, "pll_u_60M", NULL); 1300 clks[pll_u_60M] = clk; 1301 1302 /* PLLU_48M */ 1303 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1304 CLK_SET_RATE_PARENT, 1, 10); 1305 clk_register_clkdev(clk, "pll_u_48M", NULL); 1306 clks[pll_u_48M] = clk; 1307 1308 /* PLLU_12M */ 1309 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1310 CLK_SET_RATE_PARENT, 1, 40); 1311 clk_register_clkdev(clk, "pll_u_12M", NULL); 1312 clks[pll_u_12M] = clk; 1313 1314 /* PLLD */ 1315 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1316 0, &pll_d_params, 1317 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1318 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock); 1319 clk_register_clkdev(clk, "pll_d", NULL); 1320 clks[pll_d] = clk; 1321 1322 /* PLLD_OUT0 */ 1323 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1324 CLK_SET_RATE_PARENT, 1, 2); 1325 clk_register_clkdev(clk, "pll_d_out0", NULL); 1326 clks[pll_d_out0] = clk; 1327 1328 /* PLLD2 */ 1329 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1330 0, &pll_d2_params, 1331 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1332 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock); 1333 clk_register_clkdev(clk, "pll_d2", NULL); 1334 clks[pll_d2] = clk; 1335 1336 /* PLLD2_OUT0 */ 1337 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1338 CLK_SET_RATE_PARENT, 1, 2); 1339 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1340 clks[pll_d2_out0] = clk; 1341 1342 /* PLLA */ 1343 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, 1344 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1345 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1346 clk_register_clkdev(clk, "pll_a", NULL); 1347 clks[pll_a] = clk; 1348 1349 /* PLLA_OUT0 */ 1350 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1351 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1352 8, 8, 1, NULL); 1353 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1354 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1355 CLK_SET_RATE_PARENT, 0, NULL); 1356 clk_register_clkdev(clk, "pll_a_out0", NULL); 1357 clks[pll_a_out0] = clk; 1358 1359 /* PLLRE */ 1360 _clip_vco_min(&pll_re_vco_params); 1361 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1362 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1363 NULL, &pll_re_lock, pll_ref_freq); 1364 clk_register_clkdev(clk, "pll_re_vco", NULL); 1365 clks[pll_re_vco] = clk; 1366 1367 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1368 clk_base + PLLRE_BASE, 16, 4, 0, 1369 pll_re_div_table, &pll_re_lock); 1370 clk_register_clkdev(clk, "pll_re_out", NULL); 1371 clks[pll_re_out] = clk; 1372 1373 /* PLLE */ 1374 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1375 clk_base, 0, 100000000, &pll_e_params, 1376 pll_e_freq_table, NULL); 1377 clk_register_clkdev(clk, "pll_e_out0", NULL); 1378 clks[pll_e_out0] = clk; 1379} 1380 1381static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1382 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1383}; 1384 1385static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1386 "clk_m_div4", "extern1", 1387}; 1388 1389static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1390 "clk_m_div4", "extern2", 1391}; 1392 1393static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1394 "clk_m_div4", "extern3", 1395}; 1396 1397static void __init tegra114_audio_clk_init(void __iomem *clk_base) 1398{ 1399 struct clk *clk; 1400 1401 /* spdif_in_sync */ 1402 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1403 24000000); 1404 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1405 clks[spdif_in_sync] = clk; 1406 1407 /* i2s0_sync */ 1408 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1409 clk_register_clkdev(clk, "i2s0_sync", NULL); 1410 clks[i2s0_sync] = clk; 1411 1412 /* i2s1_sync */ 1413 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1414 clk_register_clkdev(clk, "i2s1_sync", NULL); 1415 clks[i2s1_sync] = clk; 1416 1417 /* i2s2_sync */ 1418 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1419 clk_register_clkdev(clk, "i2s2_sync", NULL); 1420 clks[i2s2_sync] = clk; 1421 1422 /* i2s3_sync */ 1423 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1424 clk_register_clkdev(clk, "i2s3_sync", NULL); 1425 clks[i2s3_sync] = clk; 1426 1427 /* i2s4_sync */ 1428 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1429 clk_register_clkdev(clk, "i2s4_sync", NULL); 1430 clks[i2s4_sync] = clk; 1431 1432 /* vimclk_sync */ 1433 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1434 clk_register_clkdev(clk, "vimclk_sync", NULL); 1435 clks[vimclk_sync] = clk; 1436 1437 /* audio0 */ 1438 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1439 ARRAY_SIZE(mux_audio_sync_clk), 0, 1440 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1441 NULL); 1442 clks[audio0_mux] = clk; 1443 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1444 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1445 CLK_GATE_SET_TO_DISABLE, NULL); 1446 clk_register_clkdev(clk, "audio0", NULL); 1447 clks[audio0] = clk; 1448 1449 /* audio1 */ 1450 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1451 ARRAY_SIZE(mux_audio_sync_clk), 0, 1452 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1453 NULL); 1454 clks[audio1_mux] = clk; 1455 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1456 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1457 CLK_GATE_SET_TO_DISABLE, NULL); 1458 clk_register_clkdev(clk, "audio1", NULL); 1459 clks[audio1] = clk; 1460 1461 /* audio2 */ 1462 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1463 ARRAY_SIZE(mux_audio_sync_clk), 0, 1464 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1465 NULL); 1466 clks[audio2_mux] = clk; 1467 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1468 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1469 CLK_GATE_SET_TO_DISABLE, NULL); 1470 clk_register_clkdev(clk, "audio2", NULL); 1471 clks[audio2] = clk; 1472 1473 /* audio3 */ 1474 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1475 ARRAY_SIZE(mux_audio_sync_clk), 0, 1476 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1477 NULL); 1478 clks[audio3_mux] = clk; 1479 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1480 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1481 CLK_GATE_SET_TO_DISABLE, NULL); 1482 clk_register_clkdev(clk, "audio3", NULL); 1483 clks[audio3] = clk; 1484 1485 /* audio4 */ 1486 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1487 ARRAY_SIZE(mux_audio_sync_clk), 0, 1488 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1489 NULL); 1490 clks[audio4_mux] = clk; 1491 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1492 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1493 CLK_GATE_SET_TO_DISABLE, NULL); 1494 clk_register_clkdev(clk, "audio4", NULL); 1495 clks[audio4] = clk; 1496 1497 /* spdif */ 1498 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1499 ARRAY_SIZE(mux_audio_sync_clk), 0, 1500 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1501 NULL); 1502 clks[spdif_mux] = clk; 1503 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1504 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1505 CLK_GATE_SET_TO_DISABLE, NULL); 1506 clk_register_clkdev(clk, "spdif", NULL); 1507 clks[spdif] = clk; 1508 1509 /* audio0_2x */ 1510 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1511 CLK_SET_RATE_PARENT, 2, 1); 1512 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1513 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 1514 0, &clk_doubler_lock); 1515 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1516 TEGRA_PERIPH_NO_RESET, clk_base, 1517 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1518 periph_clk_enb_refcnt); 1519 clk_register_clkdev(clk, "audio0_2x", NULL); 1520 clks[audio0_2x] = clk; 1521 1522 /* audio1_2x */ 1523 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1524 CLK_SET_RATE_PARENT, 2, 1); 1525 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1526 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 1527 0, &clk_doubler_lock); 1528 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1529 TEGRA_PERIPH_NO_RESET, clk_base, 1530 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1531 periph_clk_enb_refcnt); 1532 clk_register_clkdev(clk, "audio1_2x", NULL); 1533 clks[audio1_2x] = clk; 1534 1535 /* audio2_2x */ 1536 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1537 CLK_SET_RATE_PARENT, 2, 1); 1538 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1539 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 1540 0, &clk_doubler_lock); 1541 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1542 TEGRA_PERIPH_NO_RESET, clk_base, 1543 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1544 periph_clk_enb_refcnt); 1545 clk_register_clkdev(clk, "audio2_2x", NULL); 1546 clks[audio2_2x] = clk; 1547 1548 /* audio3_2x */ 1549 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1550 CLK_SET_RATE_PARENT, 2, 1); 1551 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1552 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 1553 0, &clk_doubler_lock); 1554 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1555 TEGRA_PERIPH_NO_RESET, clk_base, 1556 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1557 periph_clk_enb_refcnt); 1558 clk_register_clkdev(clk, "audio3_2x", NULL); 1559 clks[audio3_2x] = clk; 1560 1561 /* audio4_2x */ 1562 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1563 CLK_SET_RATE_PARENT, 2, 1); 1564 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1565 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 1566 0, &clk_doubler_lock); 1567 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1568 TEGRA_PERIPH_NO_RESET, clk_base, 1569 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1570 periph_clk_enb_refcnt); 1571 clk_register_clkdev(clk, "audio4_2x", NULL); 1572 clks[audio4_2x] = clk; 1573 1574 /* spdif_2x */ 1575 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1576 CLK_SET_RATE_PARENT, 2, 1); 1577 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1578 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 1579 0, &clk_doubler_lock); 1580 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1581 TEGRA_PERIPH_NO_RESET, clk_base, 1582 CLK_SET_RATE_PARENT, 118, 1583 &periph_v_regs, periph_clk_enb_refcnt); 1584 clk_register_clkdev(clk, "spdif_2x", NULL); 1585 clks[spdif_2x] = clk; 1586} 1587 1588static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1589{ 1590 struct clk *clk; 1591 1592 /* clk_out_1 */ 1593 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1594 ARRAY_SIZE(clk_out1_parents), 0, 1595 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1596 &clk_out_lock); 1597 clks[clk_out_1_mux] = clk; 1598 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1599 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1600 &clk_out_lock); 1601 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1602 clks[clk_out_1] = clk; 1603 1604 /* clk_out_2 */ 1605 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1606 ARRAY_SIZE(clk_out2_parents), 0, 1607 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1608 &clk_out_lock); 1609 clks[clk_out_2_mux] = clk; 1610 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1611 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1612 &clk_out_lock); 1613 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1614 clks[clk_out_2] = clk; 1615 1616 /* clk_out_3 */ 1617 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1618 ARRAY_SIZE(clk_out3_parents), 0, 1619 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1620 &clk_out_lock); 1621 clks[clk_out_3_mux] = clk; 1622 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1623 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1624 &clk_out_lock); 1625 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1626 clks[clk_out_3] = clk; 1627 1628 /* blink */ 1629 /* clear the blink timer register to directly output clk_32k */ 1630 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1631 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1632 pmc_base + PMC_DPD_PADS_ORIDE, 1633 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1634 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1635 pmc_base + PMC_CTRL, 1636 PMC_CTRL_BLINK_ENB, 0, NULL); 1637 clk_register_clkdev(clk, "blink", NULL); 1638 clks[blink] = clk; 1639 1640} 1641 1642static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1643 "pll_p_out3", "pll_p_out2", "unused", 1644 "clk_32k", "pll_m_out1" }; 1645 1646static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1647 "pll_p", "pll_p_out4", "unused", 1648 "unused", "pll_x" }; 1649 1650static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1651 "pll_p", "pll_p_out4", "unused", 1652 "unused", "pll_x", "pll_x_out0" }; 1653 1654static void __init tegra114_super_clk_init(void __iomem *clk_base) 1655{ 1656 struct clk *clk; 1657 1658 /* CCLKG */ 1659 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1660 ARRAY_SIZE(cclk_g_parents), 1661 CLK_SET_RATE_PARENT, 1662 clk_base + CCLKG_BURST_POLICY, 1663 0, 4, 0, 0, NULL); 1664 clk_register_clkdev(clk, "cclk_g", NULL); 1665 clks[cclk_g] = clk; 1666 1667 /* CCLKLP */ 1668 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1669 ARRAY_SIZE(cclk_lp_parents), 1670 CLK_SET_RATE_PARENT, 1671 clk_base + CCLKLP_BURST_POLICY, 1672 0, 4, 8, 9, NULL); 1673 clk_register_clkdev(clk, "cclk_lp", NULL); 1674 clks[cclk_lp] = clk; 1675 1676 /* SCLK */ 1677 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1678 ARRAY_SIZE(sclk_parents), 1679 CLK_SET_RATE_PARENT, 1680 clk_base + SCLK_BURST_POLICY, 1681 0, 4, 0, 0, NULL); 1682 clk_register_clkdev(clk, "sclk", NULL); 1683 clks[sclk] = clk; 1684 1685 /* HCLK */ 1686 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1687 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1688 &sysrate_lock); 1689 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | 1690 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1691 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1692 clk_register_clkdev(clk, "hclk", NULL); 1693 clks[hclk] = clk; 1694 1695 /* PCLK */ 1696 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1697 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1698 &sysrate_lock); 1699 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 1700 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1701 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1702 clk_register_clkdev(clk, "pclk", NULL); 1703 clks[pclk] = clk; 1704} 1705 1706static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1707 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1708 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1709 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1710 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1711 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1712 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1713 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1714 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm), 1715 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx), 1716 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx), 1717 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda), 1718 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x), 1719 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1720 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1721 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1722 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1723 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1724 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1725 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1726 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1727 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1728 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1729 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1730 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1731 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1732 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1733 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED), 1734 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1735 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace), 1736 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1737 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1738 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1739 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1), 1740 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2), 1741 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3), 1742 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4), 1743 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5), 1744 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1745 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1746 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1747 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1748 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d), 1749 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d), 1750 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1751 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1752 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1753 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc), 1754 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec), 1755 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1756 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1757 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab), 1758 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd), 1759 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile), 1760 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp), 1761 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp), 1762 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1763 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1764 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1765 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1766 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1767 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1768 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se), 1769 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED), 1770 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm), 1771 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src), 1772 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src), 1773 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src), 1774 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src), 1775 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src), 1776 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio), 1777 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0), 1778 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1), 1779 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2), 1780}; 1781 1782static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1783 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1), 1784 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2), 1785}; 1786 1787static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1788{ 1789 struct tegra_periph_init_data *data; 1790 struct clk *clk; 1791 int i; 1792 u32 val; 1793 1794 /* apbdma */ 1795 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1796 0, 34, &periph_h_regs, 1797 periph_clk_enb_refcnt); 1798 clks[apbdma] = clk; 1799 1800 /* rtc */ 1801 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1802 TEGRA_PERIPH_ON_APB | 1803 TEGRA_PERIPH_NO_RESET, clk_base, 1804 0, 4, &periph_l_regs, 1805 periph_clk_enb_refcnt); 1806 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1807 clks[rtc] = clk; 1808 1809 /* kbc */ 1810 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1811 TEGRA_PERIPH_ON_APB | 1812 TEGRA_PERIPH_NO_RESET, clk_base, 1813 0, 36, &periph_h_regs, 1814 periph_clk_enb_refcnt); 1815 clks[kbc] = clk; 1816 1817 /* timer */ 1818 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1819 0, 5, &periph_l_regs, 1820 periph_clk_enb_refcnt); 1821 clk_register_clkdev(clk, NULL, "timer"); 1822 clks[timer] = clk; 1823 1824 /* kfuse */ 1825 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1826 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1827 &periph_h_regs, periph_clk_enb_refcnt); 1828 clks[kfuse] = clk; 1829 1830 /* fuse */ 1831 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1832 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1833 &periph_h_regs, periph_clk_enb_refcnt); 1834 clks[fuse] = clk; 1835 1836 /* fuse_burn */ 1837 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1838 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1839 &periph_h_regs, periph_clk_enb_refcnt); 1840 clks[fuse_burn] = clk; 1841 1842 /* apbif */ 1843 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1844 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1845 &periph_v_regs, periph_clk_enb_refcnt); 1846 clks[apbif] = clk; 1847 1848 /* hda2hdmi */ 1849 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1850 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1851 &periph_w_regs, periph_clk_enb_refcnt); 1852 clks[hda2hdmi] = clk; 1853 1854 /* vcp */ 1855 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1856 29, &periph_l_regs, 1857 periph_clk_enb_refcnt); 1858 clks[vcp] = clk; 1859 1860 /* bsea */ 1861 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 1862 0, 62, &periph_h_regs, 1863 periph_clk_enb_refcnt); 1864 clks[bsea] = clk; 1865 1866 /* bsev */ 1867 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 1868 0, 63, &periph_h_regs, 1869 periph_clk_enb_refcnt); 1870 clks[bsev] = clk; 1871 1872 /* mipi-cal */ 1873 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1874 0, 56, &periph_h_regs, 1875 periph_clk_enb_refcnt); 1876 clks[mipi_cal] = clk; 1877 1878 /* usbd */ 1879 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 1880 0, 22, &periph_l_regs, 1881 periph_clk_enb_refcnt); 1882 clks[usbd] = clk; 1883 1884 /* usb2 */ 1885 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 1886 0, 58, &periph_h_regs, 1887 periph_clk_enb_refcnt); 1888 clks[usb2] = clk; 1889 1890 /* usb3 */ 1891 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 1892 0, 59, &periph_h_regs, 1893 periph_clk_enb_refcnt); 1894 clks[usb3] = clk; 1895 1896 /* csi */ 1897 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1898 0, 52, &periph_h_regs, 1899 periph_clk_enb_refcnt); 1900 clks[csi] = clk; 1901 1902 /* isp */ 1903 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 1904 23, &periph_l_regs, 1905 periph_clk_enb_refcnt); 1906 clks[isp] = clk; 1907 1908 /* csus */ 1909 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1910 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 1911 &periph_u_regs, periph_clk_enb_refcnt); 1912 clks[csus] = clk; 1913 1914 /* dds */ 1915 clk = tegra_clk_register_periph_gate("dds", "clk_m", 1916 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 1917 &periph_w_regs, periph_clk_enb_refcnt); 1918 clks[dds] = clk; 1919 1920 /* dp2 */ 1921 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 1922 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 1923 &periph_w_regs, periph_clk_enb_refcnt); 1924 clks[dp2] = clk; 1925 1926 /* dtv */ 1927 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1928 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 1929 &periph_u_regs, periph_clk_enb_refcnt); 1930 clks[dtv] = clk; 1931 1932 /* dsia */ 1933 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1934 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1935 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1936 clks[dsia_mux] = clk; 1937 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 1938 0, 48, &periph_h_regs, 1939 periph_clk_enb_refcnt); 1940 clks[dsia] = clk; 1941 1942 /* dsib */ 1943 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1944 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1945 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1946 clks[dsib_mux] = clk; 1947 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 1948 0, 82, &periph_u_regs, 1949 periph_clk_enb_refcnt); 1950 clks[dsib] = clk; 1951 1952 /* xusb_hs_src */ 1953 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); 1954 val |= BIT(25); /* always select PLLU_60M */ 1955 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); 1956 1957 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 1958 1, 1); 1959 clks[xusb_hs_src] = clk; 1960 1961 /* xusb_host */ 1962 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 1963 clk_base, 0, 89, &periph_u_regs, 1964 periph_clk_enb_refcnt); 1965 clks[xusb_host] = clk; 1966 1967 /* xusb_ss */ 1968 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 1969 clk_base, 0, 156, &periph_w_regs, 1970 periph_clk_enb_refcnt); 1971 clks[xusb_host] = clk; 1972 1973 /* xusb_dev */ 1974 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 1975 clk_base, 0, 95, &periph_u_regs, 1976 periph_clk_enb_refcnt); 1977 clks[xusb_dev] = clk; 1978 1979 /* emc */ 1980 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1981 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1982 clk_base + CLK_SOURCE_EMC, 1983 29, 3, 0, NULL); 1984 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 1985 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 1986 periph_clk_enb_refcnt); 1987 clks[emc] = clk; 1988 1989 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1990 data = &tegra_periph_clk_list[i]; 1991 clk = tegra_clk_register_periph(data->name, data->parent_names, 1992 data->num_parents, &data->periph, 1993 clk_base, data->offset, data->flags); 1994 clks[data->clk_id] = clk; 1995 } 1996 1997 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1998 data = &tegra_periph_nodiv_clk_list[i]; 1999 clk = tegra_clk_register_periph_nodiv(data->name, 2000 data->parent_names, data->num_parents, 2001 &data->periph, clk_base, data->offset); 2002 clks[data->clk_id] = clk; 2003 } 2004} 2005 2006static struct tegra_cpu_car_ops tegra114_cpu_car_ops; 2007 2008static const struct of_device_id pmc_match[] __initconst = { 2009 { .compatible = "nvidia,tegra114-pmc" }, 2010 {}, 2011}; 2012 2013static __initdata struct tegra_clk_init_table init_table[] = { 2014 {uarta, pll_p, 408000000, 0}, 2015 {uartb, pll_p, 408000000, 0}, 2016 {uartc, pll_p, 408000000, 0}, 2017 {uartd, pll_p, 408000000, 0}, 2018 {pll_a, clk_max, 564480000, 1}, 2019 {pll_a_out0, clk_max, 11289600, 1}, 2020 {extern1, pll_a_out0, 0, 1}, 2021 {clk_out_1_mux, extern1, 0, 1}, 2022 {clk_out_1, clk_max, 0, 1}, 2023 {i2s0, pll_a_out0, 11289600, 0}, 2024 {i2s1, pll_a_out0, 11289600, 0}, 2025 {i2s2, pll_a_out0, 11289600, 0}, 2026 {i2s3, pll_a_out0, 11289600, 0}, 2027 {i2s4, pll_a_out0, 11289600, 0}, 2028 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 2029}; 2030 2031static void __init tegra114_clock_apply_init_table(void) 2032{ 2033 tegra_init_from_table(init_table, clks, clk_max); 2034} 2035 2036static void __init tegra114_clock_init(struct device_node *np) 2037{ 2038 struct device_node *node; 2039 int i; 2040 2041 clk_base = of_iomap(np, 0); 2042 if (!clk_base) { 2043 pr_err("ioremap tegra114 CAR failed\n"); 2044 return; 2045 } 2046 2047 node = of_find_matching_node(NULL, pmc_match); 2048 if (!node) { 2049 pr_err("Failed to find pmc node\n"); 2050 WARN_ON(1); 2051 return; 2052 } 2053 2054 pmc_base = of_iomap(node, 0); 2055 if (!pmc_base) { 2056 pr_err("Can't map pmc registers\n"); 2057 WARN_ON(1); 2058 return; 2059 } 2060 2061 if (tegra114_osc_clk_init(clk_base) < 0) 2062 return; 2063 2064 tegra114_fixed_clk_init(clk_base); 2065 tegra114_pll_init(clk_base, pmc_base); 2066 tegra114_periph_clk_init(clk_base); 2067 tegra114_audio_clk_init(clk_base); 2068 tegra114_pmc_clk_init(pmc_base); 2069 tegra114_super_clk_init(clk_base); 2070 2071 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2072 if (IS_ERR(clks[i])) { 2073 pr_err 2074 ("Tegra114 clk %d: register failed with %ld\n", 2075 i, PTR_ERR(clks[i])); 2076 } 2077 if (!clks[i]) 2078 clks[i] = ERR_PTR(-EINVAL); 2079 } 2080 2081 clk_data.clks = clks; 2082 clk_data.clk_num = ARRAY_SIZE(clks); 2083 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2084 2085 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 2086 2087 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 2088} 2089CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); 2090