clk-tegra114.c revision c604283f52855a4568c18cfd4011bdcfeccf2c52
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/clk/tegra.h> 25 26#include "clk.h" 27 28#define RST_DEVICES_L 0x004 29#define RST_DEVICES_H 0x008 30#define RST_DEVICES_U 0x00C 31#define RST_DEVICES_V 0x358 32#define RST_DEVICES_W 0x35C 33#define RST_DEVICES_X 0x28C 34#define RST_DEVICES_SET_L 0x300 35#define RST_DEVICES_CLR_L 0x304 36#define RST_DEVICES_SET_H 0x308 37#define RST_DEVICES_CLR_H 0x30c 38#define RST_DEVICES_SET_U 0x310 39#define RST_DEVICES_CLR_U 0x314 40#define RST_DEVICES_SET_V 0x430 41#define RST_DEVICES_CLR_V 0x434 42#define RST_DEVICES_SET_W 0x438 43#define RST_DEVICES_CLR_W 0x43c 44#define RST_DEVICES_NUM 5 45 46#define CLK_OUT_ENB_L 0x010 47#define CLK_OUT_ENB_H 0x014 48#define CLK_OUT_ENB_U 0x018 49#define CLK_OUT_ENB_V 0x360 50#define CLK_OUT_ENB_W 0x364 51#define CLK_OUT_ENB_X 0x280 52#define CLK_OUT_ENB_SET_L 0x320 53#define CLK_OUT_ENB_CLR_L 0x324 54#define CLK_OUT_ENB_SET_H 0x328 55#define CLK_OUT_ENB_CLR_H 0x32c 56#define CLK_OUT_ENB_SET_U 0x330 57#define CLK_OUT_ENB_CLR_U 0x334 58#define CLK_OUT_ENB_SET_V 0x440 59#define CLK_OUT_ENB_CLR_V 0x444 60#define CLK_OUT_ENB_SET_W 0x448 61#define CLK_OUT_ENB_CLR_W 0x44c 62#define CLK_OUT_ENB_SET_X 0x284 63#define CLK_OUT_ENB_CLR_X 0x288 64#define CLK_OUT_ENB_NUM 6 65 66#define PLLC_BASE 0x80 67#define PLLC_MISC2 0x88 68#define PLLC_MISC 0x8c 69#define PLLC2_BASE 0x4e8 70#define PLLC2_MISC 0x4ec 71#define PLLC3_BASE 0x4fc 72#define PLLC3_MISC 0x500 73#define PLLM_BASE 0x90 74#define PLLM_MISC 0x9c 75#define PLLP_BASE 0xa0 76#define PLLP_MISC 0xac 77#define PLLX_BASE 0xe0 78#define PLLX_MISC 0xe4 79#define PLLX_MISC2 0x514 80#define PLLX_MISC3 0x518 81#define PLLD_BASE 0xd0 82#define PLLD_MISC 0xdc 83#define PLLD2_BASE 0x4b8 84#define PLLD2_MISC 0x4bc 85#define PLLE_BASE 0xe8 86#define PLLE_MISC 0xec 87#define PLLA_BASE 0xb0 88#define PLLA_MISC 0xbc 89#define PLLU_BASE 0xc0 90#define PLLU_MISC 0xcc 91#define PLLRE_BASE 0x4c4 92#define PLLRE_MISC 0x4c8 93 94#define PLL_MISC_LOCK_ENABLE 18 95#define PLLC_MISC_LOCK_ENABLE 24 96#define PLLDU_MISC_LOCK_ENABLE 22 97#define PLLE_MISC_LOCK_ENABLE 9 98#define PLLRE_MISC_LOCK_ENABLE 30 99 100#define PLLC_IDDQ_BIT 26 101#define PLLX_IDDQ_BIT 3 102#define PLLRE_IDDQ_BIT 16 103 104#define PLL_BASE_LOCK BIT(27) 105#define PLLE_MISC_LOCK BIT(11) 106#define PLLRE_MISC_LOCK BIT(24) 107#define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 108 109#define PLLE_AUX 0x48c 110#define PLLC_OUT 0x84 111#define PLLM_OUT 0x94 112#define PLLP_OUTA 0xa4 113#define PLLP_OUTB 0xa8 114#define PLLA_OUT 0xb4 115 116#define AUDIO_SYNC_CLK_I2S0 0x4a0 117#define AUDIO_SYNC_CLK_I2S1 0x4a4 118#define AUDIO_SYNC_CLK_I2S2 0x4a8 119#define AUDIO_SYNC_CLK_I2S3 0x4ac 120#define AUDIO_SYNC_CLK_I2S4 0x4b0 121#define AUDIO_SYNC_CLK_SPDIF 0x4b4 122 123#define AUDIO_SYNC_DOUBLER 0x49c 124 125#define PMC_CLK_OUT_CNTRL 0x1a8 126#define PMC_DPD_PADS_ORIDE 0x1c 127#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 128#define PMC_CTRL 0 129#define PMC_CTRL_BLINK_ENB 7 130 131#define OSC_CTRL 0x50 132#define OSC_CTRL_OSC_FREQ_SHIFT 28 133#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 134 135#define PLLXC_SW_MAX_P 6 136 137#define CCLKG_BURST_POLICY 0x368 138#define CCLKLP_BURST_POLICY 0x370 139#define SCLK_BURST_POLICY 0x028 140#define SYSTEM_CLK_RATE 0x030 141 142#define UTMIP_PLL_CFG2 0x488 143#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 144#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 145#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 146#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 147#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 148 149#define UTMIP_PLL_CFG1 0x484 150#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 151#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 152#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 153#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 154#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 155#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 156#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 157 158#define UTMIPLL_HW_PWRDN_CFG0 0x52c 159#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 160#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 161#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 162#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 163#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 164#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 165#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 166#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 167 168#define CLK_SOURCE_I2S0 0x1d8 169#define CLK_SOURCE_I2S1 0x100 170#define CLK_SOURCE_I2S2 0x104 171#define CLK_SOURCE_NDFLASH 0x160 172#define CLK_SOURCE_I2S3 0x3bc 173#define CLK_SOURCE_I2S4 0x3c0 174#define CLK_SOURCE_SPDIF_OUT 0x108 175#define CLK_SOURCE_SPDIF_IN 0x10c 176#define CLK_SOURCE_PWM 0x110 177#define CLK_SOURCE_ADX 0x638 178#define CLK_SOURCE_AMX 0x63c 179#define CLK_SOURCE_HDA 0x428 180#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 181#define CLK_SOURCE_SBC1 0x134 182#define CLK_SOURCE_SBC2 0x118 183#define CLK_SOURCE_SBC3 0x11c 184#define CLK_SOURCE_SBC4 0x1b4 185#define CLK_SOURCE_SBC5 0x3c8 186#define CLK_SOURCE_SBC6 0x3cc 187#define CLK_SOURCE_SATA_OOB 0x420 188#define CLK_SOURCE_SATA 0x424 189#define CLK_SOURCE_NDSPEED 0x3f8 190#define CLK_SOURCE_VFIR 0x168 191#define CLK_SOURCE_SDMMC1 0x150 192#define CLK_SOURCE_SDMMC2 0x154 193#define CLK_SOURCE_SDMMC3 0x1bc 194#define CLK_SOURCE_SDMMC4 0x164 195#define CLK_SOURCE_VDE 0x1c8 196#define CLK_SOURCE_CSITE 0x1d4 197#define CLK_SOURCE_LA 0x1f8 198#define CLK_SOURCE_TRACE 0x634 199#define CLK_SOURCE_OWR 0x1cc 200#define CLK_SOURCE_NOR 0x1d0 201#define CLK_SOURCE_MIPI 0x174 202#define CLK_SOURCE_I2C1 0x124 203#define CLK_SOURCE_I2C2 0x198 204#define CLK_SOURCE_I2C3 0x1b8 205#define CLK_SOURCE_I2C4 0x3c4 206#define CLK_SOURCE_I2C5 0x128 207#define CLK_SOURCE_UARTA 0x178 208#define CLK_SOURCE_UARTB 0x17c 209#define CLK_SOURCE_UARTC 0x1a0 210#define CLK_SOURCE_UARTD 0x1c0 211#define CLK_SOURCE_UARTE 0x1c4 212#define CLK_SOURCE_UARTA_DBG 0x178 213#define CLK_SOURCE_UARTB_DBG 0x17c 214#define CLK_SOURCE_UARTC_DBG 0x1a0 215#define CLK_SOURCE_UARTD_DBG 0x1c0 216#define CLK_SOURCE_UARTE_DBG 0x1c4 217#define CLK_SOURCE_3D 0x158 218#define CLK_SOURCE_2D 0x15c 219#define CLK_SOURCE_VI_SENSOR 0x1a8 220#define CLK_SOURCE_VI 0x148 221#define CLK_SOURCE_EPP 0x16c 222#define CLK_SOURCE_MSENC 0x1f0 223#define CLK_SOURCE_TSEC 0x1f4 224#define CLK_SOURCE_HOST1X 0x180 225#define CLK_SOURCE_HDMI 0x18c 226#define CLK_SOURCE_DISP1 0x138 227#define CLK_SOURCE_DISP2 0x13c 228#define CLK_SOURCE_CILAB 0x614 229#define CLK_SOURCE_CILCD 0x618 230#define CLK_SOURCE_CILE 0x61c 231#define CLK_SOURCE_DSIALP 0x620 232#define CLK_SOURCE_DSIBLP 0x624 233#define CLK_SOURCE_TSENSOR 0x3b8 234#define CLK_SOURCE_D_AUDIO 0x3d0 235#define CLK_SOURCE_DAM0 0x3d8 236#define CLK_SOURCE_DAM1 0x3dc 237#define CLK_SOURCE_DAM2 0x3e0 238#define CLK_SOURCE_ACTMON 0x3e8 239#define CLK_SOURCE_EXTERN1 0x3ec 240#define CLK_SOURCE_EXTERN2 0x3f0 241#define CLK_SOURCE_EXTERN3 0x3f4 242#define CLK_SOURCE_I2CSLOW 0x3fc 243#define CLK_SOURCE_SE 0x42c 244#define CLK_SOURCE_MSELECT 0x3b4 245#define CLK_SOURCE_SOC_THERM 0x644 246#define CLK_SOURCE_XUSB_HOST_SRC 0x600 247#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 248#define CLK_SOURCE_XUSB_FS_SRC 0x608 249#define CLK_SOURCE_XUSB_SS_SRC 0x610 250#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 251#define CLK_SOURCE_EMC 0x19c 252 253static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 254 255static void __iomem *clk_base; 256static void __iomem *pmc_base; 257 258static DEFINE_SPINLOCK(pll_d_lock); 259static DEFINE_SPINLOCK(pll_d2_lock); 260static DEFINE_SPINLOCK(pll_u_lock); 261static DEFINE_SPINLOCK(pll_div_lock); 262static DEFINE_SPINLOCK(pll_re_lock); 263static DEFINE_SPINLOCK(clk_doubler_lock); 264static DEFINE_SPINLOCK(clk_out_lock); 265static DEFINE_SPINLOCK(sysrate_lock); 266 267static struct pdiv_map pllxc_p[] = { 268 { .pdiv = 1, .hw_val = 0 }, 269 { .pdiv = 2, .hw_val = 1 }, 270 { .pdiv = 3, .hw_val = 2 }, 271 { .pdiv = 4, .hw_val = 3 }, 272 { .pdiv = 5, .hw_val = 4 }, 273 { .pdiv = 6, .hw_val = 5 }, 274 { .pdiv = 8, .hw_val = 6 }, 275 { .pdiv = 10, .hw_val = 7 }, 276 { .pdiv = 12, .hw_val = 8 }, 277 { .pdiv = 16, .hw_val = 9 }, 278 { .pdiv = 12, .hw_val = 10 }, 279 { .pdiv = 16, .hw_val = 11 }, 280 { .pdiv = 20, .hw_val = 12 }, 281 { .pdiv = 24, .hw_val = 13 }, 282 { .pdiv = 32, .hw_val = 14 }, 283 { .pdiv = 0, .hw_val = 0 }, 284}; 285 286static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 287 { 12000000, 624000000, 104, 0, 2}, 288 { 12000000, 600000000, 100, 0, 2}, 289 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 290 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 291 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 292 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 293 { 0, 0, 0, 0, 0, 0 }, 294}; 295 296static struct tegra_clk_pll_params pll_c_params = { 297 .input_min = 12000000, 298 .input_max = 800000000, 299 .cf_min = 12000000, 300 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 301 .vco_min = 600000000, 302 .vco_max = 1400000000, 303 .base_reg = PLLC_BASE, 304 .misc_reg = PLLC_MISC, 305 .lock_mask = PLL_BASE_LOCK, 306 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 307 .lock_delay = 300, 308 .iddq_reg = PLLC_MISC, 309 .iddq_bit_idx = PLLC_IDDQ_BIT, 310 .max_p = PLLXC_SW_MAX_P, 311 .dyn_ramp_reg = PLLC_MISC2, 312 .stepa_shift = 17, 313 .stepb_shift = 9, 314 .pdiv_tohw = pllxc_p, 315}; 316 317static struct pdiv_map pllc_p[] = { 318 { .pdiv = 1, .hw_val = 0 }, 319 { .pdiv = 2, .hw_val = 1 }, 320 { .pdiv = 4, .hw_val = 3 }, 321 { .pdiv = 8, .hw_val = 5 }, 322 { .pdiv = 16, .hw_val = 7 }, 323 { .pdiv = 0, .hw_val = 0 }, 324}; 325 326static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 327 {12000000, 600000000, 100, 0, 2}, 328 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 329 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 330 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 331 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 332 {0, 0, 0, 0, 0, 0}, 333}; 334 335static struct tegra_clk_pll_params pll_c2_params = { 336 .input_min = 12000000, 337 .input_max = 48000000, 338 .cf_min = 12000000, 339 .cf_max = 19200000, 340 .vco_min = 600000000, 341 .vco_max = 1200000000, 342 .base_reg = PLLC2_BASE, 343 .misc_reg = PLLC2_MISC, 344 .lock_mask = PLL_BASE_LOCK, 345 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 346 .lock_delay = 300, 347 .pdiv_tohw = pllc_p, 348 .ext_misc_reg[0] = 0x4f0, 349 .ext_misc_reg[1] = 0x4f4, 350 .ext_misc_reg[2] = 0x4f8, 351}; 352 353static struct tegra_clk_pll_params pll_c3_params = { 354 .input_min = 12000000, 355 .input_max = 48000000, 356 .cf_min = 12000000, 357 .cf_max = 19200000, 358 .vco_min = 600000000, 359 .vco_max = 1200000000, 360 .base_reg = PLLC3_BASE, 361 .misc_reg = PLLC3_MISC, 362 .lock_mask = PLL_BASE_LOCK, 363 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 364 .lock_delay = 300, 365 .pdiv_tohw = pllc_p, 366 .ext_misc_reg[0] = 0x504, 367 .ext_misc_reg[1] = 0x508, 368 .ext_misc_reg[2] = 0x50c, 369}; 370 371static struct pdiv_map pllm_p[] = { 372 { .pdiv = 1, .hw_val = 0 }, 373 { .pdiv = 2, .hw_val = 1 }, 374 { .pdiv = 0, .hw_val = 0 }, 375}; 376 377static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 378 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 379 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 380 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 381 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 382 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 383 {0, 0, 0, 0, 0, 0}, 384}; 385 386static struct tegra_clk_pll_params pll_m_params = { 387 .input_min = 12000000, 388 .input_max = 500000000, 389 .cf_min = 12000000, 390 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 391 .vco_min = 400000000, 392 .vco_max = 1066000000, 393 .base_reg = PLLM_BASE, 394 .misc_reg = PLLM_MISC, 395 .lock_mask = PLL_BASE_LOCK, 396 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 397 .lock_delay = 300, 398 .max_p = 2, 399 .pdiv_tohw = pllm_p, 400}; 401 402static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 403 {12000000, 216000000, 432, 12, 1, 8}, 404 {13000000, 216000000, 432, 13, 1, 8}, 405 {16800000, 216000000, 360, 14, 1, 8}, 406 {19200000, 216000000, 360, 16, 1, 8}, 407 {26000000, 216000000, 432, 26, 1, 8}, 408 {0, 0, 0, 0, 0, 0}, 409}; 410 411static struct tegra_clk_pll_params pll_p_params = { 412 .input_min = 2000000, 413 .input_max = 31000000, 414 .cf_min = 1000000, 415 .cf_max = 6000000, 416 .vco_min = 200000000, 417 .vco_max = 700000000, 418 .base_reg = PLLP_BASE, 419 .misc_reg = PLLP_MISC, 420 .lock_mask = PLL_BASE_LOCK, 421 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 422 .lock_delay = 300, 423}; 424 425static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 426 {9600000, 282240000, 147, 5, 0, 4}, 427 {9600000, 368640000, 192, 5, 0, 4}, 428 {9600000, 240000000, 200, 8, 0, 8}, 429 430 {28800000, 282240000, 245, 25, 0, 8}, 431 {28800000, 368640000, 320, 25, 0, 8}, 432 {28800000, 240000000, 200, 24, 0, 8}, 433 {0, 0, 0, 0, 0, 0}, 434}; 435 436 437static struct tegra_clk_pll_params pll_a_params = { 438 .input_min = 2000000, 439 .input_max = 31000000, 440 .cf_min = 1000000, 441 .cf_max = 6000000, 442 .vco_min = 200000000, 443 .vco_max = 700000000, 444 .base_reg = PLLA_BASE, 445 .misc_reg = PLLA_MISC, 446 .lock_mask = PLL_BASE_LOCK, 447 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 448 .lock_delay = 300, 449}; 450 451static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 452 {12000000, 216000000, 864, 12, 2, 12}, 453 {13000000, 216000000, 864, 13, 2, 12}, 454 {16800000, 216000000, 720, 14, 2, 12}, 455 {19200000, 216000000, 720, 16, 2, 12}, 456 {26000000, 216000000, 864, 26, 2, 12}, 457 458 {12000000, 594000000, 594, 12, 0, 12}, 459 {13000000, 594000000, 594, 13, 0, 12}, 460 {16800000, 594000000, 495, 14, 0, 12}, 461 {19200000, 594000000, 495, 16, 0, 12}, 462 {26000000, 594000000, 594, 26, 0, 12}, 463 464 {12000000, 1000000000, 1000, 12, 0, 12}, 465 {13000000, 1000000000, 1000, 13, 0, 12}, 466 {19200000, 1000000000, 625, 12, 0, 12}, 467 {26000000, 1000000000, 1000, 26, 0, 12}, 468 469 {0, 0, 0, 0, 0, 0}, 470}; 471 472static struct tegra_clk_pll_params pll_d_params = { 473 .input_min = 2000000, 474 .input_max = 40000000, 475 .cf_min = 1000000, 476 .cf_max = 6000000, 477 .vco_min = 500000000, 478 .vco_max = 1000000000, 479 .base_reg = PLLD_BASE, 480 .misc_reg = PLLD_MISC, 481 .lock_mask = PLL_BASE_LOCK, 482 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 483 .lock_delay = 1000, 484}; 485 486static struct tegra_clk_pll_params pll_d2_params = { 487 .input_min = 2000000, 488 .input_max = 40000000, 489 .cf_min = 1000000, 490 .cf_max = 6000000, 491 .vco_min = 500000000, 492 .vco_max = 1000000000, 493 .base_reg = PLLD2_BASE, 494 .misc_reg = PLLD2_MISC, 495 .lock_mask = PLL_BASE_LOCK, 496 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 497 .lock_delay = 1000, 498}; 499 500static struct pdiv_map pllu_p[] = { 501 { .pdiv = 1, .hw_val = 1 }, 502 { .pdiv = 2, .hw_val = 0 }, 503 { .pdiv = 0, .hw_val = 0 }, 504}; 505 506static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 507 {12000000, 480000000, 960, 12, 0, 12}, 508 {13000000, 480000000, 960, 13, 0, 12}, 509 {16800000, 480000000, 400, 7, 0, 5}, 510 {19200000, 480000000, 200, 4, 0, 3}, 511 {26000000, 480000000, 960, 26, 0, 12}, 512 {0, 0, 0, 0, 0, 0}, 513}; 514 515static struct tegra_clk_pll_params pll_u_params = { 516 .input_min = 2000000, 517 .input_max = 40000000, 518 .cf_min = 1000000, 519 .cf_max = 6000000, 520 .vco_min = 480000000, 521 .vco_max = 960000000, 522 .base_reg = PLLU_BASE, 523 .misc_reg = PLLU_MISC, 524 .lock_mask = PLL_BASE_LOCK, 525 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 526 .lock_delay = 1000, 527 .pdiv_tohw = pllu_p, 528}; 529 530static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 531 /* 1 GHz */ 532 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 533 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 534 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 535 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 536 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 537 538 {0, 0, 0, 0, 0, 0}, 539}; 540 541static struct tegra_clk_pll_params pll_x_params = { 542 .input_min = 12000000, 543 .input_max = 800000000, 544 .cf_min = 12000000, 545 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 546 .vco_min = 700000000, 547 .vco_max = 2400000000U, 548 .base_reg = PLLX_BASE, 549 .misc_reg = PLLX_MISC, 550 .lock_mask = PLL_BASE_LOCK, 551 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 552 .lock_delay = 300, 553 .iddq_reg = PLLX_MISC3, 554 .iddq_bit_idx = PLLX_IDDQ_BIT, 555 .max_p = PLLXC_SW_MAX_P, 556 .dyn_ramp_reg = PLLX_MISC2, 557 .stepa_shift = 16, 558 .stepb_shift = 24, 559 .pdiv_tohw = pllxc_p, 560}; 561 562static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 563 /* PLLE special case: use cpcon field to store cml divider value */ 564 {336000000, 100000000, 100, 21, 16, 11}, 565 {312000000, 100000000, 200, 26, 24, 13}, 566 {0, 0, 0, 0, 0, 0}, 567}; 568 569static struct tegra_clk_pll_params pll_e_params = { 570 .input_min = 12000000, 571 .input_max = 1000000000, 572 .cf_min = 12000000, 573 .cf_max = 75000000, 574 .vco_min = 1600000000, 575 .vco_max = 2400000000U, 576 .base_reg = PLLE_BASE, 577 .misc_reg = PLLE_MISC, 578 .aux_reg = PLLE_AUX, 579 .lock_mask = PLLE_MISC_LOCK, 580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 581 .lock_delay = 300, 582}; 583 584static struct tegra_clk_pll_params pll_re_vco_params = { 585 .input_min = 12000000, 586 .input_max = 1000000000, 587 .cf_min = 12000000, 588 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 589 .vco_min = 300000000, 590 .vco_max = 600000000, 591 .base_reg = PLLRE_BASE, 592 .misc_reg = PLLRE_MISC, 593 .lock_mask = PLLRE_MISC_LOCK, 594 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 595 .lock_delay = 300, 596 .iddq_reg = PLLRE_MISC, 597 .iddq_bit_idx = PLLRE_IDDQ_BIT, 598}; 599 600/* Peripheral clock registers */ 601 602static struct tegra_clk_periph_regs periph_l_regs = { 603 .enb_reg = CLK_OUT_ENB_L, 604 .enb_set_reg = CLK_OUT_ENB_SET_L, 605 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 606 .rst_reg = RST_DEVICES_L, 607 .rst_set_reg = RST_DEVICES_SET_L, 608 .rst_clr_reg = RST_DEVICES_CLR_L, 609}; 610 611static struct tegra_clk_periph_regs periph_h_regs = { 612 .enb_reg = CLK_OUT_ENB_H, 613 .enb_set_reg = CLK_OUT_ENB_SET_H, 614 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 615 .rst_reg = RST_DEVICES_H, 616 .rst_set_reg = RST_DEVICES_SET_H, 617 .rst_clr_reg = RST_DEVICES_CLR_H, 618}; 619 620static struct tegra_clk_periph_regs periph_u_regs = { 621 .enb_reg = CLK_OUT_ENB_U, 622 .enb_set_reg = CLK_OUT_ENB_SET_U, 623 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 624 .rst_reg = RST_DEVICES_U, 625 .rst_set_reg = RST_DEVICES_SET_U, 626 .rst_clr_reg = RST_DEVICES_CLR_U, 627}; 628 629static struct tegra_clk_periph_regs periph_v_regs = { 630 .enb_reg = CLK_OUT_ENB_V, 631 .enb_set_reg = CLK_OUT_ENB_SET_V, 632 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 633 .rst_reg = RST_DEVICES_V, 634 .rst_set_reg = RST_DEVICES_SET_V, 635 .rst_clr_reg = RST_DEVICES_CLR_V, 636}; 637 638static struct tegra_clk_periph_regs periph_w_regs = { 639 .enb_reg = CLK_OUT_ENB_W, 640 .enb_set_reg = CLK_OUT_ENB_SET_W, 641 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 642 .rst_reg = RST_DEVICES_W, 643 .rst_set_reg = RST_DEVICES_SET_W, 644 .rst_clr_reg = RST_DEVICES_CLR_W, 645}; 646 647/* possible OSC frequencies in Hz */ 648static unsigned long tegra114_input_freq[] = { 649 [0] = 13000000, 650 [1] = 16800000, 651 [4] = 19200000, 652 [5] = 38400000, 653 [8] = 12000000, 654 [9] = 48000000, 655 [12] = 260000000, 656}; 657 658#define MASK(x) (BIT(x) - 1) 659 660#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 661 _clk_num, _regs, _gate_flags, _clk_id) \ 662 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 663 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 664 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 665 _parents##_idx, 0) 666 667#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 668 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 669 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 670 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 671 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 672 _parents##_idx, flags) 673 674#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 675 _clk_num, _regs, _gate_flags, _clk_id) \ 676 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 677 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \ 678 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 679 _parents##_idx, 0) 680 681#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 682 _clk_num, _regs, _gate_flags, _clk_id) \ 683 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 684 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 685 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 686 _clk_id, _parents##_idx, 0) 687 688#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 689 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 690 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 691 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 692 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 693 _clk_id, _parents##_idx, flags) 694 695#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 696 _clk_num, _regs, _gate_flags, _clk_id) \ 697 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 698 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 699 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 700 _clk_id, _parents##_idx, 0) 701 702#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 703 _clk_num, _regs, _clk_id) \ 704 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 705 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\ 706 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \ 707 _parents##_idx, 0) 708 709#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 710 _clk_num, _regs, _clk_id) \ 711 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 712 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \ 713 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 714 715#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 716 _mux_shift, _mux_mask, _clk_num, _regs, \ 717 _gate_flags, _clk_id) \ 718 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 719 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 720 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 721 _clk_id, _parents##_idx, 0) 722 723#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 724 _clk_num, _regs, _gate_flags, _clk_id) \ 725 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 726 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 727 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 728 _clk_id, _parents##_idx, 0) 729 730#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 731 _regs, _gate_flags, _clk_id) \ 732 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 733 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \ 734 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 735 mux_d_audio_clk_idx, 0) 736 737enum tegra114_clk { 738 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12, 739 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19, 740 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27, 741 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40, 742 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48, 743 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56, 744 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65, 745 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73, 746 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80, 747 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91, 748 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102, 749 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1, 750 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x, 751 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120, 752 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128, 753 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148, 754 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192, 755 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k, 756 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2, 757 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3, 758 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0, 759 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0, 760 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync, 761 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0, 762 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3, 763 blink, xusb_host_src, xusb_falcon_src, xusb_fs_src, xusb_ss_src, 764 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp, 765 766 /* Mux clocks */ 767 768 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux, 769 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux, 770 dsib_mux, clk_max, 771}; 772 773struct utmi_clk_param { 774 /* Oscillator Frequency in KHz */ 775 u32 osc_frequency; 776 /* UTMIP PLL Enable Delay Count */ 777 u8 enable_delay_count; 778 /* UTMIP PLL Stable count */ 779 u8 stable_count; 780 /* UTMIP PLL Active delay count */ 781 u8 active_delay_count; 782 /* UTMIP PLL Xtal frequency count */ 783 u8 xtal_freq_count; 784}; 785 786static const struct utmi_clk_param utmi_parameters[] = { 787 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 788 .stable_count = 0x33, .active_delay_count = 0x05, 789 .xtal_freq_count = 0x7F}, 790 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 791 .stable_count = 0x4B, .active_delay_count = 0x06, 792 .xtal_freq_count = 0xBB}, 793 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 794 .stable_count = 0x2F, .active_delay_count = 0x04, 795 .xtal_freq_count = 0x76}, 796 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 797 .stable_count = 0x66, .active_delay_count = 0x09, 798 .xtal_freq_count = 0xFE}, 799 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 800 .stable_count = 0x41, .active_delay_count = 0x0A, 801 .xtal_freq_count = 0xA4}, 802}; 803 804/* peripheral mux definitions */ 805 806#define MUX_I2S_SPDIF(_id) \ 807static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 808 #_id, "pll_p",\ 809 "clk_m"}; 810MUX_I2S_SPDIF(audio0) 811MUX_I2S_SPDIF(audio1) 812MUX_I2S_SPDIF(audio2) 813MUX_I2S_SPDIF(audio3) 814MUX_I2S_SPDIF(audio4) 815MUX_I2S_SPDIF(audio) 816 817#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 818#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 819#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 820#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 821#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 822#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 823 824static const char *mux_pllp_pllc_pllm_clkm[] = { 825 "pll_p", "pll_c", "pll_m", "clk_m" 826}; 827#define mux_pllp_pllc_pllm_clkm_idx NULL 828 829static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 830#define mux_pllp_pllc_pllm_idx NULL 831 832static const char *mux_pllp_pllc_clk32_clkm[] = { 833 "pll_p", "pll_c", "clk_32k", "clk_m" 834}; 835#define mux_pllp_pllc_clk32_clkm_idx NULL 836 837static const char *mux_plla_pllc_pllp_clkm[] = { 838 "pll_a_out0", "pll_c", "pll_p", "clk_m" 839}; 840#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 841 842static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 843 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 844}; 845static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 846 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 847}; 848 849static const char *mux_pllp_clkm[] = { 850 "pll_p", "clk_m" 851}; 852static u32 mux_pllp_clkm_idx[] = { 853 [0] = 0, [1] = 3, 854}; 855 856static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 857 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 858}; 859#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 860 861static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 862 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 863 "pll_d2_out0", "clk_m" 864}; 865#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 866 867static const char *mux_pllm_pllc_pllp_plla[] = { 868 "pll_m", "pll_c", "pll_p", "pll_a_out0" 869}; 870#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 871 872static const char *mux_pllp_pllc_clkm[] = { 873 "pll_p", "pll_c", "pll_m" 874}; 875static u32 mux_pllp_pllc_clkm_idx[] = { 876 [0] = 0, [1] = 1, [2] = 3, 877}; 878 879static const char *mux_pllp_pllc_clkm_clk32[] = { 880 "pll_p", "pll_c", "clk_m", "clk_32k" 881}; 882#define mux_pllp_pllc_clkm_clk32_idx NULL 883 884static const char *mux_plla_clk32_pllp_clkm_plle[] = { 885 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 886}; 887#define mux_plla_clk32_pllp_clkm_plle_idx NULL 888 889static const char *mux_clkm_pllp_pllc_pllre[] = { 890 "clk_m", "pll_p", "pll_c", "pll_re_out" 891}; 892static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 893 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 894}; 895 896static const char *mux_clkm_48M_pllp_480M[] = { 897 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 898}; 899#define mux_clkm_48M_pllp_480M_idx NULL 900 901static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 902 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 903}; 904static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 905 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 906}; 907 908static const char *mux_plld_out0_plld2_out0[] = { 909 "pll_d_out0", "pll_d2_out0", 910}; 911#define mux_plld_out0_plld2_out0_idx NULL 912 913static const char *mux_d_audio_clk[] = { 914 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 915 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 916}; 917static u32 mux_d_audio_clk_idx[] = { 918 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 919 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 920}; 921 922static const char *mux_pllmcp_clkm[] = { 923 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 924}; 925 926static const struct clk_div_table pll_re_div_table[] = { 927 { .val = 0, .div = 1 }, 928 { .val = 1, .div = 2 }, 929 { .val = 2, .div = 3 }, 930 { .val = 3, .div = 4 }, 931 { .val = 4, .div = 5 }, 932 { .val = 5, .div = 6 }, 933 { .val = 0, .div = 0 }, 934}; 935 936static struct clk *clks[clk_max]; 937static struct clk_onecell_data clk_data; 938 939static unsigned long osc_freq; 940static unsigned long pll_ref_freq; 941 942static int __init tegra114_osc_clk_init(void __iomem *clk_base) 943{ 944 struct clk *clk; 945 u32 val, pll_ref_div; 946 947 val = readl_relaxed(clk_base + OSC_CTRL); 948 949 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; 950 if (!osc_freq) { 951 WARN_ON(1); 952 return -EINVAL; 953 } 954 955 /* clk_m */ 956 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 957 osc_freq); 958 clk_register_clkdev(clk, "clk_m", NULL); 959 clks[clk_m] = clk; 960 961 /* pll_ref */ 962 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 963 pll_ref_div = 1 << val; 964 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 965 CLK_SET_RATE_PARENT, 1, pll_ref_div); 966 clk_register_clkdev(clk, "pll_ref", NULL); 967 clks[pll_ref] = clk; 968 969 pll_ref_freq = osc_freq / pll_ref_div; 970 971 return 0; 972} 973 974static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 975{ 976 struct clk *clk; 977 978 /* clk_32k */ 979 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 980 32768); 981 clk_register_clkdev(clk, "clk_32k", NULL); 982 clks[clk_32k] = clk; 983 984 /* clk_m_div2 */ 985 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 986 CLK_SET_RATE_PARENT, 1, 2); 987 clk_register_clkdev(clk, "clk_m_div2", NULL); 988 clks[clk_m_div2] = clk; 989 990 /* clk_m_div4 */ 991 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 992 CLK_SET_RATE_PARENT, 1, 4); 993 clk_register_clkdev(clk, "clk_m_div4", NULL); 994 clks[clk_m_div4] = clk; 995 996} 997 998static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 999{ 1000 u32 reg; 1001 int i; 1002 1003 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1004 if (osc_freq == utmi_parameters[i].osc_frequency) 1005 break; 1006 } 1007 1008 if (i >= ARRAY_SIZE(utmi_parameters)) { 1009 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1010 osc_freq); 1011 return; 1012 } 1013 1014 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1015 1016 /* Program UTMIP PLL stable and active counts */ 1017 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1018 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1019 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1020 1021 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1022 1023 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1024 active_delay_count); 1025 1026 /* Remove power downs from UTMIP PLL control bits */ 1027 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1028 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1029 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1030 1031 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1032 1033 /* Program UTMIP PLL delay and oscillator frequency counts */ 1034 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1035 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1036 1037 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1038 enable_delay_count); 1039 1040 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1041 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1042 xtal_freq_count); 1043 1044 /* Remove power downs from UTMIP PLL control bits */ 1045 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1046 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1047 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1048 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1049 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1050 1051 /* Setup HW control of UTMIPLL */ 1052 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1053 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1054 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1055 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1056 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1057 1058 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1059 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1060 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1061 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1062 1063 udelay(1); 1064 1065 /* Setup SW override of UTMIPLL assuming USB2.0 1066 ports are assigned to USB2 */ 1067 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1068 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1069 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1070 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1071 1072 udelay(1); 1073 1074 /* Enable HW control UTMIPLL */ 1075 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1076 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1077 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1078} 1079 1080static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params) 1081{ 1082 pll_params->vco_min = 1083 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq; 1084} 1085 1086static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1087 void __iomem *clk_base) 1088{ 1089 u32 val; 1090 u32 step_a, step_b; 1091 1092 switch (pll_ref_freq) { 1093 case 12000000: 1094 case 13000000: 1095 case 26000000: 1096 step_a = 0x2B; 1097 step_b = 0x0B; 1098 break; 1099 case 16800000: 1100 step_a = 0x1A; 1101 step_b = 0x09; 1102 break; 1103 case 19200000: 1104 step_a = 0x12; 1105 step_b = 0x08; 1106 break; 1107 default: 1108 pr_err("%s: Unexpected reference rate %lu\n", 1109 __func__, pll_ref_freq); 1110 WARN_ON(1); 1111 return -EINVAL; 1112 } 1113 1114 val = step_a << pll_params->stepa_shift; 1115 val |= step_b << pll_params->stepb_shift; 1116 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1117 1118 return 0; 1119} 1120 1121static void __init _init_iddq(struct tegra_clk_pll_params *pll_params, 1122 void __iomem *clk_base) 1123{ 1124 u32 val, val_iddq; 1125 1126 val = readl_relaxed(clk_base + pll_params->base_reg); 1127 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1128 1129 if (val & BIT(30)) 1130 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1131 else { 1132 val_iddq |= BIT(pll_params->iddq_bit_idx); 1133 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1134 } 1135} 1136 1137static void __init tegra114_pll_init(void __iomem *clk_base, 1138 void __iomem *pmc) 1139{ 1140 u32 val; 1141 struct clk *clk; 1142 1143 /* PLLC */ 1144 _clip_vco_min(&pll_c_params); 1145 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1146 _init_iddq(&pll_c_params, clk_base); 1147 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1148 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1149 pll_c_freq_table, NULL); 1150 clk_register_clkdev(clk, "pll_c", NULL); 1151 clks[pll_c] = clk; 1152 1153 /* PLLC_OUT1 */ 1154 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1155 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1156 8, 8, 1, NULL); 1157 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1158 clk_base + PLLC_OUT, 1, 0, 1159 CLK_SET_RATE_PARENT, 0, NULL); 1160 clk_register_clkdev(clk, "pll_c_out1", NULL); 1161 clks[pll_c_out1] = clk; 1162 } 1163 1164 /* PLLC2 */ 1165 _clip_vco_min(&pll_c2_params); 1166 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1167 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1168 pll_cx_freq_table, NULL); 1169 clk_register_clkdev(clk, "pll_c2", NULL); 1170 clks[pll_c2] = clk; 1171 1172 /* PLLC3 */ 1173 _clip_vco_min(&pll_c3_params); 1174 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1175 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1176 pll_cx_freq_table, NULL); 1177 clk_register_clkdev(clk, "pll_c3", NULL); 1178 clks[pll_c3] = clk; 1179 1180 /* PLLP */ 1181 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, 1182 408000000, &pll_p_params, 1183 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 1184 pll_p_freq_table, NULL); 1185 clk_register_clkdev(clk, "pll_p", NULL); 1186 clks[pll_p] = clk; 1187 1188 /* PLLP_OUT1 */ 1189 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 1190 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1191 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1192 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 1193 clk_base + PLLP_OUTA, 1, 0, 1194 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1195 &pll_div_lock); 1196 clk_register_clkdev(clk, "pll_p_out1", NULL); 1197 clks[pll_p_out1] = clk; 1198 1199 /* PLLP_OUT2 */ 1200 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 1201 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1202 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1203 &pll_div_lock); 1204 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 1205 clk_base + PLLP_OUTA, 17, 16, 1206 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1207 &pll_div_lock); 1208 clk_register_clkdev(clk, "pll_p_out2", NULL); 1209 clks[pll_p_out2] = clk; 1210 1211 /* PLLP_OUT3 */ 1212 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 1213 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1214 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1215 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 1216 clk_base + PLLP_OUTB, 1, 0, 1217 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1218 &pll_div_lock); 1219 clk_register_clkdev(clk, "pll_p_out3", NULL); 1220 clks[pll_p_out3] = clk; 1221 1222 /* PLLP_OUT4 */ 1223 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 1224 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1225 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1226 &pll_div_lock); 1227 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 1228 clk_base + PLLP_OUTB, 17, 16, 1229 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1230 &pll_div_lock); 1231 clk_register_clkdev(clk, "pll_p_out4", NULL); 1232 clks[pll_p_out4] = clk; 1233 1234 /* PLLM */ 1235 _clip_vco_min(&pll_m_params); 1236 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1237 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1238 &pll_m_params, TEGRA_PLL_USE_LOCK, 1239 pll_m_freq_table, NULL); 1240 clk_register_clkdev(clk, "pll_m", NULL); 1241 clks[pll_m] = clk; 1242 1243 /* PLLM_OUT1 */ 1244 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1245 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1246 8, 8, 1, NULL); 1247 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1248 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1249 CLK_SET_RATE_PARENT, 0, NULL); 1250 clk_register_clkdev(clk, "pll_m_out1", NULL); 1251 clks[pll_m_out1] = clk; 1252 1253 /* PLLM_UD */ 1254 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1255 CLK_SET_RATE_PARENT, 1, 1); 1256 1257 /* PLLX */ 1258 _clip_vco_min(&pll_x_params); 1259 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) { 1260 _init_iddq(&pll_x_params, clk_base); 1261 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, 1262 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params, 1263 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL); 1264 clk_register_clkdev(clk, "pll_x", NULL); 1265 clks[pll_x] = clk; 1266 } 1267 1268 /* PLLX_OUT0 */ 1269 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 1270 CLK_SET_RATE_PARENT, 1, 2); 1271 clk_register_clkdev(clk, "pll_x_out0", NULL); 1272 clks[pll_x_out0] = clk; 1273 1274 /* PLLU */ 1275 val = readl(clk_base + pll_u_params.base_reg); 1276 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1277 writel(val, clk_base + pll_u_params.base_reg); 1278 1279 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1280 0, &pll_u_params, TEGRA_PLLU | 1281 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1282 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock); 1283 clk_register_clkdev(clk, "pll_u", NULL); 1284 clks[pll_u] = clk; 1285 1286 tegra114_utmi_param_configure(clk_base); 1287 1288 /* PLLU_480M */ 1289 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1290 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1291 22, 0, &pll_u_lock); 1292 clk_register_clkdev(clk, "pll_u_480M", NULL); 1293 clks[pll_u_480M] = clk; 1294 1295 /* PLLU_60M */ 1296 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1297 CLK_SET_RATE_PARENT, 1, 8); 1298 clk_register_clkdev(clk, "pll_u_60M", NULL); 1299 clks[pll_u_60M] = clk; 1300 1301 /* PLLU_48M */ 1302 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1303 CLK_SET_RATE_PARENT, 1, 10); 1304 clk_register_clkdev(clk, "pll_u_48M", NULL); 1305 clks[pll_u_48M] = clk; 1306 1307 /* PLLU_12M */ 1308 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1309 CLK_SET_RATE_PARENT, 1, 40); 1310 clk_register_clkdev(clk, "pll_u_12M", NULL); 1311 clks[pll_u_12M] = clk; 1312 1313 /* PLLD */ 1314 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1315 0, &pll_d_params, 1316 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1317 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock); 1318 clk_register_clkdev(clk, "pll_d", NULL); 1319 clks[pll_d] = clk; 1320 1321 /* PLLD_OUT0 */ 1322 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1323 CLK_SET_RATE_PARENT, 1, 2); 1324 clk_register_clkdev(clk, "pll_d_out0", NULL); 1325 clks[pll_d_out0] = clk; 1326 1327 /* PLLD2 */ 1328 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1329 0, &pll_d2_params, 1330 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1331 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock); 1332 clk_register_clkdev(clk, "pll_d2", NULL); 1333 clks[pll_d2] = clk; 1334 1335 /* PLLD2_OUT0 */ 1336 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1337 CLK_SET_RATE_PARENT, 1, 2); 1338 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1339 clks[pll_d2_out0] = clk; 1340 1341 /* PLLA */ 1342 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, 1343 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1344 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1345 clk_register_clkdev(clk, "pll_a", NULL); 1346 clks[pll_a] = clk; 1347 1348 /* PLLA_OUT0 */ 1349 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1350 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1351 8, 8, 1, NULL); 1352 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1353 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1354 CLK_SET_RATE_PARENT, 0, NULL); 1355 clk_register_clkdev(clk, "pll_a_out0", NULL); 1356 clks[pll_a_out0] = clk; 1357 1358 /* PLLRE */ 1359 _clip_vco_min(&pll_re_vco_params); 1360 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1361 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1362 NULL, &pll_re_lock, pll_ref_freq); 1363 clk_register_clkdev(clk, "pll_re_vco", NULL); 1364 clks[pll_re_vco] = clk; 1365 1366 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1367 clk_base + PLLRE_BASE, 16, 4, 0, 1368 pll_re_div_table, &pll_re_lock); 1369 clk_register_clkdev(clk, "pll_re_out", NULL); 1370 clks[pll_re_out] = clk; 1371 1372 /* PLLE */ 1373 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1374 clk_base, 0, 100000000, &pll_e_params, 1375 pll_e_freq_table, NULL); 1376 clk_register_clkdev(clk, "pll_e_out0", NULL); 1377 clks[pll_e_out0] = clk; 1378} 1379 1380static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1381 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1382}; 1383 1384static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1385 "clk_m_div4", "extern1", 1386}; 1387 1388static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1389 "clk_m_div4", "extern2", 1390}; 1391 1392static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1393 "clk_m_div4", "extern3", 1394}; 1395 1396static void __init tegra114_audio_clk_init(void __iomem *clk_base) 1397{ 1398 struct clk *clk; 1399 1400 /* spdif_in_sync */ 1401 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1402 24000000); 1403 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1404 clks[spdif_in_sync] = clk; 1405 1406 /* i2s0_sync */ 1407 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1408 clk_register_clkdev(clk, "i2s0_sync", NULL); 1409 clks[i2s0_sync] = clk; 1410 1411 /* i2s1_sync */ 1412 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1413 clk_register_clkdev(clk, "i2s1_sync", NULL); 1414 clks[i2s1_sync] = clk; 1415 1416 /* i2s2_sync */ 1417 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1418 clk_register_clkdev(clk, "i2s2_sync", NULL); 1419 clks[i2s2_sync] = clk; 1420 1421 /* i2s3_sync */ 1422 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1423 clk_register_clkdev(clk, "i2s3_sync", NULL); 1424 clks[i2s3_sync] = clk; 1425 1426 /* i2s4_sync */ 1427 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1428 clk_register_clkdev(clk, "i2s4_sync", NULL); 1429 clks[i2s4_sync] = clk; 1430 1431 /* vimclk_sync */ 1432 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1433 clk_register_clkdev(clk, "vimclk_sync", NULL); 1434 clks[vimclk_sync] = clk; 1435 1436 /* audio0 */ 1437 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1438 ARRAY_SIZE(mux_audio_sync_clk), 0, 1439 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1440 NULL); 1441 clks[audio0_mux] = clk; 1442 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1443 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1444 CLK_GATE_SET_TO_DISABLE, NULL); 1445 clk_register_clkdev(clk, "audio0", NULL); 1446 clks[audio0] = clk; 1447 1448 /* audio1 */ 1449 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1450 ARRAY_SIZE(mux_audio_sync_clk), 0, 1451 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1452 NULL); 1453 clks[audio1_mux] = clk; 1454 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1455 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1456 CLK_GATE_SET_TO_DISABLE, NULL); 1457 clk_register_clkdev(clk, "audio1", NULL); 1458 clks[audio1] = clk; 1459 1460 /* audio2 */ 1461 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1462 ARRAY_SIZE(mux_audio_sync_clk), 0, 1463 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1464 NULL); 1465 clks[audio2_mux] = clk; 1466 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1467 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1468 CLK_GATE_SET_TO_DISABLE, NULL); 1469 clk_register_clkdev(clk, "audio2", NULL); 1470 clks[audio2] = clk; 1471 1472 /* audio3 */ 1473 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1474 ARRAY_SIZE(mux_audio_sync_clk), 0, 1475 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1476 NULL); 1477 clks[audio3_mux] = clk; 1478 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1479 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1480 CLK_GATE_SET_TO_DISABLE, NULL); 1481 clk_register_clkdev(clk, "audio3", NULL); 1482 clks[audio3] = clk; 1483 1484 /* audio4 */ 1485 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1486 ARRAY_SIZE(mux_audio_sync_clk), 0, 1487 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1488 NULL); 1489 clks[audio4_mux] = clk; 1490 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1491 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1492 CLK_GATE_SET_TO_DISABLE, NULL); 1493 clk_register_clkdev(clk, "audio4", NULL); 1494 clks[audio4] = clk; 1495 1496 /* spdif */ 1497 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1498 ARRAY_SIZE(mux_audio_sync_clk), 0, 1499 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1500 NULL); 1501 clks[spdif_mux] = clk; 1502 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1503 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1504 CLK_GATE_SET_TO_DISABLE, NULL); 1505 clk_register_clkdev(clk, "spdif", NULL); 1506 clks[spdif] = clk; 1507 1508 /* audio0_2x */ 1509 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1510 CLK_SET_RATE_PARENT, 2, 1); 1511 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1512 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 1513 0, &clk_doubler_lock); 1514 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1515 TEGRA_PERIPH_NO_RESET, clk_base, 1516 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1517 periph_clk_enb_refcnt); 1518 clk_register_clkdev(clk, "audio0_2x", NULL); 1519 clks[audio0_2x] = clk; 1520 1521 /* audio1_2x */ 1522 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1523 CLK_SET_RATE_PARENT, 2, 1); 1524 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1525 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 1526 0, &clk_doubler_lock); 1527 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1528 TEGRA_PERIPH_NO_RESET, clk_base, 1529 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1530 periph_clk_enb_refcnt); 1531 clk_register_clkdev(clk, "audio1_2x", NULL); 1532 clks[audio1_2x] = clk; 1533 1534 /* audio2_2x */ 1535 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1536 CLK_SET_RATE_PARENT, 2, 1); 1537 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1538 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 1539 0, &clk_doubler_lock); 1540 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1541 TEGRA_PERIPH_NO_RESET, clk_base, 1542 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1543 periph_clk_enb_refcnt); 1544 clk_register_clkdev(clk, "audio2_2x", NULL); 1545 clks[audio2_2x] = clk; 1546 1547 /* audio3_2x */ 1548 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1549 CLK_SET_RATE_PARENT, 2, 1); 1550 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1551 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 1552 0, &clk_doubler_lock); 1553 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1554 TEGRA_PERIPH_NO_RESET, clk_base, 1555 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1556 periph_clk_enb_refcnt); 1557 clk_register_clkdev(clk, "audio3_2x", NULL); 1558 clks[audio3_2x] = clk; 1559 1560 /* audio4_2x */ 1561 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1562 CLK_SET_RATE_PARENT, 2, 1); 1563 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1564 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 1565 0, &clk_doubler_lock); 1566 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1567 TEGRA_PERIPH_NO_RESET, clk_base, 1568 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1569 periph_clk_enb_refcnt); 1570 clk_register_clkdev(clk, "audio4_2x", NULL); 1571 clks[audio4_2x] = clk; 1572 1573 /* spdif_2x */ 1574 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1575 CLK_SET_RATE_PARENT, 2, 1); 1576 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1577 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 1578 0, &clk_doubler_lock); 1579 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1580 TEGRA_PERIPH_NO_RESET, clk_base, 1581 CLK_SET_RATE_PARENT, 118, 1582 &periph_v_regs, periph_clk_enb_refcnt); 1583 clk_register_clkdev(clk, "spdif_2x", NULL); 1584 clks[spdif_2x] = clk; 1585} 1586 1587static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1588{ 1589 struct clk *clk; 1590 1591 /* clk_out_1 */ 1592 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1593 ARRAY_SIZE(clk_out1_parents), 0, 1594 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1595 &clk_out_lock); 1596 clks[clk_out_1_mux] = clk; 1597 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1598 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1599 &clk_out_lock); 1600 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1601 clks[clk_out_1] = clk; 1602 1603 /* clk_out_2 */ 1604 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1605 ARRAY_SIZE(clk_out1_parents), 0, 1606 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1607 &clk_out_lock); 1608 clks[clk_out_2_mux] = clk; 1609 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1610 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1611 &clk_out_lock); 1612 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1613 clks[clk_out_2] = clk; 1614 1615 /* clk_out_3 */ 1616 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1617 ARRAY_SIZE(clk_out1_parents), 0, 1618 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1619 &clk_out_lock); 1620 clks[clk_out_3_mux] = clk; 1621 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1622 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1623 &clk_out_lock); 1624 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1625 clks[clk_out_3] = clk; 1626 1627 /* blink */ 1628 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1629 pmc_base + PMC_DPD_PADS_ORIDE, 1630 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1631 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1632 pmc_base + PMC_CTRL, 1633 PMC_CTRL_BLINK_ENB, 0, NULL); 1634 clk_register_clkdev(clk, "blink", NULL); 1635 clks[blink] = clk; 1636 1637} 1638 1639static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1640 "pll_p_out3", "pll_p_out2", "unused", 1641 "clk_32k", "pll_m_out1" }; 1642 1643static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1644 "pll_p", "pll_p_out4", "unused", 1645 "unused", "pll_x" }; 1646 1647static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1648 "pll_p", "pll_p_out4", "unused", 1649 "unused", "pll_x", "pll_x_out0" }; 1650 1651static void __init tegra114_super_clk_init(void __iomem *clk_base) 1652{ 1653 struct clk *clk; 1654 1655 /* CCLKG */ 1656 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1657 ARRAY_SIZE(cclk_g_parents), 1658 CLK_SET_RATE_PARENT, 1659 clk_base + CCLKG_BURST_POLICY, 1660 0, 4, 0, 0, NULL); 1661 clk_register_clkdev(clk, "cclk_g", NULL); 1662 clks[cclk_g] = clk; 1663 1664 /* CCLKLP */ 1665 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1666 ARRAY_SIZE(cclk_lp_parents), 1667 CLK_SET_RATE_PARENT, 1668 clk_base + CCLKLP_BURST_POLICY, 1669 0, 4, 8, 9, NULL); 1670 clk_register_clkdev(clk, "cclk_lp", NULL); 1671 clks[cclk_lp] = clk; 1672 1673 /* SCLK */ 1674 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1675 ARRAY_SIZE(sclk_parents), 1676 CLK_SET_RATE_PARENT, 1677 clk_base + SCLK_BURST_POLICY, 1678 0, 4, 0, 0, NULL); 1679 clk_register_clkdev(clk, "sclk", NULL); 1680 clks[sclk] = clk; 1681 1682 /* HCLK */ 1683 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1684 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1685 &sysrate_lock); 1686 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | 1687 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1688 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1689 clk_register_clkdev(clk, "hclk", NULL); 1690 clks[hclk] = clk; 1691 1692 /* PCLK */ 1693 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1694 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1695 &sysrate_lock); 1696 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 1697 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1698 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1699 clk_register_clkdev(clk, "pclk", NULL); 1700 clks[pclk] = clk; 1701} 1702 1703static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1704 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1705 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1706 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1707 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1708 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1709 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1710 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1711 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm), 1712 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx), 1713 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx), 1714 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda), 1715 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x), 1716 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1717 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1718 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1719 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1720 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1721 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1722 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1723 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1724 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1725 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1726 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1727 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1728 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1729 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1730 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED), 1731 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1732 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace), 1733 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1734 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1735 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1736 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1), 1737 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2), 1738 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3), 1739 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4), 1740 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5), 1741 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1742 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1743 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1744 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1745 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d), 1746 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d), 1747 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1748 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1749 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1750 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_h_regs, TEGRA_PERIPH_WAR_1005168, msenc), 1751 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec), 1752 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1753 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1754 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab), 1755 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd), 1756 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile), 1757 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp), 1758 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp), 1759 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1760 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1761 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1762 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1763 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1764 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1765 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se), 1766 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED), 1767 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm), 1768 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src), 1769 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src), 1770 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src), 1771 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src), 1772 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src), 1773 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio), 1774 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0), 1775 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1), 1776 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2), 1777}; 1778 1779static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1780 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1), 1781 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2), 1782}; 1783 1784static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1785{ 1786 struct tegra_periph_init_data *data; 1787 struct clk *clk; 1788 int i; 1789 u32 val; 1790 1791 /* apbdma */ 1792 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1793 0, 34, &periph_h_regs, 1794 periph_clk_enb_refcnt); 1795 clks[apbdma] = clk; 1796 1797 /* rtc */ 1798 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1799 TEGRA_PERIPH_ON_APB | 1800 TEGRA_PERIPH_NO_RESET, clk_base, 1801 0, 4, &periph_l_regs, 1802 periph_clk_enb_refcnt); 1803 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1804 clks[rtc] = clk; 1805 1806 /* kbc */ 1807 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1808 TEGRA_PERIPH_ON_APB | 1809 TEGRA_PERIPH_NO_RESET, clk_base, 1810 0, 36, &periph_h_regs, 1811 periph_clk_enb_refcnt); 1812 clks[kbc] = clk; 1813 1814 /* timer */ 1815 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1816 0, 5, &periph_l_regs, 1817 periph_clk_enb_refcnt); 1818 clk_register_clkdev(clk, NULL, "timer"); 1819 clks[timer] = clk; 1820 1821 /* kfuse */ 1822 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1823 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1824 &periph_h_regs, periph_clk_enb_refcnt); 1825 clks[kfuse] = clk; 1826 1827 /* fuse */ 1828 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1829 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1830 &periph_h_regs, periph_clk_enb_refcnt); 1831 clks[fuse] = clk; 1832 1833 /* fuse_burn */ 1834 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1835 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1836 &periph_h_regs, periph_clk_enb_refcnt); 1837 clks[fuse_burn] = clk; 1838 1839 /* apbif */ 1840 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1841 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1842 &periph_v_regs, periph_clk_enb_refcnt); 1843 clks[apbif] = clk; 1844 1845 /* hda2hdmi */ 1846 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1847 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1848 &periph_w_regs, periph_clk_enb_refcnt); 1849 clks[hda2hdmi] = clk; 1850 1851 /* vcp */ 1852 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1853 29, &periph_l_regs, 1854 periph_clk_enb_refcnt); 1855 clks[vcp] = clk; 1856 1857 /* bsea */ 1858 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 1859 0, 62, &periph_h_regs, 1860 periph_clk_enb_refcnt); 1861 clks[bsea] = clk; 1862 1863 /* bsev */ 1864 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 1865 0, 63, &periph_h_regs, 1866 periph_clk_enb_refcnt); 1867 clks[bsev] = clk; 1868 1869 /* mipi-cal */ 1870 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1871 0, 56, &periph_h_regs, 1872 periph_clk_enb_refcnt); 1873 clks[mipi_cal] = clk; 1874 1875 /* usbd */ 1876 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 1877 0, 22, &periph_l_regs, 1878 periph_clk_enb_refcnt); 1879 clks[usbd] = clk; 1880 1881 /* usb2 */ 1882 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 1883 0, 58, &periph_h_regs, 1884 periph_clk_enb_refcnt); 1885 clks[usb2] = clk; 1886 1887 /* usb3 */ 1888 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 1889 0, 59, &periph_h_regs, 1890 periph_clk_enb_refcnt); 1891 clks[usb3] = clk; 1892 1893 /* csi */ 1894 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1895 0, 52, &periph_h_regs, 1896 periph_clk_enb_refcnt); 1897 clks[csi] = clk; 1898 1899 /* isp */ 1900 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 1901 23, &periph_l_regs, 1902 periph_clk_enb_refcnt); 1903 clks[isp] = clk; 1904 1905 /* csus */ 1906 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1907 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 1908 &periph_u_regs, periph_clk_enb_refcnt); 1909 clks[csus] = clk; 1910 1911 /* dds */ 1912 clk = tegra_clk_register_periph_gate("dds", "clk_m", 1913 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 1914 &periph_w_regs, periph_clk_enb_refcnt); 1915 clks[dds] = clk; 1916 1917 /* dp2 */ 1918 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 1919 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 1920 &periph_w_regs, periph_clk_enb_refcnt); 1921 clks[dp2] = clk; 1922 1923 /* dtv */ 1924 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1925 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 1926 &periph_u_regs, periph_clk_enb_refcnt); 1927 clks[dtv] = clk; 1928 1929 /* dsia */ 1930 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1931 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1932 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1933 clks[dsia_mux] = clk; 1934 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 1935 0, 48, &periph_h_regs, 1936 periph_clk_enb_refcnt); 1937 clks[dsia] = clk; 1938 1939 /* dsib */ 1940 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1941 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1942 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1943 clks[dsib_mux] = clk; 1944 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 1945 0, 82, &periph_u_regs, 1946 periph_clk_enb_refcnt); 1947 clks[dsib] = clk; 1948 1949 /* xusb_hs_src */ 1950 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); 1951 val |= BIT(25); /* always select PLLU_60M */ 1952 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); 1953 1954 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 1955 1, 1); 1956 clks[xusb_hs_src] = clk; 1957 1958 /* xusb_host */ 1959 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 1960 clk_base, 0, 89, &periph_u_regs, 1961 periph_clk_enb_refcnt); 1962 clks[xusb_host] = clk; 1963 1964 /* xusb_ss */ 1965 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 1966 clk_base, 0, 156, &periph_w_regs, 1967 periph_clk_enb_refcnt); 1968 clks[xusb_host] = clk; 1969 1970 /* xusb_dev */ 1971 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 1972 clk_base, 0, 95, &periph_u_regs, 1973 periph_clk_enb_refcnt); 1974 clks[xusb_dev] = clk; 1975 1976 /* emc */ 1977 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1978 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1979 clk_base + CLK_SOURCE_EMC, 1980 29, 3, 0, NULL); 1981 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 1982 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 1983 periph_clk_enb_refcnt); 1984 clks[emc] = clk; 1985 1986 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1987 data = &tegra_periph_clk_list[i]; 1988 clk = tegra_clk_register_periph(data->name, data->parent_names, 1989 data->num_parents, &data->periph, 1990 clk_base, data->offset, data->flags); 1991 clks[data->clk_id] = clk; 1992 } 1993 1994 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1995 data = &tegra_periph_nodiv_clk_list[i]; 1996 clk = tegra_clk_register_periph_nodiv(data->name, 1997 data->parent_names, data->num_parents, 1998 &data->periph, clk_base, data->offset); 1999 clks[data->clk_id] = clk; 2000 } 2001} 2002 2003static struct tegra_cpu_car_ops tegra114_cpu_car_ops; 2004 2005static const struct of_device_id pmc_match[] __initconst = { 2006 { .compatible = "nvidia,tegra114-pmc" }, 2007 {}, 2008}; 2009 2010static __initdata struct tegra_clk_init_table init_table[] = { 2011 {uarta, pll_p, 408000000, 0}, 2012 {uartb, pll_p, 408000000, 0}, 2013 {uartc, pll_p, 408000000, 0}, 2014 {uartd, pll_p, 408000000, 0}, 2015 {pll_a, clk_max, 564480000, 1}, 2016 {pll_a_out0, clk_max, 11289600, 1}, 2017 {extern1, pll_a_out0, 0, 1}, 2018 {clk_out_1_mux, extern1, 0, 1}, 2019 {clk_out_1, clk_max, 0, 1}, 2020 {i2s0, pll_a_out0, 11289600, 0}, 2021 {i2s1, pll_a_out0, 11289600, 0}, 2022 {i2s2, pll_a_out0, 11289600, 0}, 2023 {i2s3, pll_a_out0, 11289600, 0}, 2024 {i2s4, pll_a_out0, 11289600, 0}, 2025 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 2026}; 2027 2028static void __init tegra114_clock_apply_init_table(void) 2029{ 2030 tegra_init_from_table(init_table, clks, clk_max); 2031} 2032 2033void __init tegra114_clock_init(struct device_node *np) 2034{ 2035 struct device_node *node; 2036 int i; 2037 2038 clk_base = of_iomap(np, 0); 2039 if (!clk_base) { 2040 pr_err("ioremap tegra114 CAR failed\n"); 2041 return; 2042 } 2043 2044 node = of_find_matching_node(NULL, pmc_match); 2045 if (!node) { 2046 pr_err("Failed to find pmc node\n"); 2047 WARN_ON(1); 2048 return; 2049 } 2050 2051 pmc_base = of_iomap(node, 0); 2052 if (!pmc_base) { 2053 pr_err("Can't map pmc registers\n"); 2054 WARN_ON(1); 2055 return; 2056 } 2057 2058 if (tegra114_osc_clk_init(clk_base) < 0) 2059 return; 2060 2061 tegra114_fixed_clk_init(clk_base); 2062 tegra114_pll_init(clk_base, pmc_base); 2063 tegra114_periph_clk_init(clk_base); 2064 tegra114_audio_clk_init(clk_base); 2065 tegra114_pmc_clk_init(pmc_base); 2066 tegra114_super_clk_init(clk_base); 2067 2068 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2069 if (IS_ERR(clks[i])) { 2070 pr_err 2071 ("Tegra114 clk %d: register failed with %ld\n", 2072 i, PTR_ERR(clks[i])); 2073 } 2074 if (!clks[i]) 2075 clks[i] = ERR_PTR(-EINVAL); 2076 } 2077 2078 clk_data.clks = clks; 2079 clk_data.clk_num = ARRAY_SIZE(clks); 2080 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2081 2082 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 2083 2084 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 2085} 2086