clk-tegra114.c revision f67a8d21e63876a79f9f94b734049e789d594c7b
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/export.h> 25#include <linux/clk/tegra.h> 26#include <dt-bindings/clock/tegra114-car.h> 27 28#include "clk.h" 29 30#define RST_DEVICES_L 0x004 31#define RST_DEVICES_H 0x008 32#define RST_DEVICES_U 0x00C 33#define RST_DFLL_DVCO 0x2F4 34#define RST_DEVICES_V 0x358 35#define RST_DEVICES_W 0x35C 36#define RST_DEVICES_X 0x28C 37#define RST_DEVICES_SET_L 0x300 38#define RST_DEVICES_CLR_L 0x304 39#define RST_DEVICES_SET_H 0x308 40#define RST_DEVICES_CLR_H 0x30c 41#define RST_DEVICES_SET_U 0x310 42#define RST_DEVICES_CLR_U 0x314 43#define RST_DEVICES_SET_V 0x430 44#define RST_DEVICES_CLR_V 0x434 45#define RST_DEVICES_SET_W 0x438 46#define RST_DEVICES_CLR_W 0x43c 47#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 48#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 49#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 50#define RST_DEVICES_NUM 5 51 52/* RST_DFLL_DVCO bitfields */ 53#define DVFS_DFLL_RESET_SHIFT 0 54 55/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ 56#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ 57#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ 58#define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ 59#define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ 60#define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ 61#define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ 62 63/* CPU_FINETRIM_R bitfields */ 64#define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */ 65#define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT) 66#define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */ 67#define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT) 68#define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */ 69#define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT) 70#define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */ 71#define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT) 72#define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */ 73#define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT) 74#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 75#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 76 77#define CLK_OUT_ENB_L 0x010 78#define CLK_OUT_ENB_H 0x014 79#define CLK_OUT_ENB_U 0x018 80#define CLK_OUT_ENB_V 0x360 81#define CLK_OUT_ENB_W 0x364 82#define CLK_OUT_ENB_X 0x280 83#define CLK_OUT_ENB_SET_L 0x320 84#define CLK_OUT_ENB_CLR_L 0x324 85#define CLK_OUT_ENB_SET_H 0x328 86#define CLK_OUT_ENB_CLR_H 0x32c 87#define CLK_OUT_ENB_SET_U 0x330 88#define CLK_OUT_ENB_CLR_U 0x334 89#define CLK_OUT_ENB_SET_V 0x440 90#define CLK_OUT_ENB_CLR_V 0x444 91#define CLK_OUT_ENB_SET_W 0x448 92#define CLK_OUT_ENB_CLR_W 0x44c 93#define CLK_OUT_ENB_SET_X 0x284 94#define CLK_OUT_ENB_CLR_X 0x288 95#define CLK_OUT_ENB_NUM 6 96 97#define PLLC_BASE 0x80 98#define PLLC_MISC2 0x88 99#define PLLC_MISC 0x8c 100#define PLLC2_BASE 0x4e8 101#define PLLC2_MISC 0x4ec 102#define PLLC3_BASE 0x4fc 103#define PLLC3_MISC 0x500 104#define PLLM_BASE 0x90 105#define PLLM_MISC 0x9c 106#define PLLP_BASE 0xa0 107#define PLLP_MISC 0xac 108#define PLLX_BASE 0xe0 109#define PLLX_MISC 0xe4 110#define PLLX_MISC2 0x514 111#define PLLX_MISC3 0x518 112#define PLLD_BASE 0xd0 113#define PLLD_MISC 0xdc 114#define PLLD2_BASE 0x4b8 115#define PLLD2_MISC 0x4bc 116#define PLLE_BASE 0xe8 117#define PLLE_MISC 0xec 118#define PLLA_BASE 0xb0 119#define PLLA_MISC 0xbc 120#define PLLU_BASE 0xc0 121#define PLLU_MISC 0xcc 122#define PLLRE_BASE 0x4c4 123#define PLLRE_MISC 0x4c8 124 125#define PLL_MISC_LOCK_ENABLE 18 126#define PLLC_MISC_LOCK_ENABLE 24 127#define PLLDU_MISC_LOCK_ENABLE 22 128#define PLLE_MISC_LOCK_ENABLE 9 129#define PLLRE_MISC_LOCK_ENABLE 30 130 131#define PLLC_IDDQ_BIT 26 132#define PLLX_IDDQ_BIT 3 133#define PLLRE_IDDQ_BIT 16 134 135#define PLL_BASE_LOCK BIT(27) 136#define PLLE_MISC_LOCK BIT(11) 137#define PLLRE_MISC_LOCK BIT(24) 138#define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 139 140#define PLLE_AUX 0x48c 141#define PLLC_OUT 0x84 142#define PLLM_OUT 0x94 143#define PLLP_OUTA 0xa4 144#define PLLP_OUTB 0xa8 145#define PLLA_OUT 0xb4 146 147#define AUDIO_SYNC_CLK_I2S0 0x4a0 148#define AUDIO_SYNC_CLK_I2S1 0x4a4 149#define AUDIO_SYNC_CLK_I2S2 0x4a8 150#define AUDIO_SYNC_CLK_I2S3 0x4ac 151#define AUDIO_SYNC_CLK_I2S4 0x4b0 152#define AUDIO_SYNC_CLK_SPDIF 0x4b4 153 154#define AUDIO_SYNC_DOUBLER 0x49c 155 156#define PMC_CLK_OUT_CNTRL 0x1a8 157#define PMC_DPD_PADS_ORIDE 0x1c 158#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 159#define PMC_CTRL 0 160#define PMC_CTRL_BLINK_ENB 7 161#define PMC_BLINK_TIMER 0x40 162 163#define OSC_CTRL 0x50 164#define OSC_CTRL_OSC_FREQ_SHIFT 28 165#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 166 167#define PLLXC_SW_MAX_P 6 168 169#define CCLKG_BURST_POLICY 0x368 170#define CCLKLP_BURST_POLICY 0x370 171#define SCLK_BURST_POLICY 0x028 172#define SYSTEM_CLK_RATE 0x030 173 174#define UTMIP_PLL_CFG2 0x488 175#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 176#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 177#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 178#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 179#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 180 181#define UTMIP_PLL_CFG1 0x484 182#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 183#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 184#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 185#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 186#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 187#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 188#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 189 190#define UTMIPLL_HW_PWRDN_CFG0 0x52c 191#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 192#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 193#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 194#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 195#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 196#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 197#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 198#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 199 200#define CLK_SOURCE_I2S0 0x1d8 201#define CLK_SOURCE_I2S1 0x100 202#define CLK_SOURCE_I2S2 0x104 203#define CLK_SOURCE_NDFLASH 0x160 204#define CLK_SOURCE_I2S3 0x3bc 205#define CLK_SOURCE_I2S4 0x3c0 206#define CLK_SOURCE_SPDIF_OUT 0x108 207#define CLK_SOURCE_SPDIF_IN 0x10c 208#define CLK_SOURCE_PWM 0x110 209#define CLK_SOURCE_ADX 0x638 210#define CLK_SOURCE_AMX 0x63c 211#define CLK_SOURCE_HDA 0x428 212#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 213#define CLK_SOURCE_SBC1 0x134 214#define CLK_SOURCE_SBC2 0x118 215#define CLK_SOURCE_SBC3 0x11c 216#define CLK_SOURCE_SBC4 0x1b4 217#define CLK_SOURCE_SBC5 0x3c8 218#define CLK_SOURCE_SBC6 0x3cc 219#define CLK_SOURCE_SATA_OOB 0x420 220#define CLK_SOURCE_SATA 0x424 221#define CLK_SOURCE_NDSPEED 0x3f8 222#define CLK_SOURCE_VFIR 0x168 223#define CLK_SOURCE_SDMMC1 0x150 224#define CLK_SOURCE_SDMMC2 0x154 225#define CLK_SOURCE_SDMMC3 0x1bc 226#define CLK_SOURCE_SDMMC4 0x164 227#define CLK_SOURCE_VDE 0x1c8 228#define CLK_SOURCE_CSITE 0x1d4 229#define CLK_SOURCE_LA 0x1f8 230#define CLK_SOURCE_TRACE 0x634 231#define CLK_SOURCE_OWR 0x1cc 232#define CLK_SOURCE_NOR 0x1d0 233#define CLK_SOURCE_MIPI 0x174 234#define CLK_SOURCE_I2C1 0x124 235#define CLK_SOURCE_I2C2 0x198 236#define CLK_SOURCE_I2C3 0x1b8 237#define CLK_SOURCE_I2C4 0x3c4 238#define CLK_SOURCE_I2C5 0x128 239#define CLK_SOURCE_UARTA 0x178 240#define CLK_SOURCE_UARTB 0x17c 241#define CLK_SOURCE_UARTC 0x1a0 242#define CLK_SOURCE_UARTD 0x1c0 243#define CLK_SOURCE_UARTE 0x1c4 244#define CLK_SOURCE_UARTA_DBG 0x178 245#define CLK_SOURCE_UARTB_DBG 0x17c 246#define CLK_SOURCE_UARTC_DBG 0x1a0 247#define CLK_SOURCE_UARTD_DBG 0x1c0 248#define CLK_SOURCE_UARTE_DBG 0x1c4 249#define CLK_SOURCE_3D 0x158 250#define CLK_SOURCE_2D 0x15c 251#define CLK_SOURCE_VI_SENSOR 0x1a8 252#define CLK_SOURCE_VI 0x148 253#define CLK_SOURCE_EPP 0x16c 254#define CLK_SOURCE_MSENC 0x1f0 255#define CLK_SOURCE_TSEC 0x1f4 256#define CLK_SOURCE_HOST1X 0x180 257#define CLK_SOURCE_HDMI 0x18c 258#define CLK_SOURCE_DISP1 0x138 259#define CLK_SOURCE_DISP2 0x13c 260#define CLK_SOURCE_CILAB 0x614 261#define CLK_SOURCE_CILCD 0x618 262#define CLK_SOURCE_CILE 0x61c 263#define CLK_SOURCE_DSIALP 0x620 264#define CLK_SOURCE_DSIBLP 0x624 265#define CLK_SOURCE_TSENSOR 0x3b8 266#define CLK_SOURCE_D_AUDIO 0x3d0 267#define CLK_SOURCE_DAM0 0x3d8 268#define CLK_SOURCE_DAM1 0x3dc 269#define CLK_SOURCE_DAM2 0x3e0 270#define CLK_SOURCE_ACTMON 0x3e8 271#define CLK_SOURCE_EXTERN1 0x3ec 272#define CLK_SOURCE_EXTERN2 0x3f0 273#define CLK_SOURCE_EXTERN3 0x3f4 274#define CLK_SOURCE_I2CSLOW 0x3fc 275#define CLK_SOURCE_SE 0x42c 276#define CLK_SOURCE_MSELECT 0x3b4 277#define CLK_SOURCE_DFLL_REF 0x62c 278#define CLK_SOURCE_DFLL_SOC 0x630 279#define CLK_SOURCE_SOC_THERM 0x644 280#define CLK_SOURCE_XUSB_HOST_SRC 0x600 281#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 282#define CLK_SOURCE_XUSB_FS_SRC 0x608 283#define CLK_SOURCE_XUSB_SS_SRC 0x610 284#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 285#define CLK_SOURCE_EMC 0x19c 286 287/* PLLM override registers */ 288#define PMC_PLLM_WB0_OVERRIDE 0x1dc 289#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 290 291/* Tegra CPU clock and reset control regs */ 292#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 293 294#ifdef CONFIG_PM_SLEEP 295static struct cpu_clk_suspend_context { 296 u32 clk_csite_src; 297 u32 cclkg_burst; 298 u32 cclkg_divider; 299} tegra114_cpu_clk_sctx; 300#endif 301 302static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 303 304static void __iomem *clk_base; 305static void __iomem *pmc_base; 306 307static DEFINE_SPINLOCK(pll_d_lock); 308static DEFINE_SPINLOCK(pll_d2_lock); 309static DEFINE_SPINLOCK(pll_u_lock); 310static DEFINE_SPINLOCK(pll_div_lock); 311static DEFINE_SPINLOCK(pll_re_lock); 312static DEFINE_SPINLOCK(clk_doubler_lock); 313static DEFINE_SPINLOCK(clk_out_lock); 314static DEFINE_SPINLOCK(sysrate_lock); 315 316static struct div_nmp pllxc_nmp = { 317 .divm_shift = 0, 318 .divm_width = 8, 319 .divn_shift = 8, 320 .divn_width = 8, 321 .divp_shift = 20, 322 .divp_width = 4, 323}; 324 325static struct pdiv_map pllxc_p[] = { 326 { .pdiv = 1, .hw_val = 0 }, 327 { .pdiv = 2, .hw_val = 1 }, 328 { .pdiv = 3, .hw_val = 2 }, 329 { .pdiv = 4, .hw_val = 3 }, 330 { .pdiv = 5, .hw_val = 4 }, 331 { .pdiv = 6, .hw_val = 5 }, 332 { .pdiv = 8, .hw_val = 6 }, 333 { .pdiv = 10, .hw_val = 7 }, 334 { .pdiv = 12, .hw_val = 8 }, 335 { .pdiv = 16, .hw_val = 9 }, 336 { .pdiv = 12, .hw_val = 10 }, 337 { .pdiv = 16, .hw_val = 11 }, 338 { .pdiv = 20, .hw_val = 12 }, 339 { .pdiv = 24, .hw_val = 13 }, 340 { .pdiv = 32, .hw_val = 14 }, 341 { .pdiv = 0, .hw_val = 0 }, 342}; 343 344static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 345 { 12000000, 624000000, 104, 0, 2}, 346 { 12000000, 600000000, 100, 0, 2}, 347 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 348 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 349 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 350 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 351 { 0, 0, 0, 0, 0, 0 }, 352}; 353 354static struct tegra_clk_pll_params pll_c_params = { 355 .input_min = 12000000, 356 .input_max = 800000000, 357 .cf_min = 12000000, 358 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 359 .vco_min = 600000000, 360 .vco_max = 1400000000, 361 .base_reg = PLLC_BASE, 362 .misc_reg = PLLC_MISC, 363 .lock_mask = PLL_BASE_LOCK, 364 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 365 .lock_delay = 300, 366 .iddq_reg = PLLC_MISC, 367 .iddq_bit_idx = PLLC_IDDQ_BIT, 368 .max_p = PLLXC_SW_MAX_P, 369 .dyn_ramp_reg = PLLC_MISC2, 370 .stepa_shift = 17, 371 .stepb_shift = 9, 372 .pdiv_tohw = pllxc_p, 373 .div_nmp = &pllxc_nmp, 374}; 375 376static struct div_nmp pllcx_nmp = { 377 .divm_shift = 0, 378 .divm_width = 2, 379 .divn_shift = 8, 380 .divn_width = 8, 381 .divp_shift = 20, 382 .divp_width = 3, 383}; 384 385static struct pdiv_map pllc_p[] = { 386 { .pdiv = 1, .hw_val = 0 }, 387 { .pdiv = 2, .hw_val = 1 }, 388 { .pdiv = 4, .hw_val = 3 }, 389 { .pdiv = 8, .hw_val = 5 }, 390 { .pdiv = 16, .hw_val = 7 }, 391 { .pdiv = 0, .hw_val = 0 }, 392}; 393 394static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 395 {12000000, 600000000, 100, 0, 2}, 396 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 397 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 398 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 399 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 400 {0, 0, 0, 0, 0, 0}, 401}; 402 403static struct tegra_clk_pll_params pll_c2_params = { 404 .input_min = 12000000, 405 .input_max = 48000000, 406 .cf_min = 12000000, 407 .cf_max = 19200000, 408 .vco_min = 600000000, 409 .vco_max = 1200000000, 410 .base_reg = PLLC2_BASE, 411 .misc_reg = PLLC2_MISC, 412 .lock_mask = PLL_BASE_LOCK, 413 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 414 .lock_delay = 300, 415 .pdiv_tohw = pllc_p, 416 .div_nmp = &pllcx_nmp, 417 .max_p = 7, 418 .ext_misc_reg[0] = 0x4f0, 419 .ext_misc_reg[1] = 0x4f4, 420 .ext_misc_reg[2] = 0x4f8, 421}; 422 423static struct tegra_clk_pll_params pll_c3_params = { 424 .input_min = 12000000, 425 .input_max = 48000000, 426 .cf_min = 12000000, 427 .cf_max = 19200000, 428 .vco_min = 600000000, 429 .vco_max = 1200000000, 430 .base_reg = PLLC3_BASE, 431 .misc_reg = PLLC3_MISC, 432 .lock_mask = PLL_BASE_LOCK, 433 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 434 .lock_delay = 300, 435 .pdiv_tohw = pllc_p, 436 .div_nmp = &pllcx_nmp, 437 .max_p = 7, 438 .ext_misc_reg[0] = 0x504, 439 .ext_misc_reg[1] = 0x508, 440 .ext_misc_reg[2] = 0x50c, 441}; 442 443static struct div_nmp pllm_nmp = { 444 .divm_shift = 0, 445 .divm_width = 8, 446 .override_divm_shift = 0, 447 .divn_shift = 8, 448 .divn_width = 8, 449 .override_divn_shift = 8, 450 .divp_shift = 20, 451 .divp_width = 1, 452 .override_divp_shift = 27, 453}; 454 455static struct pdiv_map pllm_p[] = { 456 { .pdiv = 1, .hw_val = 0 }, 457 { .pdiv = 2, .hw_val = 1 }, 458 { .pdiv = 0, .hw_val = 0 }, 459}; 460 461static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 462 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 463 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 464 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 465 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 466 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 467 {0, 0, 0, 0, 0, 0}, 468}; 469 470static struct tegra_clk_pll_params pll_m_params = { 471 .input_min = 12000000, 472 .input_max = 500000000, 473 .cf_min = 12000000, 474 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 475 .vco_min = 400000000, 476 .vco_max = 1066000000, 477 .base_reg = PLLM_BASE, 478 .misc_reg = PLLM_MISC, 479 .lock_mask = PLL_BASE_LOCK, 480 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 481 .lock_delay = 300, 482 .max_p = 2, 483 .pdiv_tohw = pllm_p, 484 .div_nmp = &pllm_nmp, 485 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 486 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 487}; 488 489static struct div_nmp pllp_nmp = { 490 .divm_shift = 0, 491 .divm_width = 5, 492 .divn_shift = 8, 493 .divn_width = 10, 494 .divp_shift = 20, 495 .divp_width = 3, 496}; 497 498static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 499 {12000000, 216000000, 432, 12, 1, 8}, 500 {13000000, 216000000, 432, 13, 1, 8}, 501 {16800000, 216000000, 360, 14, 1, 8}, 502 {19200000, 216000000, 360, 16, 1, 8}, 503 {26000000, 216000000, 432, 26, 1, 8}, 504 {0, 0, 0, 0, 0, 0}, 505}; 506 507static struct tegra_clk_pll_params pll_p_params = { 508 .input_min = 2000000, 509 .input_max = 31000000, 510 .cf_min = 1000000, 511 .cf_max = 6000000, 512 .vco_min = 200000000, 513 .vco_max = 700000000, 514 .base_reg = PLLP_BASE, 515 .misc_reg = PLLP_MISC, 516 .lock_mask = PLL_BASE_LOCK, 517 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 518 .lock_delay = 300, 519 .div_nmp = &pllp_nmp, 520}; 521 522static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 523 {9600000, 282240000, 147, 5, 0, 4}, 524 {9600000, 368640000, 192, 5, 0, 4}, 525 {9600000, 240000000, 200, 8, 0, 8}, 526 527 {28800000, 282240000, 245, 25, 0, 8}, 528 {28800000, 368640000, 320, 25, 0, 8}, 529 {28800000, 240000000, 200, 24, 0, 8}, 530 {0, 0, 0, 0, 0, 0}, 531}; 532 533 534static struct tegra_clk_pll_params pll_a_params = { 535 .input_min = 2000000, 536 .input_max = 31000000, 537 .cf_min = 1000000, 538 .cf_max = 6000000, 539 .vco_min = 200000000, 540 .vco_max = 700000000, 541 .base_reg = PLLA_BASE, 542 .misc_reg = PLLA_MISC, 543 .lock_mask = PLL_BASE_LOCK, 544 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 545 .lock_delay = 300, 546 .div_nmp = &pllp_nmp, 547}; 548 549static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 550 {12000000, 216000000, 864, 12, 2, 12}, 551 {13000000, 216000000, 864, 13, 2, 12}, 552 {16800000, 216000000, 720, 14, 2, 12}, 553 {19200000, 216000000, 720, 16, 2, 12}, 554 {26000000, 216000000, 864, 26, 2, 12}, 555 556 {12000000, 594000000, 594, 12, 0, 12}, 557 {13000000, 594000000, 594, 13, 0, 12}, 558 {16800000, 594000000, 495, 14, 0, 12}, 559 {19200000, 594000000, 495, 16, 0, 12}, 560 {26000000, 594000000, 594, 26, 0, 12}, 561 562 {12000000, 1000000000, 1000, 12, 0, 12}, 563 {13000000, 1000000000, 1000, 13, 0, 12}, 564 {19200000, 1000000000, 625, 12, 0, 12}, 565 {26000000, 1000000000, 1000, 26, 0, 12}, 566 567 {0, 0, 0, 0, 0, 0}, 568}; 569 570static struct tegra_clk_pll_params pll_d_params = { 571 .input_min = 2000000, 572 .input_max = 40000000, 573 .cf_min = 1000000, 574 .cf_max = 6000000, 575 .vco_min = 500000000, 576 .vco_max = 1000000000, 577 .base_reg = PLLD_BASE, 578 .misc_reg = PLLD_MISC, 579 .lock_mask = PLL_BASE_LOCK, 580 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 581 .lock_delay = 1000, 582 .div_nmp = &pllp_nmp, 583}; 584 585static struct tegra_clk_pll_params pll_d2_params = { 586 .input_min = 2000000, 587 .input_max = 40000000, 588 .cf_min = 1000000, 589 .cf_max = 6000000, 590 .vco_min = 500000000, 591 .vco_max = 1000000000, 592 .base_reg = PLLD2_BASE, 593 .misc_reg = PLLD2_MISC, 594 .lock_mask = PLL_BASE_LOCK, 595 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 596 .lock_delay = 1000, 597 .div_nmp = &pllp_nmp, 598}; 599 600static struct pdiv_map pllu_p[] = { 601 { .pdiv = 1, .hw_val = 1 }, 602 { .pdiv = 2, .hw_val = 0 }, 603 { .pdiv = 0, .hw_val = 0 }, 604}; 605 606static struct div_nmp pllu_nmp = { 607 .divm_shift = 0, 608 .divm_width = 5, 609 .divn_shift = 8, 610 .divn_width = 10, 611 .divp_shift = 20, 612 .divp_width = 1, 613}; 614 615static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 616 {12000000, 480000000, 960, 12, 0, 12}, 617 {13000000, 480000000, 960, 13, 0, 12}, 618 {16800000, 480000000, 400, 7, 0, 5}, 619 {19200000, 480000000, 200, 4, 0, 3}, 620 {26000000, 480000000, 960, 26, 0, 12}, 621 {0, 0, 0, 0, 0, 0}, 622}; 623 624static struct tegra_clk_pll_params pll_u_params = { 625 .input_min = 2000000, 626 .input_max = 40000000, 627 .cf_min = 1000000, 628 .cf_max = 6000000, 629 .vco_min = 480000000, 630 .vco_max = 960000000, 631 .base_reg = PLLU_BASE, 632 .misc_reg = PLLU_MISC, 633 .lock_mask = PLL_BASE_LOCK, 634 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 635 .lock_delay = 1000, 636 .pdiv_tohw = pllu_p, 637 .div_nmp = &pllu_nmp, 638}; 639 640static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 641 /* 1 GHz */ 642 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 643 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 644 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 645 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 646 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 647 648 {0, 0, 0, 0, 0, 0}, 649}; 650 651static struct tegra_clk_pll_params pll_x_params = { 652 .input_min = 12000000, 653 .input_max = 800000000, 654 .cf_min = 12000000, 655 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 656 .vco_min = 700000000, 657 .vco_max = 2400000000U, 658 .base_reg = PLLX_BASE, 659 .misc_reg = PLLX_MISC, 660 .lock_mask = PLL_BASE_LOCK, 661 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 662 .lock_delay = 300, 663 .iddq_reg = PLLX_MISC3, 664 .iddq_bit_idx = PLLX_IDDQ_BIT, 665 .max_p = PLLXC_SW_MAX_P, 666 .dyn_ramp_reg = PLLX_MISC2, 667 .stepa_shift = 16, 668 .stepb_shift = 24, 669 .pdiv_tohw = pllxc_p, 670 .div_nmp = &pllxc_nmp, 671}; 672 673static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 674 /* PLLE special case: use cpcon field to store cml divider value */ 675 {336000000, 100000000, 100, 21, 16, 11}, 676 {312000000, 100000000, 200, 26, 24, 13}, 677 {0, 0, 0, 0, 0, 0}, 678}; 679 680static struct div_nmp plle_nmp = { 681 .divm_shift = 0, 682 .divm_width = 8, 683 .divn_shift = 8, 684 .divn_width = 8, 685 .divp_shift = 24, 686 .divp_width = 4, 687}; 688 689static struct tegra_clk_pll_params pll_e_params = { 690 .input_min = 12000000, 691 .input_max = 1000000000, 692 .cf_min = 12000000, 693 .cf_max = 75000000, 694 .vco_min = 1600000000, 695 .vco_max = 2400000000U, 696 .base_reg = PLLE_BASE, 697 .misc_reg = PLLE_MISC, 698 .aux_reg = PLLE_AUX, 699 .lock_mask = PLLE_MISC_LOCK, 700 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 701 .lock_delay = 300, 702 .div_nmp = &plle_nmp, 703}; 704 705static struct div_nmp pllre_nmp = { 706 .divm_shift = 0, 707 .divm_width = 8, 708 .divn_shift = 8, 709 .divn_width = 8, 710 .divp_shift = 16, 711 .divp_width = 4, 712}; 713 714static struct tegra_clk_pll_params pll_re_vco_params = { 715 .input_min = 12000000, 716 .input_max = 1000000000, 717 .cf_min = 12000000, 718 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 719 .vco_min = 300000000, 720 .vco_max = 600000000, 721 .base_reg = PLLRE_BASE, 722 .misc_reg = PLLRE_MISC, 723 .lock_mask = PLLRE_MISC_LOCK, 724 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 725 .lock_delay = 300, 726 .iddq_reg = PLLRE_MISC, 727 .iddq_bit_idx = PLLRE_IDDQ_BIT, 728 .div_nmp = &pllre_nmp, 729}; 730 731/* Peripheral clock registers */ 732 733static struct tegra_clk_periph_regs periph_l_regs = { 734 .enb_reg = CLK_OUT_ENB_L, 735 .enb_set_reg = CLK_OUT_ENB_SET_L, 736 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 737 .rst_reg = RST_DEVICES_L, 738 .rst_set_reg = RST_DEVICES_SET_L, 739 .rst_clr_reg = RST_DEVICES_CLR_L, 740}; 741 742static struct tegra_clk_periph_regs periph_h_regs = { 743 .enb_reg = CLK_OUT_ENB_H, 744 .enb_set_reg = CLK_OUT_ENB_SET_H, 745 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 746 .rst_reg = RST_DEVICES_H, 747 .rst_set_reg = RST_DEVICES_SET_H, 748 .rst_clr_reg = RST_DEVICES_CLR_H, 749}; 750 751static struct tegra_clk_periph_regs periph_u_regs = { 752 .enb_reg = CLK_OUT_ENB_U, 753 .enb_set_reg = CLK_OUT_ENB_SET_U, 754 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 755 .rst_reg = RST_DEVICES_U, 756 .rst_set_reg = RST_DEVICES_SET_U, 757 .rst_clr_reg = RST_DEVICES_CLR_U, 758}; 759 760static struct tegra_clk_periph_regs periph_v_regs = { 761 .enb_reg = CLK_OUT_ENB_V, 762 .enb_set_reg = CLK_OUT_ENB_SET_V, 763 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 764 .rst_reg = RST_DEVICES_V, 765 .rst_set_reg = RST_DEVICES_SET_V, 766 .rst_clr_reg = RST_DEVICES_CLR_V, 767}; 768 769static struct tegra_clk_periph_regs periph_w_regs = { 770 .enb_reg = CLK_OUT_ENB_W, 771 .enb_set_reg = CLK_OUT_ENB_SET_W, 772 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 773 .rst_reg = RST_DEVICES_W, 774 .rst_set_reg = RST_DEVICES_SET_W, 775 .rst_clr_reg = RST_DEVICES_CLR_W, 776}; 777 778/* possible OSC frequencies in Hz */ 779static unsigned long tegra114_input_freq[] = { 780 [0] = 13000000, 781 [1] = 16800000, 782 [4] = 19200000, 783 [5] = 38400000, 784 [8] = 12000000, 785 [9] = 48000000, 786 [12] = 260000000, 787}; 788 789#define MASK(x) (BIT(x) - 1) 790 791#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 792 _clk_num, _regs, _gate_flags, _clk_id) \ 793 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 794 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 795 _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\ 796 _clk_id, _parents##_idx, 0) 797 798#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 799 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 800 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 801 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 802 _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\ 803 _clk_id, _parents##_idx, flags) 804 805#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 806 _clk_num, _regs, _gate_flags, _clk_id) \ 807 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 808 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 809 _regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\ 810 _clk_id, _parents##_idx, 0) 811 812#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 813 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 814 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 815 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 816 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 817 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 818 _parents##_idx, flags) 819 820#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 821 _clk_num, _regs, _gate_flags, _clk_id) \ 822 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 823 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 824 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 825 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 826 _parents##_idx, 0) 827 828#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 829 _clk_num, _regs, _clk_id) \ 830 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 831 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \ 832 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 833 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 834 835#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 836 _clk_num, _regs, _clk_id) \ 837 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 838 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ 839 _regs, _clk_num, periph_clk_enb_refcnt, 0, _clk_id,\ 840 _parents##_idx, 0) 841 842#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 843 _mux_shift, _mux_mask, _clk_num, _regs, \ 844 _gate_flags, _clk_id) \ 845 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 846 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 847 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 848 _clk_id, _parents##_idx, 0) 849 850#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 851 _clk_num, _regs, _gate_flags, _clk_id) \ 852 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 853 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 854 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 855 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 856 _parents##_idx, 0) 857 858#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 859 _regs, _gate_flags, _clk_id) \ 860 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 861 _offset, 16, 0xE01F, 0, 0, 8, 1, \ 862 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 863 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 864 mux_d_audio_clk_idx, 0) 865 866struct utmi_clk_param { 867 /* Oscillator Frequency in KHz */ 868 u32 osc_frequency; 869 /* UTMIP PLL Enable Delay Count */ 870 u8 enable_delay_count; 871 /* UTMIP PLL Stable count */ 872 u8 stable_count; 873 /* UTMIP PLL Active delay count */ 874 u8 active_delay_count; 875 /* UTMIP PLL Xtal frequency count */ 876 u8 xtal_freq_count; 877}; 878 879static const struct utmi_clk_param utmi_parameters[] = { 880 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 881 .stable_count = 0x33, .active_delay_count = 0x05, 882 .xtal_freq_count = 0x7F}, 883 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 884 .stable_count = 0x4B, .active_delay_count = 0x06, 885 .xtal_freq_count = 0xBB}, 886 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 887 .stable_count = 0x2F, .active_delay_count = 0x04, 888 .xtal_freq_count = 0x76}, 889 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 890 .stable_count = 0x66, .active_delay_count = 0x09, 891 .xtal_freq_count = 0xFE}, 892 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 893 .stable_count = 0x41, .active_delay_count = 0x0A, 894 .xtal_freq_count = 0xA4}, 895}; 896 897/* peripheral mux definitions */ 898 899#define MUX_I2S_SPDIF(_id) \ 900static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 901 #_id, "pll_p",\ 902 "clk_m"}; 903MUX_I2S_SPDIF(audio0) 904MUX_I2S_SPDIF(audio1) 905MUX_I2S_SPDIF(audio2) 906MUX_I2S_SPDIF(audio3) 907MUX_I2S_SPDIF(audio4) 908MUX_I2S_SPDIF(audio) 909 910#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 911#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 912#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 913#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 914#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 915#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 916 917static const char *mux_pllp_pllc_pllm_clkm[] = { 918 "pll_p", "pll_c", "pll_m", "clk_m" 919}; 920#define mux_pllp_pllc_pllm_clkm_idx NULL 921 922static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 923#define mux_pllp_pllc_pllm_idx NULL 924 925static const char *mux_pllp_pllc_clk32_clkm[] = { 926 "pll_p", "pll_c", "clk_32k", "clk_m" 927}; 928#define mux_pllp_pllc_clk32_clkm_idx NULL 929 930static const char *mux_plla_pllc_pllp_clkm[] = { 931 "pll_a_out0", "pll_c", "pll_p", "clk_m" 932}; 933#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 934 935static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 936 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 937}; 938static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 939 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 940}; 941 942static const char *mux_pllp_clkm[] = { 943 "pll_p", "clk_m" 944}; 945static u32 mux_pllp_clkm_idx[] = { 946 [0] = 0, [1] = 3, 947}; 948 949static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 950 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 951}; 952#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 953 954static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 955 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 956 "pll_d2_out0", "clk_m" 957}; 958#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 959 960static const char *mux_pllm_pllc_pllp_plla[] = { 961 "pll_m", "pll_c", "pll_p", "pll_a_out0" 962}; 963#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 964 965static const char *mux_pllp_pllc_clkm[] = { 966 "pll_p", "pll_c", "pll_m" 967}; 968static u32 mux_pllp_pllc_clkm_idx[] = { 969 [0] = 0, [1] = 1, [2] = 3, 970}; 971 972static const char *mux_pllp_pllc_clkm_clk32[] = { 973 "pll_p", "pll_c", "clk_m", "clk_32k" 974}; 975#define mux_pllp_pllc_clkm_clk32_idx NULL 976 977static const char *mux_plla_clk32_pllp_clkm_plle[] = { 978 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 979}; 980#define mux_plla_clk32_pllp_clkm_plle_idx NULL 981 982static const char *mux_clkm_pllp_pllc_pllre[] = { 983 "clk_m", "pll_p", "pll_c", "pll_re_out" 984}; 985static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 986 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 987}; 988 989static const char *mux_clkm_48M_pllp_480M[] = { 990 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 991}; 992#define mux_clkm_48M_pllp_480M_idx NULL 993 994static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 995 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 996}; 997static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 998 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 999}; 1000 1001static const char *mux_plld_out0_plld2_out0[] = { 1002 "pll_d_out0", "pll_d2_out0", 1003}; 1004#define mux_plld_out0_plld2_out0_idx NULL 1005 1006static const char *mux_d_audio_clk[] = { 1007 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 1008 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1009}; 1010static u32 mux_d_audio_clk_idx[] = { 1011 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 1012 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 1013}; 1014 1015static const char *mux_pllmcp_clkm[] = { 1016 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 1017}; 1018 1019static const struct clk_div_table pll_re_div_table[] = { 1020 { .val = 0, .div = 1 }, 1021 { .val = 1, .div = 2 }, 1022 { .val = 2, .div = 3 }, 1023 { .val = 3, .div = 4 }, 1024 { .val = 4, .div = 5 }, 1025 { .val = 5, .div = 6 }, 1026 { .val = 0, .div = 0 }, 1027}; 1028 1029static struct clk *clks[TEGRA114_CLK_CLK_MAX]; 1030static struct clk_onecell_data clk_data; 1031 1032static unsigned long osc_freq; 1033static unsigned long pll_ref_freq; 1034 1035static int __init tegra114_osc_clk_init(void __iomem *clk_base) 1036{ 1037 struct clk *clk; 1038 u32 val, pll_ref_div; 1039 1040 val = readl_relaxed(clk_base + OSC_CTRL); 1041 1042 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; 1043 if (!osc_freq) { 1044 WARN_ON(1); 1045 return -EINVAL; 1046 } 1047 1048 /* clk_m */ 1049 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1050 osc_freq); 1051 clk_register_clkdev(clk, "clk_m", NULL); 1052 clks[TEGRA114_CLK_CLK_M] = clk; 1053 1054 /* pll_ref */ 1055 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 1056 pll_ref_div = 1 << val; 1057 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1058 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1059 clk_register_clkdev(clk, "pll_ref", NULL); 1060 clks[TEGRA114_CLK_PLL_REF] = clk; 1061 1062 pll_ref_freq = osc_freq / pll_ref_div; 1063 1064 return 0; 1065} 1066 1067static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 1068{ 1069 struct clk *clk; 1070 1071 /* clk_32k */ 1072 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1073 32768); 1074 clk_register_clkdev(clk, "clk_32k", NULL); 1075 clks[TEGRA114_CLK_CLK_32K] = clk; 1076 1077 /* clk_m_div2 */ 1078 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1079 CLK_SET_RATE_PARENT, 1, 2); 1080 clk_register_clkdev(clk, "clk_m_div2", NULL); 1081 clks[TEGRA114_CLK_CLK_M_DIV2] = clk; 1082 1083 /* clk_m_div4 */ 1084 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1085 CLK_SET_RATE_PARENT, 1, 4); 1086 clk_register_clkdev(clk, "clk_m_div4", NULL); 1087 clks[TEGRA114_CLK_CLK_M_DIV4] = clk; 1088 1089} 1090 1091static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 1092{ 1093 u32 reg; 1094 int i; 1095 1096 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1097 if (osc_freq == utmi_parameters[i].osc_frequency) 1098 break; 1099 } 1100 1101 if (i >= ARRAY_SIZE(utmi_parameters)) { 1102 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1103 osc_freq); 1104 return; 1105 } 1106 1107 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1108 1109 /* Program UTMIP PLL stable and active counts */ 1110 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1111 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1112 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1113 1114 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1115 1116 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1117 active_delay_count); 1118 1119 /* Remove power downs from UTMIP PLL control bits */ 1120 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1121 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1122 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1123 1124 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1125 1126 /* Program UTMIP PLL delay and oscillator frequency counts */ 1127 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1128 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1129 1130 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1131 enable_delay_count); 1132 1133 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1134 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1135 xtal_freq_count); 1136 1137 /* Remove power downs from UTMIP PLL control bits */ 1138 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1139 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1140 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1141 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1142 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1143 1144 /* Setup HW control of UTMIPLL */ 1145 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1146 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1147 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1148 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1149 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1150 1151 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1152 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1153 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1154 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1155 1156 udelay(1); 1157 1158 /* Setup SW override of UTMIPLL assuming USB2.0 1159 ports are assigned to USB2 */ 1160 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1161 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1162 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1163 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1164 1165 udelay(1); 1166 1167 /* Enable HW control UTMIPLL */ 1168 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1169 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1170 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1171} 1172 1173static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params) 1174{ 1175 pll_params->vco_min = 1176 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq; 1177} 1178 1179static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1180 void __iomem *clk_base) 1181{ 1182 u32 val; 1183 u32 step_a, step_b; 1184 1185 switch (pll_ref_freq) { 1186 case 12000000: 1187 case 13000000: 1188 case 26000000: 1189 step_a = 0x2B; 1190 step_b = 0x0B; 1191 break; 1192 case 16800000: 1193 step_a = 0x1A; 1194 step_b = 0x09; 1195 break; 1196 case 19200000: 1197 step_a = 0x12; 1198 step_b = 0x08; 1199 break; 1200 default: 1201 pr_err("%s: Unexpected reference rate %lu\n", 1202 __func__, pll_ref_freq); 1203 WARN_ON(1); 1204 return -EINVAL; 1205 } 1206 1207 val = step_a << pll_params->stepa_shift; 1208 val |= step_b << pll_params->stepb_shift; 1209 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1210 1211 return 0; 1212} 1213 1214static void __init _init_iddq(struct tegra_clk_pll_params *pll_params, 1215 void __iomem *clk_base) 1216{ 1217 u32 val, val_iddq; 1218 1219 val = readl_relaxed(clk_base + pll_params->base_reg); 1220 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1221 1222 if (val & BIT(30)) 1223 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1224 else { 1225 val_iddq |= BIT(pll_params->iddq_bit_idx); 1226 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1227 } 1228} 1229 1230static void __init tegra114_pll_init(void __iomem *clk_base, 1231 void __iomem *pmc) 1232{ 1233 u32 val; 1234 struct clk *clk; 1235 1236 /* PLLC */ 1237 _clip_vco_min(&pll_c_params); 1238 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1239 _init_iddq(&pll_c_params, clk_base); 1240 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1241 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1242 pll_c_freq_table, NULL); 1243 clk_register_clkdev(clk, "pll_c", NULL); 1244 clks[TEGRA114_CLK_PLL_C] = clk; 1245 1246 /* PLLC_OUT1 */ 1247 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1248 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1249 8, 8, 1, NULL); 1250 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1251 clk_base + PLLC_OUT, 1, 0, 1252 CLK_SET_RATE_PARENT, 0, NULL); 1253 clk_register_clkdev(clk, "pll_c_out1", NULL); 1254 clks[TEGRA114_CLK_PLL_C_OUT1] = clk; 1255 } 1256 1257 /* PLLC2 */ 1258 _clip_vco_min(&pll_c2_params); 1259 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1260 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1261 pll_cx_freq_table, NULL); 1262 clk_register_clkdev(clk, "pll_c2", NULL); 1263 clks[TEGRA114_CLK_PLL_C2] = clk; 1264 1265 /* PLLC3 */ 1266 _clip_vco_min(&pll_c3_params); 1267 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1268 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1269 pll_cx_freq_table, NULL); 1270 clk_register_clkdev(clk, "pll_c3", NULL); 1271 clks[TEGRA114_CLK_PLL_C3] = clk; 1272 1273 /* PLLP */ 1274 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, 1275 408000000, &pll_p_params, 1276 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 1277 pll_p_freq_table, NULL); 1278 clk_register_clkdev(clk, "pll_p", NULL); 1279 clks[TEGRA114_CLK_PLL_P] = clk; 1280 1281 /* PLLP_OUT1 */ 1282 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 1283 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1284 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1285 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 1286 clk_base + PLLP_OUTA, 1, 0, 1287 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1288 &pll_div_lock); 1289 clk_register_clkdev(clk, "pll_p_out1", NULL); 1290 clks[TEGRA114_CLK_PLL_P_OUT1] = clk; 1291 1292 /* PLLP_OUT2 */ 1293 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 1294 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1295 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, 1296 8, 1, &pll_div_lock); 1297 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 1298 clk_base + PLLP_OUTA, 17, 16, 1299 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1300 &pll_div_lock); 1301 clk_register_clkdev(clk, "pll_p_out2", NULL); 1302 clks[TEGRA114_CLK_PLL_P_OUT2] = clk; 1303 1304 /* PLLP_OUT3 */ 1305 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 1306 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1307 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1308 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 1309 clk_base + PLLP_OUTB, 1, 0, 1310 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1311 &pll_div_lock); 1312 clk_register_clkdev(clk, "pll_p_out3", NULL); 1313 clks[TEGRA114_CLK_PLL_P_OUT3] = clk; 1314 1315 /* PLLP_OUT4 */ 1316 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 1317 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1318 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1319 &pll_div_lock); 1320 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 1321 clk_base + PLLP_OUTB, 17, 16, 1322 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1323 &pll_div_lock); 1324 clk_register_clkdev(clk, "pll_p_out4", NULL); 1325 clks[TEGRA114_CLK_PLL_P_OUT4] = clk; 1326 1327 /* PLLM */ 1328 _clip_vco_min(&pll_m_params); 1329 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1330 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1331 &pll_m_params, TEGRA_PLL_USE_LOCK, 1332 pll_m_freq_table, NULL); 1333 clk_register_clkdev(clk, "pll_m", NULL); 1334 clks[TEGRA114_CLK_PLL_M] = clk; 1335 1336 /* PLLM_OUT1 */ 1337 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1338 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1339 8, 8, 1, NULL); 1340 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1341 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1342 CLK_SET_RATE_PARENT, 0, NULL); 1343 clk_register_clkdev(clk, "pll_m_out1", NULL); 1344 clks[TEGRA114_CLK_PLL_M_OUT1] = clk; 1345 1346 /* PLLM_UD */ 1347 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1348 CLK_SET_RATE_PARENT, 1, 1); 1349 1350 /* PLLX */ 1351 _clip_vco_min(&pll_x_params); 1352 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) { 1353 _init_iddq(&pll_x_params, clk_base); 1354 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, 1355 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params, 1356 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL); 1357 clk_register_clkdev(clk, "pll_x", NULL); 1358 clks[TEGRA114_CLK_PLL_X] = clk; 1359 } 1360 1361 /* PLLX_OUT0 */ 1362 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 1363 CLK_SET_RATE_PARENT, 1, 2); 1364 clk_register_clkdev(clk, "pll_x_out0", NULL); 1365 clks[TEGRA114_CLK_PLL_X_OUT0] = clk; 1366 1367 /* PLLU */ 1368 val = readl(clk_base + pll_u_params.base_reg); 1369 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1370 writel(val, clk_base + pll_u_params.base_reg); 1371 1372 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1373 0, &pll_u_params, TEGRA_PLLU | 1374 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1375 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock); 1376 clk_register_clkdev(clk, "pll_u", NULL); 1377 clks[TEGRA114_CLK_PLL_U] = clk; 1378 1379 tegra114_utmi_param_configure(clk_base); 1380 1381 /* PLLU_480M */ 1382 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1383 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1384 22, 0, &pll_u_lock); 1385 clk_register_clkdev(clk, "pll_u_480M", NULL); 1386 clks[TEGRA114_CLK_PLL_U_480M] = clk; 1387 1388 /* PLLU_60M */ 1389 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1390 CLK_SET_RATE_PARENT, 1, 8); 1391 clk_register_clkdev(clk, "pll_u_60M", NULL); 1392 clks[TEGRA114_CLK_PLL_U_60M] = clk; 1393 1394 /* PLLU_48M */ 1395 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1396 CLK_SET_RATE_PARENT, 1, 10); 1397 clk_register_clkdev(clk, "pll_u_48M", NULL); 1398 clks[TEGRA114_CLK_PLL_U_48M] = clk; 1399 1400 /* PLLU_12M */ 1401 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1402 CLK_SET_RATE_PARENT, 1, 40); 1403 clk_register_clkdev(clk, "pll_u_12M", NULL); 1404 clks[TEGRA114_CLK_PLL_U_12M] = clk; 1405 1406 /* PLLD */ 1407 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1408 0, &pll_d_params, 1409 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1410 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock); 1411 clk_register_clkdev(clk, "pll_d", NULL); 1412 clks[TEGRA114_CLK_PLL_D] = clk; 1413 1414 /* PLLD_OUT0 */ 1415 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1416 CLK_SET_RATE_PARENT, 1, 2); 1417 clk_register_clkdev(clk, "pll_d_out0", NULL); 1418 clks[TEGRA114_CLK_PLL_D_OUT0] = clk; 1419 1420 /* PLLD2 */ 1421 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1422 0, &pll_d2_params, 1423 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1424 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock); 1425 clk_register_clkdev(clk, "pll_d2", NULL); 1426 clks[TEGRA114_CLK_PLL_D2] = clk; 1427 1428 /* PLLD2_OUT0 */ 1429 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1430 CLK_SET_RATE_PARENT, 1, 2); 1431 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1432 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk; 1433 1434 /* PLLA */ 1435 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, 1436 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1437 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1438 clk_register_clkdev(clk, "pll_a", NULL); 1439 clks[TEGRA114_CLK_PLL_A] = clk; 1440 1441 /* PLLA_OUT0 */ 1442 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1443 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1444 8, 8, 1, NULL); 1445 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1446 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1447 CLK_SET_RATE_PARENT, 0, NULL); 1448 clk_register_clkdev(clk, "pll_a_out0", NULL); 1449 clks[TEGRA114_CLK_PLL_A_OUT0] = clk; 1450 1451 /* PLLRE */ 1452 _clip_vco_min(&pll_re_vco_params); 1453 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1454 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1455 NULL, &pll_re_lock, pll_ref_freq); 1456 clk_register_clkdev(clk, "pll_re_vco", NULL); 1457 clks[TEGRA114_CLK_PLL_RE_VCO] = clk; 1458 1459 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1460 clk_base + PLLRE_BASE, 16, 4, 0, 1461 pll_re_div_table, &pll_re_lock); 1462 clk_register_clkdev(clk, "pll_re_out", NULL); 1463 clks[TEGRA114_CLK_PLL_RE_OUT] = clk; 1464 1465 /* PLLE */ 1466 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1467 clk_base, 0, 100000000, &pll_e_params, 1468 pll_e_freq_table, NULL); 1469 clk_register_clkdev(clk, "pll_e_out0", NULL); 1470 clks[TEGRA114_CLK_PLL_E_OUT0] = clk; 1471} 1472 1473static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1474 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1475}; 1476 1477static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1478 "clk_m_div4", "extern1", 1479}; 1480 1481static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1482 "clk_m_div4", "extern2", 1483}; 1484 1485static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1486 "clk_m_div4", "extern3", 1487}; 1488 1489static void __init tegra114_audio_clk_init(void __iomem *clk_base) 1490{ 1491 struct clk *clk; 1492 1493 /* spdif_in_sync */ 1494 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1495 24000000); 1496 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1497 clks[TEGRA114_CLK_SPDIF_IN_SYNC] = clk; 1498 1499 /* i2s0_sync */ 1500 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1501 clk_register_clkdev(clk, "i2s0_sync", NULL); 1502 clks[TEGRA114_CLK_I2S0_SYNC] = clk; 1503 1504 /* i2s1_sync */ 1505 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1506 clk_register_clkdev(clk, "i2s1_sync", NULL); 1507 clks[TEGRA114_CLK_I2S1_SYNC] = clk; 1508 1509 /* i2s2_sync */ 1510 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1511 clk_register_clkdev(clk, "i2s2_sync", NULL); 1512 clks[TEGRA114_CLK_I2S2_SYNC] = clk; 1513 1514 /* i2s3_sync */ 1515 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1516 clk_register_clkdev(clk, "i2s3_sync", NULL); 1517 clks[TEGRA114_CLK_I2S3_SYNC] = clk; 1518 1519 /* i2s4_sync */ 1520 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1521 clk_register_clkdev(clk, "i2s4_sync", NULL); 1522 clks[TEGRA114_CLK_I2S4_SYNC] = clk; 1523 1524 /* vimclk_sync */ 1525 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1526 clk_register_clkdev(clk, "vimclk_sync", NULL); 1527 clks[TEGRA114_CLK_VIMCLK_SYNC] = clk; 1528 1529 /* audio0 */ 1530 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1531 ARRAY_SIZE(mux_audio_sync_clk), 1532 CLK_SET_RATE_NO_REPARENT, 1533 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1534 NULL); 1535 clks[TEGRA114_CLK_AUDIO0_MUX] = clk; 1536 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1537 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1538 CLK_GATE_SET_TO_DISABLE, NULL); 1539 clk_register_clkdev(clk, "audio0", NULL); 1540 clks[TEGRA114_CLK_AUDIO0] = clk; 1541 1542 /* audio1 */ 1543 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1544 ARRAY_SIZE(mux_audio_sync_clk), 1545 CLK_SET_RATE_NO_REPARENT, 1546 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1547 NULL); 1548 clks[TEGRA114_CLK_AUDIO1_MUX] = clk; 1549 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1550 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1551 CLK_GATE_SET_TO_DISABLE, NULL); 1552 clk_register_clkdev(clk, "audio1", NULL); 1553 clks[TEGRA114_CLK_AUDIO1] = clk; 1554 1555 /* audio2 */ 1556 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1557 ARRAY_SIZE(mux_audio_sync_clk), 1558 CLK_SET_RATE_NO_REPARENT, 1559 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1560 NULL); 1561 clks[TEGRA114_CLK_AUDIO2_MUX] = clk; 1562 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1563 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1564 CLK_GATE_SET_TO_DISABLE, NULL); 1565 clk_register_clkdev(clk, "audio2", NULL); 1566 clks[TEGRA114_CLK_AUDIO2] = clk; 1567 1568 /* audio3 */ 1569 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1570 ARRAY_SIZE(mux_audio_sync_clk), 1571 CLK_SET_RATE_NO_REPARENT, 1572 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1573 NULL); 1574 clks[TEGRA114_CLK_AUDIO3_MUX] = clk; 1575 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1576 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1577 CLK_GATE_SET_TO_DISABLE, NULL); 1578 clk_register_clkdev(clk, "audio3", NULL); 1579 clks[TEGRA114_CLK_AUDIO3] = clk; 1580 1581 /* audio4 */ 1582 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1583 ARRAY_SIZE(mux_audio_sync_clk), 1584 CLK_SET_RATE_NO_REPARENT, 1585 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1586 NULL); 1587 clks[TEGRA114_CLK_AUDIO4_MUX] = clk; 1588 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1589 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1590 CLK_GATE_SET_TO_DISABLE, NULL); 1591 clk_register_clkdev(clk, "audio4", NULL); 1592 clks[TEGRA114_CLK_AUDIO4] = clk; 1593 1594 /* spdif */ 1595 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1596 ARRAY_SIZE(mux_audio_sync_clk), 1597 CLK_SET_RATE_NO_REPARENT, 1598 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1599 NULL); 1600 clks[TEGRA114_CLK_SPDIF_MUX] = clk; 1601 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1602 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1603 CLK_GATE_SET_TO_DISABLE, NULL); 1604 clk_register_clkdev(clk, "spdif", NULL); 1605 clks[TEGRA114_CLK_SPDIF] = clk; 1606 1607 /* audio0_2x */ 1608 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1609 CLK_SET_RATE_PARENT, 2, 1); 1610 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1611 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 1612 0, &clk_doubler_lock); 1613 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1614 TEGRA_PERIPH_NO_RESET, clk_base, 1615 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1616 periph_clk_enb_refcnt); 1617 clk_register_clkdev(clk, "audio0_2x", NULL); 1618 clks[TEGRA114_CLK_AUDIO0_2X] = clk; 1619 1620 /* audio1_2x */ 1621 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1622 CLK_SET_RATE_PARENT, 2, 1); 1623 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1624 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 1625 0, &clk_doubler_lock); 1626 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1627 TEGRA_PERIPH_NO_RESET, clk_base, 1628 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1629 periph_clk_enb_refcnt); 1630 clk_register_clkdev(clk, "audio1_2x", NULL); 1631 clks[TEGRA114_CLK_AUDIO1_2X] = clk; 1632 1633 /* audio2_2x */ 1634 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1635 CLK_SET_RATE_PARENT, 2, 1); 1636 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1637 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 1638 0, &clk_doubler_lock); 1639 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1640 TEGRA_PERIPH_NO_RESET, clk_base, 1641 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1642 periph_clk_enb_refcnt); 1643 clk_register_clkdev(clk, "audio2_2x", NULL); 1644 clks[TEGRA114_CLK_AUDIO2_2X] = clk; 1645 1646 /* audio3_2x */ 1647 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1648 CLK_SET_RATE_PARENT, 2, 1); 1649 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1650 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 1651 0, &clk_doubler_lock); 1652 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1653 TEGRA_PERIPH_NO_RESET, clk_base, 1654 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1655 periph_clk_enb_refcnt); 1656 clk_register_clkdev(clk, "audio3_2x", NULL); 1657 clks[TEGRA114_CLK_AUDIO3_2X] = clk; 1658 1659 /* audio4_2x */ 1660 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1661 CLK_SET_RATE_PARENT, 2, 1); 1662 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1663 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 1664 0, &clk_doubler_lock); 1665 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1666 TEGRA_PERIPH_NO_RESET, clk_base, 1667 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1668 periph_clk_enb_refcnt); 1669 clk_register_clkdev(clk, "audio4_2x", NULL); 1670 clks[TEGRA114_CLK_AUDIO4_2X] = clk; 1671 1672 /* spdif_2x */ 1673 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1674 CLK_SET_RATE_PARENT, 2, 1); 1675 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1676 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 1677 0, &clk_doubler_lock); 1678 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1679 TEGRA_PERIPH_NO_RESET, clk_base, 1680 CLK_SET_RATE_PARENT, 118, 1681 &periph_v_regs, periph_clk_enb_refcnt); 1682 clk_register_clkdev(clk, "spdif_2x", NULL); 1683 clks[TEGRA114_CLK_SPDIF_2X] = clk; 1684} 1685 1686static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1687{ 1688 struct clk *clk; 1689 1690 /* clk_out_1 */ 1691 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1692 ARRAY_SIZE(clk_out1_parents), 1693 CLK_SET_RATE_NO_REPARENT, 1694 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1695 &clk_out_lock); 1696 clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk; 1697 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1698 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1699 &clk_out_lock); 1700 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1701 clks[TEGRA114_CLK_CLK_OUT_1] = clk; 1702 1703 /* clk_out_2 */ 1704 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1705 ARRAY_SIZE(clk_out2_parents), 1706 CLK_SET_RATE_NO_REPARENT, 1707 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1708 &clk_out_lock); 1709 clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk; 1710 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1711 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1712 &clk_out_lock); 1713 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1714 clks[TEGRA114_CLK_CLK_OUT_2] = clk; 1715 1716 /* clk_out_3 */ 1717 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1718 ARRAY_SIZE(clk_out3_parents), 1719 CLK_SET_RATE_NO_REPARENT, 1720 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1721 &clk_out_lock); 1722 clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk; 1723 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1724 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1725 &clk_out_lock); 1726 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1727 clks[TEGRA114_CLK_CLK_OUT_3] = clk; 1728 1729 /* blink */ 1730 /* clear the blink timer register to directly output clk_32k */ 1731 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1732 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1733 pmc_base + PMC_DPD_PADS_ORIDE, 1734 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1735 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1736 pmc_base + PMC_CTRL, 1737 PMC_CTRL_BLINK_ENB, 0, NULL); 1738 clk_register_clkdev(clk, "blink", NULL); 1739 clks[TEGRA114_CLK_BLINK] = clk; 1740 1741} 1742 1743static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1744 "pll_p", "pll_p_out2", "unused", 1745 "clk_32k", "pll_m_out1" }; 1746 1747static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1748 "pll_p", "pll_p_out4", "unused", 1749 "unused", "pll_x" }; 1750 1751static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1752 "pll_p", "pll_p_out4", "unused", 1753 "unused", "pll_x", "pll_x_out0" }; 1754 1755static void __init tegra114_super_clk_init(void __iomem *clk_base) 1756{ 1757 struct clk *clk; 1758 1759 /* CCLKG */ 1760 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1761 ARRAY_SIZE(cclk_g_parents), 1762 CLK_SET_RATE_PARENT, 1763 clk_base + CCLKG_BURST_POLICY, 1764 0, 4, 0, 0, NULL); 1765 clk_register_clkdev(clk, "cclk_g", NULL); 1766 clks[TEGRA114_CLK_CCLK_G] = clk; 1767 1768 /* CCLKLP */ 1769 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1770 ARRAY_SIZE(cclk_lp_parents), 1771 CLK_SET_RATE_PARENT, 1772 clk_base + CCLKLP_BURST_POLICY, 1773 0, 4, 8, 9, NULL); 1774 clk_register_clkdev(clk, "cclk_lp", NULL); 1775 clks[TEGRA114_CLK_CCLK_LP] = clk; 1776 1777 /* SCLK */ 1778 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1779 ARRAY_SIZE(sclk_parents), 1780 CLK_SET_RATE_PARENT, 1781 clk_base + SCLK_BURST_POLICY, 1782 0, 4, 0, 0, NULL); 1783 clk_register_clkdev(clk, "sclk", NULL); 1784 clks[TEGRA114_CLK_SCLK] = clk; 1785 1786 /* HCLK */ 1787 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1788 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1789 &sysrate_lock); 1790 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | 1791 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1792 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1793 clk_register_clkdev(clk, "hclk", NULL); 1794 clks[TEGRA114_CLK_HCLK] = clk; 1795 1796 /* PCLK */ 1797 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1798 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1799 &sysrate_lock); 1800 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 1801 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1802 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1803 clk_register_clkdev(clk, "pclk", NULL); 1804 clks[TEGRA114_CLK_PCLK] = clk; 1805} 1806 1807static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1808 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S0), 1809 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S1), 1810 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S2), 1811 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S3), 1812 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S4), 1813 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_OUT), 1814 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_IN), 1815 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_PWM), 1816 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_ADX), 1817 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_AMX), 1818 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA), 1819 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA2CODEC_2X), 1820 TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC1), 1821 TEGRA_INIT_DATA_MUX8("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC2), 1822 TEGRA_INIT_DATA_MUX8("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC3), 1823 TEGRA_INIT_DATA_MUX8("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC4), 1824 TEGRA_INIT_DATA_MUX8("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC5), 1825 TEGRA_INIT_DATA_MUX8("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC6), 1826 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), 1827 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), 1828 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_VFIR), 1829 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, TEGRA114_CLK_SDMMC1), 1830 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, TEGRA114_CLK_SDMMC2), 1831 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, TEGRA114_CLK_SDMMC3), 1832 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, TEGRA114_CLK_SDMMC4), 1833 TEGRA_INIT_DATA_INT8("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, TEGRA114_CLK_VDE), 1834 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_CSITE, CLK_IGNORE_UNUSED), 1835 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_LA), 1836 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TRACE), 1837 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_OWR), 1838 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, TEGRA114_CLK_NOR), 1839 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_MIPI), 1840 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA114_CLK_I2C1), 1841 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA114_CLK_I2C2), 1842 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA114_CLK_I2C3), 1843 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA114_CLK_I2C4), 1844 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA114_CLK_I2C5), 1845 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, TEGRA114_CLK_UARTA), 1846 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, TEGRA114_CLK_UARTB), 1847 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, TEGRA114_CLK_UARTC), 1848 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, TEGRA114_CLK_UARTD), 1849 TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, TEGRA114_CLK_GR3D), 1850 TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, TEGRA114_CLK_GR2D), 1851 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), 1852 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, TEGRA114_CLK_VI), 1853 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, TEGRA114_CLK_EPP), 1854 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, TEGRA114_CLK_MSENC), 1855 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, TEGRA114_CLK_TSEC), 1856 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, TEGRA114_CLK_HOST1X), 1857 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, TEGRA114_CLK_HDMI), 1858 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, TEGRA114_CLK_CILAB), 1859 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, TEGRA114_CLK_CILCD), 1860 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, TEGRA114_CLK_CILE), 1861 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, TEGRA114_CLK_DSIALP), 1862 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, TEGRA114_CLK_DSIBLP), 1863 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TSENSOR), 1864 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, TEGRA114_CLK_ACTMON), 1865 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, TEGRA114_CLK_EXTERN1), 1866 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, TEGRA114_CLK_EXTERN2), 1867 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, TEGRA114_CLK_EXTERN3), 1868 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2CSLOW), 1869 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SE), 1870 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, TEGRA114_CLK_MSELECT, CLK_IGNORE_UNUSED), 1871 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_REF), 1872 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_SOC), 1873 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SOC_THERM), 1874 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_HOST_SRC), 1875 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FALCON_SRC), 1876 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FS_SRC), 1877 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_SS_SRC), 1878 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_DEV_SRC), 1879 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_D_AUDIO), 1880 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM0), 1881 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM1), 1882 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM2), 1883}; 1884 1885static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1886 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, TEGRA114_CLK_DISP1), 1887 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, TEGRA114_CLK_DISP2), 1888}; 1889 1890static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1891{ 1892 struct tegra_periph_init_data *data; 1893 struct clk *clk; 1894 int i; 1895 u32 val; 1896 1897 /* apbdma */ 1898 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1899 0, 34, &periph_h_regs, 1900 periph_clk_enb_refcnt); 1901 clks[TEGRA114_CLK_APBDMA] = clk; 1902 1903 /* rtc */ 1904 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1905 TEGRA_PERIPH_ON_APB | 1906 TEGRA_PERIPH_NO_RESET, clk_base, 1907 0, 4, &periph_l_regs, 1908 periph_clk_enb_refcnt); 1909 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1910 clks[TEGRA114_CLK_RTC] = clk; 1911 1912 /* kbc */ 1913 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1914 TEGRA_PERIPH_ON_APB | 1915 TEGRA_PERIPH_NO_RESET, clk_base, 1916 0, 36, &periph_h_regs, 1917 periph_clk_enb_refcnt); 1918 clks[TEGRA114_CLK_KBC] = clk; 1919 1920 /* timer */ 1921 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1922 0, 5, &periph_l_regs, 1923 periph_clk_enb_refcnt); 1924 clk_register_clkdev(clk, NULL, "timer"); 1925 clks[TEGRA114_CLK_TIMER] = clk; 1926 1927 /* kfuse */ 1928 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1929 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1930 &periph_h_regs, periph_clk_enb_refcnt); 1931 clks[TEGRA114_CLK_KFUSE] = clk; 1932 1933 /* fuse */ 1934 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1935 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1936 &periph_h_regs, periph_clk_enb_refcnt); 1937 clks[TEGRA114_CLK_FUSE] = clk; 1938 1939 /* fuse_burn */ 1940 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1941 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1942 &periph_h_regs, periph_clk_enb_refcnt); 1943 clks[TEGRA114_CLK_FUSE_BURN] = clk; 1944 1945 /* apbif */ 1946 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1947 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1948 &periph_v_regs, periph_clk_enb_refcnt); 1949 clks[TEGRA114_CLK_APBIF] = clk; 1950 1951 /* hda2hdmi */ 1952 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1953 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1954 &periph_w_regs, periph_clk_enb_refcnt); 1955 clks[TEGRA114_CLK_HDA2HDMI] = clk; 1956 1957 /* vcp */ 1958 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1959 29, &periph_l_regs, 1960 periph_clk_enb_refcnt); 1961 clks[TEGRA114_CLK_VCP] = clk; 1962 1963 /* bsea */ 1964 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 1965 0, 62, &periph_h_regs, 1966 periph_clk_enb_refcnt); 1967 clks[TEGRA114_CLK_BSEA] = clk; 1968 1969 /* bsev */ 1970 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 1971 0, 63, &periph_h_regs, 1972 periph_clk_enb_refcnt); 1973 clks[TEGRA114_CLK_BSEV] = clk; 1974 1975 /* mipi-cal */ 1976 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1977 0, 56, &periph_h_regs, 1978 periph_clk_enb_refcnt); 1979 clks[TEGRA114_CLK_MIPI_CAL] = clk; 1980 1981 /* usbd */ 1982 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 1983 0, 22, &periph_l_regs, 1984 periph_clk_enb_refcnt); 1985 clks[TEGRA114_CLK_USBD] = clk; 1986 1987 /* usb2 */ 1988 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 1989 0, 58, &periph_h_regs, 1990 periph_clk_enb_refcnt); 1991 clks[TEGRA114_CLK_USB2] = clk; 1992 1993 /* usb3 */ 1994 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 1995 0, 59, &periph_h_regs, 1996 periph_clk_enb_refcnt); 1997 clks[TEGRA114_CLK_USB3] = clk; 1998 1999 /* csi */ 2000 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 2001 0, 52, &periph_h_regs, 2002 periph_clk_enb_refcnt); 2003 clks[TEGRA114_CLK_CSI] = clk; 2004 2005 /* isp */ 2006 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 2007 23, &periph_l_regs, 2008 periph_clk_enb_refcnt); 2009 clks[TEGRA114_CLK_ISP] = clk; 2010 2011 /* csus */ 2012 clk = tegra_clk_register_periph_gate("csus", "clk_m", 2013 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 2014 &periph_u_regs, periph_clk_enb_refcnt); 2015 clks[TEGRA114_CLK_CSUS] = clk; 2016 2017 /* dds */ 2018 clk = tegra_clk_register_periph_gate("dds", "clk_m", 2019 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 2020 &periph_w_regs, periph_clk_enb_refcnt); 2021 clks[TEGRA114_CLK_DDS] = clk; 2022 2023 /* dp2 */ 2024 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 2025 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 2026 &periph_w_regs, periph_clk_enb_refcnt); 2027 clks[TEGRA114_CLK_DP2] = clk; 2028 2029 /* dtv */ 2030 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 2031 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 2032 &periph_u_regs, periph_clk_enb_refcnt); 2033 clks[TEGRA114_CLK_DTV] = clk; 2034 2035 /* dsia */ 2036 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2037 ARRAY_SIZE(mux_plld_out0_plld2_out0), 2038 CLK_SET_RATE_NO_REPARENT, 2039 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2040 clks[TEGRA114_CLK_DSIA_MUX] = clk; 2041 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2042 0, 48, &periph_h_regs, 2043 periph_clk_enb_refcnt); 2044 clks[TEGRA114_CLK_DSIA] = clk; 2045 2046 /* dsib */ 2047 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2048 ARRAY_SIZE(mux_plld_out0_plld2_out0), 2049 CLK_SET_RATE_NO_REPARENT, 2050 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2051 clks[TEGRA114_CLK_DSIB_MUX] = clk; 2052 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2053 0, 82, &periph_u_regs, 2054 periph_clk_enb_refcnt); 2055 clks[TEGRA114_CLK_DSIB] = clk; 2056 2057 /* xusb_hs_src */ 2058 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); 2059 val |= BIT(25); /* always select PLLU_60M */ 2060 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); 2061 2062 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 2063 1, 1); 2064 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk; 2065 2066 /* xusb_host */ 2067 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 2068 clk_base, 0, 89, &periph_u_regs, 2069 periph_clk_enb_refcnt); 2070 clks[TEGRA114_CLK_XUSB_HOST] = clk; 2071 2072 /* xusb_ss */ 2073 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 2074 clk_base, 0, 156, &periph_w_regs, 2075 periph_clk_enb_refcnt); 2076 clks[TEGRA114_CLK_XUSB_HOST] = clk; 2077 2078 /* xusb_dev */ 2079 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 2080 clk_base, 0, 95, &periph_u_regs, 2081 periph_clk_enb_refcnt); 2082 clks[TEGRA114_CLK_XUSB_DEV] = clk; 2083 2084 /* emc */ 2085 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2086 ARRAY_SIZE(mux_pllmcp_clkm), 2087 CLK_SET_RATE_NO_REPARENT, 2088 clk_base + CLK_SOURCE_EMC, 2089 29, 3, 0, NULL); 2090 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2091 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 2092 periph_clk_enb_refcnt); 2093 clks[TEGRA114_CLK_EMC] = clk; 2094 2095 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 2096 data = &tegra_periph_clk_list[i]; 2097 clk = tegra_clk_register_periph(data->name, data->parent_names, 2098 data->num_parents, &data->periph, 2099 clk_base, data->offset, data->flags); 2100 clks[data->clk_id] = clk; 2101 } 2102 2103 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 2104 data = &tegra_periph_nodiv_clk_list[i]; 2105 clk = tegra_clk_register_periph_nodiv(data->name, 2106 data->parent_names, data->num_parents, 2107 &data->periph, clk_base, data->offset); 2108 clks[data->clk_id] = clk; 2109 } 2110} 2111 2112/* Tegra114 CPU clock and reset control functions */ 2113static void tegra114_wait_cpu_in_reset(u32 cpu) 2114{ 2115 unsigned int reg; 2116 2117 do { 2118 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 2119 cpu_relax(); 2120 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 2121} 2122static void tegra114_disable_cpu_clock(u32 cpu) 2123{ 2124 /* flow controller would take care in the power sequence. */ 2125} 2126 2127#ifdef CONFIG_PM_SLEEP 2128static void tegra114_cpu_clock_suspend(void) 2129{ 2130 /* switch coresite to clk_m, save off original source */ 2131 tegra114_cpu_clk_sctx.clk_csite_src = 2132 readl(clk_base + CLK_SOURCE_CSITE); 2133 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 2134 2135 tegra114_cpu_clk_sctx.cclkg_burst = 2136 readl(clk_base + CCLKG_BURST_POLICY); 2137 tegra114_cpu_clk_sctx.cclkg_divider = 2138 readl(clk_base + CCLKG_BURST_POLICY + 4); 2139} 2140 2141static void tegra114_cpu_clock_resume(void) 2142{ 2143 writel(tegra114_cpu_clk_sctx.clk_csite_src, 2144 clk_base + CLK_SOURCE_CSITE); 2145 2146 writel(tegra114_cpu_clk_sctx.cclkg_burst, 2147 clk_base + CCLKG_BURST_POLICY); 2148 writel(tegra114_cpu_clk_sctx.cclkg_divider, 2149 clk_base + CCLKG_BURST_POLICY + 4); 2150} 2151#endif 2152 2153static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { 2154 .wait_for_reset = tegra114_wait_cpu_in_reset, 2155 .disable_clock = tegra114_disable_cpu_clock, 2156#ifdef CONFIG_PM_SLEEP 2157 .suspend = tegra114_cpu_clock_suspend, 2158 .resume = tegra114_cpu_clock_resume, 2159#endif 2160}; 2161 2162static const struct of_device_id pmc_match[] __initconst = { 2163 { .compatible = "nvidia,tegra114-pmc" }, 2164 {}, 2165}; 2166 2167/* 2168 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 2169 * breaks 2170 */ 2171static struct tegra_clk_init_table init_table[] __initdata = { 2172 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0}, 2173 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0}, 2174 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0}, 2175 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0}, 2176 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1}, 2177 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1}, 2178 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1}, 2179 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1}, 2180 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1}, 2181 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2182 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2183 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2184 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2185 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2186 {TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0}, 2187 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, 2188 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, 2189 {TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 2190 {TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 2191 2192 /* This MUST be the last entry. */ 2193 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, 2194}; 2195 2196static void __init tegra114_clock_apply_init_table(void) 2197{ 2198 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); 2199} 2200 2201 2202/** 2203 * tegra114_car_barrier - wait for pending writes to the CAR to complete 2204 * 2205 * Wait for any outstanding writes to the CAR MMIO space from this CPU 2206 * to complete before continuing execution. No return value. 2207 */ 2208static void tegra114_car_barrier(void) 2209{ 2210 wmb(); /* probably unnecessary */ 2211 readl_relaxed(clk_base + CPU_FINETRIM_SELECT); 2212} 2213 2214/** 2215 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays 2216 * 2217 * When the CPU rail voltage is in the high-voltage range, use the 2218 * built-in hardwired clock propagation delays in the CPU clock 2219 * shaper. No return value. 2220 */ 2221void tegra114_clock_tune_cpu_trimmers_high(void) 2222{ 2223 u32 select = 0; 2224 2225 /* Use hardwired rise->rise & fall->fall clock propagation delays */ 2226 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2227 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2228 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2229 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 2230 2231 tegra114_car_barrier(); 2232} 2233EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high); 2234 2235/** 2236 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays 2237 * 2238 * When the CPU rail voltage is in the low-voltage range, use the 2239 * extended clock propagation delays set by 2240 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to 2241 * maintain the input clock duty cycle that the FCPU subsystem 2242 * expects. No return value. 2243 */ 2244void tegra114_clock_tune_cpu_trimmers_low(void) 2245{ 2246 u32 select = 0; 2247 2248 /* 2249 * Use software-specified rise->rise & fall->fall clock 2250 * propagation delays (from 2251 * tegra114_clock_tune_cpu_trimmers_init() 2252 */ 2253 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2254 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2255 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2256 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 2257 2258 tegra114_car_barrier(); 2259} 2260EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low); 2261 2262/** 2263 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays 2264 * 2265 * Program extended clock propagation delays into the FCPU clock 2266 * shaper and enable them. XXX Define the purpose - peak current 2267 * reduction? No return value. 2268 */ 2269/* XXX Initial voltage rail state assumption issues? */ 2270void tegra114_clock_tune_cpu_trimmers_init(void) 2271{ 2272 u32 dr = 0, r = 0; 2273 2274 /* Increment the rise->rise clock delay by four steps */ 2275 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK | 2276 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK | 2277 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK); 2278 writel_relaxed(r, clk_base + CPU_FINETRIM_R); 2279 2280 /* 2281 * Use the rise->rise clock propagation delay specified in the 2282 * r field 2283 */ 2284 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2285 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2286 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2287 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); 2288 2289 tegra114_clock_tune_cpu_trimmers_low(); 2290} 2291EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); 2292 2293/** 2294 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 2295 * 2296 * Assert the reset line of the DFLL's DVCO. No return value. 2297 */ 2298void tegra114_clock_assert_dfll_dvco_reset(void) 2299{ 2300 u32 v; 2301 2302 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 2303 v |= (1 << DVFS_DFLL_RESET_SHIFT); 2304 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 2305 tegra114_car_barrier(); 2306} 2307EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); 2308 2309/** 2310 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 2311 * 2312 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 2313 * operate. No return value. 2314 */ 2315void tegra114_clock_deassert_dfll_dvco_reset(void) 2316{ 2317 u32 v; 2318 2319 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 2320 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 2321 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 2322 tegra114_car_barrier(); 2323} 2324EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); 2325 2326static void __init tegra114_clock_init(struct device_node *np) 2327{ 2328 struct device_node *node; 2329 int i; 2330 2331 clk_base = of_iomap(np, 0); 2332 if (!clk_base) { 2333 pr_err("ioremap tegra114 CAR failed\n"); 2334 return; 2335 } 2336 2337 node = of_find_matching_node(NULL, pmc_match); 2338 if (!node) { 2339 pr_err("Failed to find pmc node\n"); 2340 WARN_ON(1); 2341 return; 2342 } 2343 2344 pmc_base = of_iomap(node, 0); 2345 if (!pmc_base) { 2346 pr_err("Can't map pmc registers\n"); 2347 WARN_ON(1); 2348 return; 2349 } 2350 2351 if (tegra114_osc_clk_init(clk_base) < 0) 2352 return; 2353 2354 tegra114_fixed_clk_init(clk_base); 2355 tegra114_pll_init(clk_base, pmc_base); 2356 tegra114_periph_clk_init(clk_base); 2357 tegra114_audio_clk_init(clk_base); 2358 tegra114_pmc_clk_init(pmc_base); 2359 tegra114_super_clk_init(clk_base); 2360 2361 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2362 if (IS_ERR(clks[i])) { 2363 pr_err 2364 ("Tegra114 clk %d: register failed with %ld\n", 2365 i, PTR_ERR(clks[i])); 2366 } 2367 if (!clks[i]) 2368 clks[i] = ERR_PTR(-EINVAL); 2369 } 2370 2371 clk_data.clks = clks; 2372 clk_data.clk_num = ARRAY_SIZE(clks); 2373 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2374 2375 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 2376 2377 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 2378} 2379CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); 2380