clk-tegra114.c revision fc20eeff6c03fcdbb2b5ac21472778b573850e77
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/export.h> 25#include <linux/clk/tegra.h> 26#include <dt-bindings/clock/tegra114-car.h> 27 28#include "clk.h" 29 30#define RST_DEVICES_L 0x004 31#define RST_DEVICES_H 0x008 32#define RST_DEVICES_U 0x00C 33#define RST_DFLL_DVCO 0x2F4 34#define RST_DEVICES_V 0x358 35#define RST_DEVICES_W 0x35C 36#define RST_DEVICES_X 0x28C 37#define RST_DEVICES_SET_L 0x300 38#define RST_DEVICES_CLR_L 0x304 39#define RST_DEVICES_SET_H 0x308 40#define RST_DEVICES_CLR_H 0x30c 41#define RST_DEVICES_SET_U 0x310 42#define RST_DEVICES_CLR_U 0x314 43#define RST_DEVICES_SET_V 0x430 44#define RST_DEVICES_CLR_V 0x434 45#define RST_DEVICES_SET_W 0x438 46#define RST_DEVICES_CLR_W 0x43c 47#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 48#define CPU_FINETRIM_DR 0x4d8 /* rise->rise prop dly A */ 49#define CPU_FINETRIM_R 0x4e4 /* rise->rise prop dly inc A */ 50#define RST_DEVICES_NUM 5 51 52/* RST_DFLL_DVCO bitfields */ 53#define DVFS_DFLL_RESET_SHIFT 0 54 55/* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */ 56#define CPU_FINETRIM_1_FCPU_1 BIT(0) /* fcpu0 */ 57#define CPU_FINETRIM_1_FCPU_2 BIT(1) /* fcpu1 */ 58#define CPU_FINETRIM_1_FCPU_3 BIT(2) /* fcpu2 */ 59#define CPU_FINETRIM_1_FCPU_4 BIT(3) /* fcpu3 */ 60#define CPU_FINETRIM_1_FCPU_5 BIT(4) /* fl2 */ 61#define CPU_FINETRIM_1_FCPU_6 BIT(5) /* ftop */ 62 63/* CPU_FINETRIM_R bitfields */ 64#define CPU_FINETRIM_R_FCPU_1_SHIFT 0 /* fcpu0 */ 65#define CPU_FINETRIM_R_FCPU_1_MASK (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT) 66#define CPU_FINETRIM_R_FCPU_2_SHIFT 2 /* fcpu1 */ 67#define CPU_FINETRIM_R_FCPU_2_MASK (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT) 68#define CPU_FINETRIM_R_FCPU_3_SHIFT 4 /* fcpu2 */ 69#define CPU_FINETRIM_R_FCPU_3_MASK (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT) 70#define CPU_FINETRIM_R_FCPU_4_SHIFT 6 /* fcpu3 */ 71#define CPU_FINETRIM_R_FCPU_4_MASK (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT) 72#define CPU_FINETRIM_R_FCPU_5_SHIFT 8 /* fl2 */ 73#define CPU_FINETRIM_R_FCPU_5_MASK (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT) 74#define CPU_FINETRIM_R_FCPU_6_SHIFT 10 /* ftop */ 75#define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT) 76 77#define CLK_OUT_ENB_L 0x010 78#define CLK_OUT_ENB_H 0x014 79#define CLK_OUT_ENB_U 0x018 80#define CLK_OUT_ENB_V 0x360 81#define CLK_OUT_ENB_W 0x364 82#define CLK_OUT_ENB_X 0x280 83#define CLK_OUT_ENB_SET_L 0x320 84#define CLK_OUT_ENB_CLR_L 0x324 85#define CLK_OUT_ENB_SET_H 0x328 86#define CLK_OUT_ENB_CLR_H 0x32c 87#define CLK_OUT_ENB_SET_U 0x330 88#define CLK_OUT_ENB_CLR_U 0x334 89#define CLK_OUT_ENB_SET_V 0x440 90#define CLK_OUT_ENB_CLR_V 0x444 91#define CLK_OUT_ENB_SET_W 0x448 92#define CLK_OUT_ENB_CLR_W 0x44c 93#define CLK_OUT_ENB_SET_X 0x284 94#define CLK_OUT_ENB_CLR_X 0x288 95#define CLK_OUT_ENB_NUM 6 96 97#define PLLC_BASE 0x80 98#define PLLC_MISC2 0x88 99#define PLLC_MISC 0x8c 100#define PLLC2_BASE 0x4e8 101#define PLLC2_MISC 0x4ec 102#define PLLC3_BASE 0x4fc 103#define PLLC3_MISC 0x500 104#define PLLM_BASE 0x90 105#define PLLM_MISC 0x9c 106#define PLLP_BASE 0xa0 107#define PLLP_MISC 0xac 108#define PLLX_BASE 0xe0 109#define PLLX_MISC 0xe4 110#define PLLX_MISC2 0x514 111#define PLLX_MISC3 0x518 112#define PLLD_BASE 0xd0 113#define PLLD_MISC 0xdc 114#define PLLD2_BASE 0x4b8 115#define PLLD2_MISC 0x4bc 116#define PLLE_BASE 0xe8 117#define PLLE_MISC 0xec 118#define PLLA_BASE 0xb0 119#define PLLA_MISC 0xbc 120#define PLLU_BASE 0xc0 121#define PLLU_MISC 0xcc 122#define PLLRE_BASE 0x4c4 123#define PLLRE_MISC 0x4c8 124 125#define PLL_MISC_LOCK_ENABLE 18 126#define PLLC_MISC_LOCK_ENABLE 24 127#define PLLDU_MISC_LOCK_ENABLE 22 128#define PLLE_MISC_LOCK_ENABLE 9 129#define PLLRE_MISC_LOCK_ENABLE 30 130 131#define PLLC_IDDQ_BIT 26 132#define PLLX_IDDQ_BIT 3 133#define PLLRE_IDDQ_BIT 16 134 135#define PLL_BASE_LOCK BIT(27) 136#define PLLE_MISC_LOCK BIT(11) 137#define PLLRE_MISC_LOCK BIT(24) 138#define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 139 140#define PLLE_AUX 0x48c 141#define PLLC_OUT 0x84 142#define PLLM_OUT 0x94 143#define PLLP_OUTA 0xa4 144#define PLLP_OUTB 0xa8 145#define PLLA_OUT 0xb4 146 147#define AUDIO_SYNC_CLK_I2S0 0x4a0 148#define AUDIO_SYNC_CLK_I2S1 0x4a4 149#define AUDIO_SYNC_CLK_I2S2 0x4a8 150#define AUDIO_SYNC_CLK_I2S3 0x4ac 151#define AUDIO_SYNC_CLK_I2S4 0x4b0 152#define AUDIO_SYNC_CLK_SPDIF 0x4b4 153 154#define AUDIO_SYNC_DOUBLER 0x49c 155 156#define PMC_CLK_OUT_CNTRL 0x1a8 157#define PMC_DPD_PADS_ORIDE 0x1c 158#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 159#define PMC_CTRL 0 160#define PMC_CTRL_BLINK_ENB 7 161#define PMC_BLINK_TIMER 0x40 162 163#define OSC_CTRL 0x50 164#define OSC_CTRL_OSC_FREQ_SHIFT 28 165#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 166 167#define PLLXC_SW_MAX_P 6 168 169#define CCLKG_BURST_POLICY 0x368 170#define CCLKLP_BURST_POLICY 0x370 171#define SCLK_BURST_POLICY 0x028 172#define SYSTEM_CLK_RATE 0x030 173 174#define UTMIP_PLL_CFG2 0x488 175#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 176#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 177#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 178#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 179#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 180 181#define UTMIP_PLL_CFG1 0x484 182#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 183#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 184#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 185#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 186#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 187#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 188#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 189 190#define UTMIPLL_HW_PWRDN_CFG0 0x52c 191#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 192#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 193#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 194#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 195#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 196#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 197#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 198#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 199 200#define CLK_SOURCE_I2S0 0x1d8 201#define CLK_SOURCE_I2S1 0x100 202#define CLK_SOURCE_I2S2 0x104 203#define CLK_SOURCE_NDFLASH 0x160 204#define CLK_SOURCE_I2S3 0x3bc 205#define CLK_SOURCE_I2S4 0x3c0 206#define CLK_SOURCE_SPDIF_OUT 0x108 207#define CLK_SOURCE_SPDIF_IN 0x10c 208#define CLK_SOURCE_PWM 0x110 209#define CLK_SOURCE_ADX 0x638 210#define CLK_SOURCE_AMX 0x63c 211#define CLK_SOURCE_HDA 0x428 212#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 213#define CLK_SOURCE_SBC1 0x134 214#define CLK_SOURCE_SBC2 0x118 215#define CLK_SOURCE_SBC3 0x11c 216#define CLK_SOURCE_SBC4 0x1b4 217#define CLK_SOURCE_SBC5 0x3c8 218#define CLK_SOURCE_SBC6 0x3cc 219#define CLK_SOURCE_SATA_OOB 0x420 220#define CLK_SOURCE_SATA 0x424 221#define CLK_SOURCE_NDSPEED 0x3f8 222#define CLK_SOURCE_VFIR 0x168 223#define CLK_SOURCE_SDMMC1 0x150 224#define CLK_SOURCE_SDMMC2 0x154 225#define CLK_SOURCE_SDMMC3 0x1bc 226#define CLK_SOURCE_SDMMC4 0x164 227#define CLK_SOURCE_VDE 0x1c8 228#define CLK_SOURCE_CSITE 0x1d4 229#define CLK_SOURCE_LA 0x1f8 230#define CLK_SOURCE_TRACE 0x634 231#define CLK_SOURCE_OWR 0x1cc 232#define CLK_SOURCE_NOR 0x1d0 233#define CLK_SOURCE_MIPI 0x174 234#define CLK_SOURCE_I2C1 0x124 235#define CLK_SOURCE_I2C2 0x198 236#define CLK_SOURCE_I2C3 0x1b8 237#define CLK_SOURCE_I2C4 0x3c4 238#define CLK_SOURCE_I2C5 0x128 239#define CLK_SOURCE_UARTA 0x178 240#define CLK_SOURCE_UARTB 0x17c 241#define CLK_SOURCE_UARTC 0x1a0 242#define CLK_SOURCE_UARTD 0x1c0 243#define CLK_SOURCE_UARTE 0x1c4 244#define CLK_SOURCE_UARTA_DBG 0x178 245#define CLK_SOURCE_UARTB_DBG 0x17c 246#define CLK_SOURCE_UARTC_DBG 0x1a0 247#define CLK_SOURCE_UARTD_DBG 0x1c0 248#define CLK_SOURCE_UARTE_DBG 0x1c4 249#define CLK_SOURCE_3D 0x158 250#define CLK_SOURCE_2D 0x15c 251#define CLK_SOURCE_VI_SENSOR 0x1a8 252#define CLK_SOURCE_VI 0x148 253#define CLK_SOURCE_EPP 0x16c 254#define CLK_SOURCE_MSENC 0x1f0 255#define CLK_SOURCE_TSEC 0x1f4 256#define CLK_SOURCE_HOST1X 0x180 257#define CLK_SOURCE_HDMI 0x18c 258#define CLK_SOURCE_DISP1 0x138 259#define CLK_SOURCE_DISP2 0x13c 260#define CLK_SOURCE_CILAB 0x614 261#define CLK_SOURCE_CILCD 0x618 262#define CLK_SOURCE_CILE 0x61c 263#define CLK_SOURCE_DSIALP 0x620 264#define CLK_SOURCE_DSIBLP 0x624 265#define CLK_SOURCE_TSENSOR 0x3b8 266#define CLK_SOURCE_D_AUDIO 0x3d0 267#define CLK_SOURCE_DAM0 0x3d8 268#define CLK_SOURCE_DAM1 0x3dc 269#define CLK_SOURCE_DAM2 0x3e0 270#define CLK_SOURCE_ACTMON 0x3e8 271#define CLK_SOURCE_EXTERN1 0x3ec 272#define CLK_SOURCE_EXTERN2 0x3f0 273#define CLK_SOURCE_EXTERN3 0x3f4 274#define CLK_SOURCE_I2CSLOW 0x3fc 275#define CLK_SOURCE_SE 0x42c 276#define CLK_SOURCE_MSELECT 0x3b4 277#define CLK_SOURCE_DFLL_REF 0x62c 278#define CLK_SOURCE_DFLL_SOC 0x630 279#define CLK_SOURCE_SOC_THERM 0x644 280#define CLK_SOURCE_XUSB_HOST_SRC 0x600 281#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 282#define CLK_SOURCE_XUSB_FS_SRC 0x608 283#define CLK_SOURCE_XUSB_SS_SRC 0x610 284#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 285#define CLK_SOURCE_EMC 0x19c 286 287/* PLLM override registers */ 288#define PMC_PLLM_WB0_OVERRIDE 0x1dc 289#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 290 291/* Tegra CPU clock and reset control regs */ 292#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 293 294#ifdef CONFIG_PM_SLEEP 295static struct cpu_clk_suspend_context { 296 u32 clk_csite_src; 297 u32 cclkg_burst; 298 u32 cclkg_divider; 299} tegra114_cpu_clk_sctx; 300#endif 301 302static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 303 304static void __iomem *clk_base; 305static void __iomem *pmc_base; 306 307static DEFINE_SPINLOCK(pll_d_lock); 308static DEFINE_SPINLOCK(pll_d2_lock); 309static DEFINE_SPINLOCK(pll_u_lock); 310static DEFINE_SPINLOCK(pll_div_lock); 311static DEFINE_SPINLOCK(pll_re_lock); 312static DEFINE_SPINLOCK(clk_doubler_lock); 313static DEFINE_SPINLOCK(clk_out_lock); 314static DEFINE_SPINLOCK(sysrate_lock); 315 316static struct div_nmp pllxc_nmp = { 317 .divm_shift = 0, 318 .divm_width = 8, 319 .divn_shift = 8, 320 .divn_width = 8, 321 .divp_shift = 20, 322 .divp_width = 4, 323}; 324 325static struct pdiv_map pllxc_p[] = { 326 { .pdiv = 1, .hw_val = 0 }, 327 { .pdiv = 2, .hw_val = 1 }, 328 { .pdiv = 3, .hw_val = 2 }, 329 { .pdiv = 4, .hw_val = 3 }, 330 { .pdiv = 5, .hw_val = 4 }, 331 { .pdiv = 6, .hw_val = 5 }, 332 { .pdiv = 8, .hw_val = 6 }, 333 { .pdiv = 10, .hw_val = 7 }, 334 { .pdiv = 12, .hw_val = 8 }, 335 { .pdiv = 16, .hw_val = 9 }, 336 { .pdiv = 12, .hw_val = 10 }, 337 { .pdiv = 16, .hw_val = 11 }, 338 { .pdiv = 20, .hw_val = 12 }, 339 { .pdiv = 24, .hw_val = 13 }, 340 { .pdiv = 32, .hw_val = 14 }, 341 { .pdiv = 0, .hw_val = 0 }, 342}; 343 344static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 345 { 12000000, 624000000, 104, 0, 2}, 346 { 12000000, 600000000, 100, 0, 2}, 347 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 348 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 349 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 350 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 351 { 0, 0, 0, 0, 0, 0 }, 352}; 353 354static struct tegra_clk_pll_params pll_c_params = { 355 .input_min = 12000000, 356 .input_max = 800000000, 357 .cf_min = 12000000, 358 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 359 .vco_min = 600000000, 360 .vco_max = 1400000000, 361 .base_reg = PLLC_BASE, 362 .misc_reg = PLLC_MISC, 363 .lock_mask = PLL_BASE_LOCK, 364 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 365 .lock_delay = 300, 366 .iddq_reg = PLLC_MISC, 367 .iddq_bit_idx = PLLC_IDDQ_BIT, 368 .max_p = PLLXC_SW_MAX_P, 369 .dyn_ramp_reg = PLLC_MISC2, 370 .stepa_shift = 17, 371 .stepb_shift = 9, 372 .pdiv_tohw = pllxc_p, 373 .div_nmp = &pllxc_nmp, 374}; 375 376static struct div_nmp pllcx_nmp = { 377 .divm_shift = 0, 378 .divm_width = 2, 379 .divn_shift = 8, 380 .divn_width = 8, 381 .divp_shift = 20, 382 .divp_width = 3, 383}; 384 385static struct pdiv_map pllc_p[] = { 386 { .pdiv = 1, .hw_val = 0 }, 387 { .pdiv = 2, .hw_val = 1 }, 388 { .pdiv = 4, .hw_val = 3 }, 389 { .pdiv = 8, .hw_val = 5 }, 390 { .pdiv = 16, .hw_val = 7 }, 391 { .pdiv = 0, .hw_val = 0 }, 392}; 393 394static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 395 {12000000, 600000000, 100, 0, 2}, 396 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 397 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 398 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 399 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 400 {0, 0, 0, 0, 0, 0}, 401}; 402 403static struct tegra_clk_pll_params pll_c2_params = { 404 .input_min = 12000000, 405 .input_max = 48000000, 406 .cf_min = 12000000, 407 .cf_max = 19200000, 408 .vco_min = 600000000, 409 .vco_max = 1200000000, 410 .base_reg = PLLC2_BASE, 411 .misc_reg = PLLC2_MISC, 412 .lock_mask = PLL_BASE_LOCK, 413 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 414 .lock_delay = 300, 415 .pdiv_tohw = pllc_p, 416 .div_nmp = &pllcx_nmp, 417 .max_p = 7, 418 .ext_misc_reg[0] = 0x4f0, 419 .ext_misc_reg[1] = 0x4f4, 420 .ext_misc_reg[2] = 0x4f8, 421}; 422 423static struct tegra_clk_pll_params pll_c3_params = { 424 .input_min = 12000000, 425 .input_max = 48000000, 426 .cf_min = 12000000, 427 .cf_max = 19200000, 428 .vco_min = 600000000, 429 .vco_max = 1200000000, 430 .base_reg = PLLC3_BASE, 431 .misc_reg = PLLC3_MISC, 432 .lock_mask = PLL_BASE_LOCK, 433 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 434 .lock_delay = 300, 435 .pdiv_tohw = pllc_p, 436 .div_nmp = &pllcx_nmp, 437 .max_p = 7, 438 .ext_misc_reg[0] = 0x504, 439 .ext_misc_reg[1] = 0x508, 440 .ext_misc_reg[2] = 0x50c, 441}; 442 443static struct div_nmp pllm_nmp = { 444 .divm_shift = 0, 445 .divm_width = 8, 446 .override_divm_shift = 0, 447 .divn_shift = 8, 448 .divn_width = 8, 449 .override_divn_shift = 8, 450 .divp_shift = 20, 451 .divp_width = 1, 452 .override_divp_shift = 27, 453}; 454 455static struct pdiv_map pllm_p[] = { 456 { .pdiv = 1, .hw_val = 0 }, 457 { .pdiv = 2, .hw_val = 1 }, 458 { .pdiv = 0, .hw_val = 0 }, 459}; 460 461static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 462 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 463 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 464 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 465 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 466 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 467 {0, 0, 0, 0, 0, 0}, 468}; 469 470static struct tegra_clk_pll_params pll_m_params = { 471 .input_min = 12000000, 472 .input_max = 500000000, 473 .cf_min = 12000000, 474 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 475 .vco_min = 400000000, 476 .vco_max = 1066000000, 477 .base_reg = PLLM_BASE, 478 .misc_reg = PLLM_MISC, 479 .lock_mask = PLL_BASE_LOCK, 480 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 481 .lock_delay = 300, 482 .max_p = 2, 483 .pdiv_tohw = pllm_p, 484 .div_nmp = &pllm_nmp, 485 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 486 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 487}; 488 489static struct div_nmp pllp_nmp = { 490 .divm_shift = 0, 491 .divm_width = 5, 492 .divn_shift = 8, 493 .divn_width = 10, 494 .divp_shift = 20, 495 .divp_width = 3, 496}; 497 498static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 499 {12000000, 216000000, 432, 12, 1, 8}, 500 {13000000, 216000000, 432, 13, 1, 8}, 501 {16800000, 216000000, 360, 14, 1, 8}, 502 {19200000, 216000000, 360, 16, 1, 8}, 503 {26000000, 216000000, 432, 26, 1, 8}, 504 {0, 0, 0, 0, 0, 0}, 505}; 506 507static struct tegra_clk_pll_params pll_p_params = { 508 .input_min = 2000000, 509 .input_max = 31000000, 510 .cf_min = 1000000, 511 .cf_max = 6000000, 512 .vco_min = 200000000, 513 .vco_max = 700000000, 514 .base_reg = PLLP_BASE, 515 .misc_reg = PLLP_MISC, 516 .lock_mask = PLL_BASE_LOCK, 517 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 518 .lock_delay = 300, 519 .div_nmp = &pllp_nmp, 520}; 521 522static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 523 {9600000, 282240000, 147, 5, 0, 4}, 524 {9600000, 368640000, 192, 5, 0, 4}, 525 {9600000, 240000000, 200, 8, 0, 8}, 526 527 {28800000, 282240000, 245, 25, 0, 8}, 528 {28800000, 368640000, 320, 25, 0, 8}, 529 {28800000, 240000000, 200, 24, 0, 8}, 530 {0, 0, 0, 0, 0, 0}, 531}; 532 533 534static struct tegra_clk_pll_params pll_a_params = { 535 .input_min = 2000000, 536 .input_max = 31000000, 537 .cf_min = 1000000, 538 .cf_max = 6000000, 539 .vco_min = 200000000, 540 .vco_max = 700000000, 541 .base_reg = PLLA_BASE, 542 .misc_reg = PLLA_MISC, 543 .lock_mask = PLL_BASE_LOCK, 544 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 545 .lock_delay = 300, 546 .div_nmp = &pllp_nmp, 547}; 548 549static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 550 {12000000, 216000000, 864, 12, 2, 12}, 551 {13000000, 216000000, 864, 13, 2, 12}, 552 {16800000, 216000000, 720, 14, 2, 12}, 553 {19200000, 216000000, 720, 16, 2, 12}, 554 {26000000, 216000000, 864, 26, 2, 12}, 555 556 {12000000, 594000000, 594, 12, 0, 12}, 557 {13000000, 594000000, 594, 13, 0, 12}, 558 {16800000, 594000000, 495, 14, 0, 12}, 559 {19200000, 594000000, 495, 16, 0, 12}, 560 {26000000, 594000000, 594, 26, 0, 12}, 561 562 {12000000, 1000000000, 1000, 12, 0, 12}, 563 {13000000, 1000000000, 1000, 13, 0, 12}, 564 {19200000, 1000000000, 625, 12, 0, 12}, 565 {26000000, 1000000000, 1000, 26, 0, 12}, 566 567 {0, 0, 0, 0, 0, 0}, 568}; 569 570static struct tegra_clk_pll_params pll_d_params = { 571 .input_min = 2000000, 572 .input_max = 40000000, 573 .cf_min = 1000000, 574 .cf_max = 6000000, 575 .vco_min = 500000000, 576 .vco_max = 1000000000, 577 .base_reg = PLLD_BASE, 578 .misc_reg = PLLD_MISC, 579 .lock_mask = PLL_BASE_LOCK, 580 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 581 .lock_delay = 1000, 582 .div_nmp = &pllp_nmp, 583}; 584 585static struct tegra_clk_pll_params pll_d2_params = { 586 .input_min = 2000000, 587 .input_max = 40000000, 588 .cf_min = 1000000, 589 .cf_max = 6000000, 590 .vco_min = 500000000, 591 .vco_max = 1000000000, 592 .base_reg = PLLD2_BASE, 593 .misc_reg = PLLD2_MISC, 594 .lock_mask = PLL_BASE_LOCK, 595 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 596 .lock_delay = 1000, 597 .div_nmp = &pllp_nmp, 598}; 599 600static struct pdiv_map pllu_p[] = { 601 { .pdiv = 1, .hw_val = 1 }, 602 { .pdiv = 2, .hw_val = 0 }, 603 { .pdiv = 0, .hw_val = 0 }, 604}; 605 606static struct div_nmp pllu_nmp = { 607 .divm_shift = 0, 608 .divm_width = 5, 609 .divn_shift = 8, 610 .divn_width = 10, 611 .divp_shift = 20, 612 .divp_width = 1, 613}; 614 615static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 616 {12000000, 480000000, 960, 12, 0, 12}, 617 {13000000, 480000000, 960, 13, 0, 12}, 618 {16800000, 480000000, 400, 7, 0, 5}, 619 {19200000, 480000000, 200, 4, 0, 3}, 620 {26000000, 480000000, 960, 26, 0, 12}, 621 {0, 0, 0, 0, 0, 0}, 622}; 623 624static struct tegra_clk_pll_params pll_u_params = { 625 .input_min = 2000000, 626 .input_max = 40000000, 627 .cf_min = 1000000, 628 .cf_max = 6000000, 629 .vco_min = 480000000, 630 .vco_max = 960000000, 631 .base_reg = PLLU_BASE, 632 .misc_reg = PLLU_MISC, 633 .lock_mask = PLL_BASE_LOCK, 634 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 635 .lock_delay = 1000, 636 .pdiv_tohw = pllu_p, 637 .div_nmp = &pllu_nmp, 638}; 639 640static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 641 /* 1 GHz */ 642 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 643 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 644 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 645 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 646 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 647 648 {0, 0, 0, 0, 0, 0}, 649}; 650 651static struct tegra_clk_pll_params pll_x_params = { 652 .input_min = 12000000, 653 .input_max = 800000000, 654 .cf_min = 12000000, 655 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 656 .vco_min = 700000000, 657 .vco_max = 2400000000U, 658 .base_reg = PLLX_BASE, 659 .misc_reg = PLLX_MISC, 660 .lock_mask = PLL_BASE_LOCK, 661 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 662 .lock_delay = 300, 663 .iddq_reg = PLLX_MISC3, 664 .iddq_bit_idx = PLLX_IDDQ_BIT, 665 .max_p = PLLXC_SW_MAX_P, 666 .dyn_ramp_reg = PLLX_MISC2, 667 .stepa_shift = 16, 668 .stepb_shift = 24, 669 .pdiv_tohw = pllxc_p, 670 .div_nmp = &pllxc_nmp, 671}; 672 673static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 674 /* PLLE special case: use cpcon field to store cml divider value */ 675 {336000000, 100000000, 100, 21, 16, 11}, 676 {312000000, 100000000, 200, 26, 24, 13}, 677 {0, 0, 0, 0, 0, 0}, 678}; 679 680static struct div_nmp plle_nmp = { 681 .divm_shift = 0, 682 .divm_width = 8, 683 .divn_shift = 8, 684 .divn_width = 8, 685 .divp_shift = 24, 686 .divp_width = 4, 687}; 688 689static struct tegra_clk_pll_params pll_e_params = { 690 .input_min = 12000000, 691 .input_max = 1000000000, 692 .cf_min = 12000000, 693 .cf_max = 75000000, 694 .vco_min = 1600000000, 695 .vco_max = 2400000000U, 696 .base_reg = PLLE_BASE, 697 .misc_reg = PLLE_MISC, 698 .aux_reg = PLLE_AUX, 699 .lock_mask = PLLE_MISC_LOCK, 700 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 701 .lock_delay = 300, 702 .div_nmp = &plle_nmp, 703}; 704 705static struct div_nmp pllre_nmp = { 706 .divm_shift = 0, 707 .divm_width = 8, 708 .divn_shift = 8, 709 .divn_width = 8, 710 .divp_shift = 16, 711 .divp_width = 4, 712}; 713 714static struct tegra_clk_pll_params pll_re_vco_params = { 715 .input_min = 12000000, 716 .input_max = 1000000000, 717 .cf_min = 12000000, 718 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 719 .vco_min = 300000000, 720 .vco_max = 600000000, 721 .base_reg = PLLRE_BASE, 722 .misc_reg = PLLRE_MISC, 723 .lock_mask = PLLRE_MISC_LOCK, 724 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 725 .lock_delay = 300, 726 .iddq_reg = PLLRE_MISC, 727 .iddq_bit_idx = PLLRE_IDDQ_BIT, 728 .div_nmp = &pllre_nmp, 729}; 730 731/* Peripheral clock registers */ 732 733static struct tegra_clk_periph_regs periph_l_regs = { 734 .enb_reg = CLK_OUT_ENB_L, 735 .enb_set_reg = CLK_OUT_ENB_SET_L, 736 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 737 .rst_reg = RST_DEVICES_L, 738 .rst_set_reg = RST_DEVICES_SET_L, 739 .rst_clr_reg = RST_DEVICES_CLR_L, 740}; 741 742static struct tegra_clk_periph_regs periph_h_regs = { 743 .enb_reg = CLK_OUT_ENB_H, 744 .enb_set_reg = CLK_OUT_ENB_SET_H, 745 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 746 .rst_reg = RST_DEVICES_H, 747 .rst_set_reg = RST_DEVICES_SET_H, 748 .rst_clr_reg = RST_DEVICES_CLR_H, 749}; 750 751static struct tegra_clk_periph_regs periph_u_regs = { 752 .enb_reg = CLK_OUT_ENB_U, 753 .enb_set_reg = CLK_OUT_ENB_SET_U, 754 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 755 .rst_reg = RST_DEVICES_U, 756 .rst_set_reg = RST_DEVICES_SET_U, 757 .rst_clr_reg = RST_DEVICES_CLR_U, 758}; 759 760static struct tegra_clk_periph_regs periph_v_regs = { 761 .enb_reg = CLK_OUT_ENB_V, 762 .enb_set_reg = CLK_OUT_ENB_SET_V, 763 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 764 .rst_reg = RST_DEVICES_V, 765 .rst_set_reg = RST_DEVICES_SET_V, 766 .rst_clr_reg = RST_DEVICES_CLR_V, 767}; 768 769static struct tegra_clk_periph_regs periph_w_regs = { 770 .enb_reg = CLK_OUT_ENB_W, 771 .enb_set_reg = CLK_OUT_ENB_SET_W, 772 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 773 .rst_reg = RST_DEVICES_W, 774 .rst_set_reg = RST_DEVICES_SET_W, 775 .rst_clr_reg = RST_DEVICES_CLR_W, 776}; 777 778/* possible OSC frequencies in Hz */ 779static unsigned long tegra114_input_freq[] = { 780 [0] = 13000000, 781 [1] = 16800000, 782 [4] = 19200000, 783 [5] = 38400000, 784 [8] = 12000000, 785 [9] = 48000000, 786 [12] = 260000000, 787}; 788 789#define MASK(x) (BIT(x) - 1) 790 791#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 792 _clk_num, _regs, _gate_flags, _clk_id) \ 793 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 794 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 795 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 796 _parents##_idx, 0) 797 798#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 799 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 800 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 801 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 802 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 803 _parents##_idx, flags) 804 805#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 806 _clk_num, _regs, _gate_flags, _clk_id) \ 807 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 808 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \ 809 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 810 _parents##_idx, 0) 811 812#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 813 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 814 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 815 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 816 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 817 _clk_id, _parents##_idx, flags) 818 819#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 820 _clk_num, _regs, _gate_flags, _clk_id) \ 821 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 822 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 823 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 824 _clk_id, _parents##_idx, 0) 825 826#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 827 _clk_num, _regs, _clk_id) \ 828 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 829 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\ 830 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \ 831 _parents##_idx, 0) 832 833#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 834 _clk_num, _regs, _clk_id) \ 835 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 836 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \ 837 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 838 839#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 840 _mux_shift, _mux_mask, _clk_num, _regs, \ 841 _gate_flags, _clk_id) \ 842 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 843 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 844 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 845 _clk_id, _parents##_idx, 0) 846 847#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 848 _clk_num, _regs, _gate_flags, _clk_id) \ 849 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 850 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 851 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 852 _clk_id, _parents##_idx, 0) 853 854#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 855 _regs, _gate_flags, _clk_id) \ 856 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 857 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \ 858 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 859 mux_d_audio_clk_idx, 0) 860 861struct utmi_clk_param { 862 /* Oscillator Frequency in KHz */ 863 u32 osc_frequency; 864 /* UTMIP PLL Enable Delay Count */ 865 u8 enable_delay_count; 866 /* UTMIP PLL Stable count */ 867 u8 stable_count; 868 /* UTMIP PLL Active delay count */ 869 u8 active_delay_count; 870 /* UTMIP PLL Xtal frequency count */ 871 u8 xtal_freq_count; 872}; 873 874static const struct utmi_clk_param utmi_parameters[] = { 875 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 876 .stable_count = 0x33, .active_delay_count = 0x05, 877 .xtal_freq_count = 0x7F}, 878 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 879 .stable_count = 0x4B, .active_delay_count = 0x06, 880 .xtal_freq_count = 0xBB}, 881 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 882 .stable_count = 0x2F, .active_delay_count = 0x04, 883 .xtal_freq_count = 0x76}, 884 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 885 .stable_count = 0x66, .active_delay_count = 0x09, 886 .xtal_freq_count = 0xFE}, 887 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 888 .stable_count = 0x41, .active_delay_count = 0x0A, 889 .xtal_freq_count = 0xA4}, 890}; 891 892/* peripheral mux definitions */ 893 894#define MUX_I2S_SPDIF(_id) \ 895static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 896 #_id, "pll_p",\ 897 "clk_m"}; 898MUX_I2S_SPDIF(audio0) 899MUX_I2S_SPDIF(audio1) 900MUX_I2S_SPDIF(audio2) 901MUX_I2S_SPDIF(audio3) 902MUX_I2S_SPDIF(audio4) 903MUX_I2S_SPDIF(audio) 904 905#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 906#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 907#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 908#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 909#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 910#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 911 912static const char *mux_pllp_pllc_pllm_clkm[] = { 913 "pll_p", "pll_c", "pll_m", "clk_m" 914}; 915#define mux_pllp_pllc_pllm_clkm_idx NULL 916 917static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 918#define mux_pllp_pllc_pllm_idx NULL 919 920static const char *mux_pllp_pllc_clk32_clkm[] = { 921 "pll_p", "pll_c", "clk_32k", "clk_m" 922}; 923#define mux_pllp_pllc_clk32_clkm_idx NULL 924 925static const char *mux_plla_pllc_pllp_clkm[] = { 926 "pll_a_out0", "pll_c", "pll_p", "clk_m" 927}; 928#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 929 930static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 931 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 932}; 933static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 934 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 935}; 936 937static const char *mux_pllp_clkm[] = { 938 "pll_p", "clk_m" 939}; 940static u32 mux_pllp_clkm_idx[] = { 941 [0] = 0, [1] = 3, 942}; 943 944static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 945 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 946}; 947#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 948 949static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 950 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 951 "pll_d2_out0", "clk_m" 952}; 953#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 954 955static const char *mux_pllm_pllc_pllp_plla[] = { 956 "pll_m", "pll_c", "pll_p", "pll_a_out0" 957}; 958#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 959 960static const char *mux_pllp_pllc_clkm[] = { 961 "pll_p", "pll_c", "pll_m" 962}; 963static u32 mux_pllp_pllc_clkm_idx[] = { 964 [0] = 0, [1] = 1, [2] = 3, 965}; 966 967static const char *mux_pllp_pllc_clkm_clk32[] = { 968 "pll_p", "pll_c", "clk_m", "clk_32k" 969}; 970#define mux_pllp_pllc_clkm_clk32_idx NULL 971 972static const char *mux_plla_clk32_pllp_clkm_plle[] = { 973 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 974}; 975#define mux_plla_clk32_pllp_clkm_plle_idx NULL 976 977static const char *mux_clkm_pllp_pllc_pllre[] = { 978 "clk_m", "pll_p", "pll_c", "pll_re_out" 979}; 980static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 981 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 982}; 983 984static const char *mux_clkm_48M_pllp_480M[] = { 985 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 986}; 987#define mux_clkm_48M_pllp_480M_idx NULL 988 989static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 990 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 991}; 992static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 993 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 994}; 995 996static const char *mux_plld_out0_plld2_out0[] = { 997 "pll_d_out0", "pll_d2_out0", 998}; 999#define mux_plld_out0_plld2_out0_idx NULL 1000 1001static const char *mux_d_audio_clk[] = { 1002 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 1003 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1004}; 1005static u32 mux_d_audio_clk_idx[] = { 1006 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 1007 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 1008}; 1009 1010static const char *mux_pllmcp_clkm[] = { 1011 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 1012}; 1013 1014static const struct clk_div_table pll_re_div_table[] = { 1015 { .val = 0, .div = 1 }, 1016 { .val = 1, .div = 2 }, 1017 { .val = 2, .div = 3 }, 1018 { .val = 3, .div = 4 }, 1019 { .val = 4, .div = 5 }, 1020 { .val = 5, .div = 6 }, 1021 { .val = 0, .div = 0 }, 1022}; 1023 1024static struct clk *clks[TEGRA114_CLK_CLK_MAX]; 1025static struct clk_onecell_data clk_data; 1026 1027static unsigned long osc_freq; 1028static unsigned long pll_ref_freq; 1029 1030static int __init tegra114_osc_clk_init(void __iomem *clk_base) 1031{ 1032 struct clk *clk; 1033 u32 val, pll_ref_div; 1034 1035 val = readl_relaxed(clk_base + OSC_CTRL); 1036 1037 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; 1038 if (!osc_freq) { 1039 WARN_ON(1); 1040 return -EINVAL; 1041 } 1042 1043 /* clk_m */ 1044 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1045 osc_freq); 1046 clk_register_clkdev(clk, "clk_m", NULL); 1047 clks[TEGRA114_CLK_CLK_M] = clk; 1048 1049 /* pll_ref */ 1050 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 1051 pll_ref_div = 1 << val; 1052 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1053 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1054 clk_register_clkdev(clk, "pll_ref", NULL); 1055 clks[TEGRA114_CLK_PLL_REF] = clk; 1056 1057 pll_ref_freq = osc_freq / pll_ref_div; 1058 1059 return 0; 1060} 1061 1062static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 1063{ 1064 struct clk *clk; 1065 1066 /* clk_32k */ 1067 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1068 32768); 1069 clk_register_clkdev(clk, "clk_32k", NULL); 1070 clks[TEGRA114_CLK_CLK_32K] = clk; 1071 1072 /* clk_m_div2 */ 1073 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1074 CLK_SET_RATE_PARENT, 1, 2); 1075 clk_register_clkdev(clk, "clk_m_div2", NULL); 1076 clks[TEGRA114_CLK_CLK_M_DIV2] = clk; 1077 1078 /* clk_m_div4 */ 1079 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1080 CLK_SET_RATE_PARENT, 1, 4); 1081 clk_register_clkdev(clk, "clk_m_div4", NULL); 1082 clks[TEGRA114_CLK_CLK_M_DIV4] = clk; 1083 1084} 1085 1086static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 1087{ 1088 u32 reg; 1089 int i; 1090 1091 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1092 if (osc_freq == utmi_parameters[i].osc_frequency) 1093 break; 1094 } 1095 1096 if (i >= ARRAY_SIZE(utmi_parameters)) { 1097 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1098 osc_freq); 1099 return; 1100 } 1101 1102 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1103 1104 /* Program UTMIP PLL stable and active counts */ 1105 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1106 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1107 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1108 1109 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1110 1111 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1112 active_delay_count); 1113 1114 /* Remove power downs from UTMIP PLL control bits */ 1115 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1116 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1117 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1118 1119 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1120 1121 /* Program UTMIP PLL delay and oscillator frequency counts */ 1122 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1123 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1124 1125 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1126 enable_delay_count); 1127 1128 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1129 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1130 xtal_freq_count); 1131 1132 /* Remove power downs from UTMIP PLL control bits */ 1133 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1134 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1135 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1136 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1137 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1138 1139 /* Setup HW control of UTMIPLL */ 1140 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1141 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1142 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1143 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1144 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1145 1146 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1147 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1148 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1149 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1150 1151 udelay(1); 1152 1153 /* Setup SW override of UTMIPLL assuming USB2.0 1154 ports are assigned to USB2 */ 1155 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1156 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1157 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1158 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1159 1160 udelay(1); 1161 1162 /* Enable HW control UTMIPLL */ 1163 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1164 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1165 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1166} 1167 1168static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params) 1169{ 1170 pll_params->vco_min = 1171 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq; 1172} 1173 1174static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1175 void __iomem *clk_base) 1176{ 1177 u32 val; 1178 u32 step_a, step_b; 1179 1180 switch (pll_ref_freq) { 1181 case 12000000: 1182 case 13000000: 1183 case 26000000: 1184 step_a = 0x2B; 1185 step_b = 0x0B; 1186 break; 1187 case 16800000: 1188 step_a = 0x1A; 1189 step_b = 0x09; 1190 break; 1191 case 19200000: 1192 step_a = 0x12; 1193 step_b = 0x08; 1194 break; 1195 default: 1196 pr_err("%s: Unexpected reference rate %lu\n", 1197 __func__, pll_ref_freq); 1198 WARN_ON(1); 1199 return -EINVAL; 1200 } 1201 1202 val = step_a << pll_params->stepa_shift; 1203 val |= step_b << pll_params->stepb_shift; 1204 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1205 1206 return 0; 1207} 1208 1209static void __init _init_iddq(struct tegra_clk_pll_params *pll_params, 1210 void __iomem *clk_base) 1211{ 1212 u32 val, val_iddq; 1213 1214 val = readl_relaxed(clk_base + pll_params->base_reg); 1215 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1216 1217 if (val & BIT(30)) 1218 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1219 else { 1220 val_iddq |= BIT(pll_params->iddq_bit_idx); 1221 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1222 } 1223} 1224 1225static void __init tegra114_pll_init(void __iomem *clk_base, 1226 void __iomem *pmc) 1227{ 1228 u32 val; 1229 struct clk *clk; 1230 1231 /* PLLC */ 1232 _clip_vco_min(&pll_c_params); 1233 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1234 _init_iddq(&pll_c_params, clk_base); 1235 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1236 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1237 pll_c_freq_table, NULL); 1238 clk_register_clkdev(clk, "pll_c", NULL); 1239 clks[TEGRA114_CLK_PLL_C] = clk; 1240 1241 /* PLLC_OUT1 */ 1242 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1243 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1244 8, 8, 1, NULL); 1245 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1246 clk_base + PLLC_OUT, 1, 0, 1247 CLK_SET_RATE_PARENT, 0, NULL); 1248 clk_register_clkdev(clk, "pll_c_out1", NULL); 1249 clks[TEGRA114_CLK_PLL_C_OUT1] = clk; 1250 } 1251 1252 /* PLLC2 */ 1253 _clip_vco_min(&pll_c2_params); 1254 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1255 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1256 pll_cx_freq_table, NULL); 1257 clk_register_clkdev(clk, "pll_c2", NULL); 1258 clks[TEGRA114_CLK_PLL_C2] = clk; 1259 1260 /* PLLC3 */ 1261 _clip_vco_min(&pll_c3_params); 1262 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1263 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1264 pll_cx_freq_table, NULL); 1265 clk_register_clkdev(clk, "pll_c3", NULL); 1266 clks[TEGRA114_CLK_PLL_C3] = clk; 1267 1268 /* PLLP */ 1269 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, 1270 408000000, &pll_p_params, 1271 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 1272 pll_p_freq_table, NULL); 1273 clk_register_clkdev(clk, "pll_p", NULL); 1274 clks[TEGRA114_CLK_PLL_P] = clk; 1275 1276 /* PLLP_OUT1 */ 1277 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 1278 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1279 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1280 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 1281 clk_base + PLLP_OUTA, 1, 0, 1282 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1283 &pll_div_lock); 1284 clk_register_clkdev(clk, "pll_p_out1", NULL); 1285 clks[TEGRA114_CLK_PLL_P_OUT1] = clk; 1286 1287 /* PLLP_OUT2 */ 1288 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 1289 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1290 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, 1291 8, 1, &pll_div_lock); 1292 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 1293 clk_base + PLLP_OUTA, 17, 16, 1294 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1295 &pll_div_lock); 1296 clk_register_clkdev(clk, "pll_p_out2", NULL); 1297 clks[TEGRA114_CLK_PLL_P_OUT2] = clk; 1298 1299 /* PLLP_OUT3 */ 1300 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 1301 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1302 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1303 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 1304 clk_base + PLLP_OUTB, 1, 0, 1305 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1306 &pll_div_lock); 1307 clk_register_clkdev(clk, "pll_p_out3", NULL); 1308 clks[TEGRA114_CLK_PLL_P_OUT3] = clk; 1309 1310 /* PLLP_OUT4 */ 1311 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 1312 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1313 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1314 &pll_div_lock); 1315 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 1316 clk_base + PLLP_OUTB, 17, 16, 1317 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1318 &pll_div_lock); 1319 clk_register_clkdev(clk, "pll_p_out4", NULL); 1320 clks[TEGRA114_CLK_PLL_P_OUT4] = clk; 1321 1322 /* PLLM */ 1323 _clip_vco_min(&pll_m_params); 1324 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1325 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1326 &pll_m_params, TEGRA_PLL_USE_LOCK, 1327 pll_m_freq_table, NULL); 1328 clk_register_clkdev(clk, "pll_m", NULL); 1329 clks[TEGRA114_CLK_PLL_M] = clk; 1330 1331 /* PLLM_OUT1 */ 1332 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1333 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1334 8, 8, 1, NULL); 1335 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1336 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1337 CLK_SET_RATE_PARENT, 0, NULL); 1338 clk_register_clkdev(clk, "pll_m_out1", NULL); 1339 clks[TEGRA114_CLK_PLL_M_OUT1] = clk; 1340 1341 /* PLLM_UD */ 1342 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1343 CLK_SET_RATE_PARENT, 1, 1); 1344 1345 /* PLLX */ 1346 _clip_vco_min(&pll_x_params); 1347 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) { 1348 _init_iddq(&pll_x_params, clk_base); 1349 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, 1350 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params, 1351 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL); 1352 clk_register_clkdev(clk, "pll_x", NULL); 1353 clks[TEGRA114_CLK_PLL_X] = clk; 1354 } 1355 1356 /* PLLX_OUT0 */ 1357 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 1358 CLK_SET_RATE_PARENT, 1, 2); 1359 clk_register_clkdev(clk, "pll_x_out0", NULL); 1360 clks[TEGRA114_CLK_PLL_X_OUT0] = clk; 1361 1362 /* PLLU */ 1363 val = readl(clk_base + pll_u_params.base_reg); 1364 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1365 writel(val, clk_base + pll_u_params.base_reg); 1366 1367 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1368 0, &pll_u_params, TEGRA_PLLU | 1369 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1370 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock); 1371 clk_register_clkdev(clk, "pll_u", NULL); 1372 clks[TEGRA114_CLK_PLL_U] = clk; 1373 1374 tegra114_utmi_param_configure(clk_base); 1375 1376 /* PLLU_480M */ 1377 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1378 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1379 22, 0, &pll_u_lock); 1380 clk_register_clkdev(clk, "pll_u_480M", NULL); 1381 clks[TEGRA114_CLK_PLL_U_480M] = clk; 1382 1383 /* PLLU_60M */ 1384 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1385 CLK_SET_RATE_PARENT, 1, 8); 1386 clk_register_clkdev(clk, "pll_u_60M", NULL); 1387 clks[TEGRA114_CLK_PLL_U_60M] = clk; 1388 1389 /* PLLU_48M */ 1390 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1391 CLK_SET_RATE_PARENT, 1, 10); 1392 clk_register_clkdev(clk, "pll_u_48M", NULL); 1393 clks[TEGRA114_CLK_PLL_U_48M] = clk; 1394 1395 /* PLLU_12M */ 1396 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1397 CLK_SET_RATE_PARENT, 1, 40); 1398 clk_register_clkdev(clk, "pll_u_12M", NULL); 1399 clks[TEGRA114_CLK_PLL_U_12M] = clk; 1400 1401 /* PLLD */ 1402 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1403 0, &pll_d_params, 1404 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1405 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock); 1406 clk_register_clkdev(clk, "pll_d", NULL); 1407 clks[TEGRA114_CLK_PLL_D] = clk; 1408 1409 /* PLLD_OUT0 */ 1410 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1411 CLK_SET_RATE_PARENT, 1, 2); 1412 clk_register_clkdev(clk, "pll_d_out0", NULL); 1413 clks[TEGRA114_CLK_PLL_D_OUT0] = clk; 1414 1415 /* PLLD2 */ 1416 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1417 0, &pll_d2_params, 1418 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1419 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock); 1420 clk_register_clkdev(clk, "pll_d2", NULL); 1421 clks[TEGRA114_CLK_PLL_D2] = clk; 1422 1423 /* PLLD2_OUT0 */ 1424 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1425 CLK_SET_RATE_PARENT, 1, 2); 1426 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1427 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk; 1428 1429 /* PLLA */ 1430 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, 1431 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1432 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1433 clk_register_clkdev(clk, "pll_a", NULL); 1434 clks[TEGRA114_CLK_PLL_A] = clk; 1435 1436 /* PLLA_OUT0 */ 1437 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1438 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1439 8, 8, 1, NULL); 1440 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1441 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1442 CLK_SET_RATE_PARENT, 0, NULL); 1443 clk_register_clkdev(clk, "pll_a_out0", NULL); 1444 clks[TEGRA114_CLK_PLL_A_OUT0] = clk; 1445 1446 /* PLLRE */ 1447 _clip_vco_min(&pll_re_vco_params); 1448 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1449 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1450 NULL, &pll_re_lock, pll_ref_freq); 1451 clk_register_clkdev(clk, "pll_re_vco", NULL); 1452 clks[TEGRA114_CLK_PLL_RE_VCO] = clk; 1453 1454 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1455 clk_base + PLLRE_BASE, 16, 4, 0, 1456 pll_re_div_table, &pll_re_lock); 1457 clk_register_clkdev(clk, "pll_re_out", NULL); 1458 clks[TEGRA114_CLK_PLL_RE_OUT] = clk; 1459 1460 /* PLLE */ 1461 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1462 clk_base, 0, 100000000, &pll_e_params, 1463 pll_e_freq_table, NULL); 1464 clk_register_clkdev(clk, "pll_e_out0", NULL); 1465 clks[TEGRA114_CLK_PLL_E_OUT0] = clk; 1466} 1467 1468static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1469 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1470}; 1471 1472static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1473 "clk_m_div4", "extern1", 1474}; 1475 1476static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1477 "clk_m_div4", "extern2", 1478}; 1479 1480static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1481 "clk_m_div4", "extern3", 1482}; 1483 1484static void __init tegra114_audio_clk_init(void __iomem *clk_base) 1485{ 1486 struct clk *clk; 1487 1488 /* spdif_in_sync */ 1489 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1490 24000000); 1491 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1492 clks[TEGRA114_CLK_SPDIF_IN_SYNC] = clk; 1493 1494 /* i2s0_sync */ 1495 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1496 clk_register_clkdev(clk, "i2s0_sync", NULL); 1497 clks[TEGRA114_CLK_I2S0_SYNC] = clk; 1498 1499 /* i2s1_sync */ 1500 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1501 clk_register_clkdev(clk, "i2s1_sync", NULL); 1502 clks[TEGRA114_CLK_I2S1_SYNC] = clk; 1503 1504 /* i2s2_sync */ 1505 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1506 clk_register_clkdev(clk, "i2s2_sync", NULL); 1507 clks[TEGRA114_CLK_I2S2_SYNC] = clk; 1508 1509 /* i2s3_sync */ 1510 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1511 clk_register_clkdev(clk, "i2s3_sync", NULL); 1512 clks[TEGRA114_CLK_I2S3_SYNC] = clk; 1513 1514 /* i2s4_sync */ 1515 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1516 clk_register_clkdev(clk, "i2s4_sync", NULL); 1517 clks[TEGRA114_CLK_I2S4_SYNC] = clk; 1518 1519 /* vimclk_sync */ 1520 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1521 clk_register_clkdev(clk, "vimclk_sync", NULL); 1522 clks[TEGRA114_CLK_VIMCLK_SYNC] = clk; 1523 1524 /* audio0 */ 1525 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1526 ARRAY_SIZE(mux_audio_sync_clk), 1527 CLK_SET_RATE_NO_REPARENT, 1528 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1529 NULL); 1530 clks[TEGRA114_CLK_AUDIO0_MUX] = clk; 1531 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1532 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1533 CLK_GATE_SET_TO_DISABLE, NULL); 1534 clk_register_clkdev(clk, "audio0", NULL); 1535 clks[TEGRA114_CLK_AUDIO0] = clk; 1536 1537 /* audio1 */ 1538 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1539 ARRAY_SIZE(mux_audio_sync_clk), 1540 CLK_SET_RATE_NO_REPARENT, 1541 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1542 NULL); 1543 clks[TEGRA114_CLK_AUDIO1_MUX] = clk; 1544 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1545 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1546 CLK_GATE_SET_TO_DISABLE, NULL); 1547 clk_register_clkdev(clk, "audio1", NULL); 1548 clks[TEGRA114_CLK_AUDIO1] = clk; 1549 1550 /* audio2 */ 1551 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1552 ARRAY_SIZE(mux_audio_sync_clk), 1553 CLK_SET_RATE_NO_REPARENT, 1554 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1555 NULL); 1556 clks[TEGRA114_CLK_AUDIO2_MUX] = clk; 1557 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1558 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1559 CLK_GATE_SET_TO_DISABLE, NULL); 1560 clk_register_clkdev(clk, "audio2", NULL); 1561 clks[TEGRA114_CLK_AUDIO2] = clk; 1562 1563 /* audio3 */ 1564 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1565 ARRAY_SIZE(mux_audio_sync_clk), 1566 CLK_SET_RATE_NO_REPARENT, 1567 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1568 NULL); 1569 clks[TEGRA114_CLK_AUDIO3_MUX] = clk; 1570 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1571 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1572 CLK_GATE_SET_TO_DISABLE, NULL); 1573 clk_register_clkdev(clk, "audio3", NULL); 1574 clks[TEGRA114_CLK_AUDIO3] = clk; 1575 1576 /* audio4 */ 1577 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1578 ARRAY_SIZE(mux_audio_sync_clk), 1579 CLK_SET_RATE_NO_REPARENT, 1580 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1581 NULL); 1582 clks[TEGRA114_CLK_AUDIO4_MUX] = clk; 1583 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1584 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1585 CLK_GATE_SET_TO_DISABLE, NULL); 1586 clk_register_clkdev(clk, "audio4", NULL); 1587 clks[TEGRA114_CLK_AUDIO4] = clk; 1588 1589 /* spdif */ 1590 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1591 ARRAY_SIZE(mux_audio_sync_clk), 1592 CLK_SET_RATE_NO_REPARENT, 1593 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1594 NULL); 1595 clks[TEGRA114_CLK_SPDIF_MUX] = clk; 1596 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1597 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1598 CLK_GATE_SET_TO_DISABLE, NULL); 1599 clk_register_clkdev(clk, "spdif", NULL); 1600 clks[TEGRA114_CLK_SPDIF] = clk; 1601 1602 /* audio0_2x */ 1603 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1604 CLK_SET_RATE_PARENT, 2, 1); 1605 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1606 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 1607 0, &clk_doubler_lock); 1608 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1609 TEGRA_PERIPH_NO_RESET, clk_base, 1610 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1611 periph_clk_enb_refcnt); 1612 clk_register_clkdev(clk, "audio0_2x", NULL); 1613 clks[TEGRA114_CLK_AUDIO0_2X] = clk; 1614 1615 /* audio1_2x */ 1616 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1617 CLK_SET_RATE_PARENT, 2, 1); 1618 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1619 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 1620 0, &clk_doubler_lock); 1621 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1622 TEGRA_PERIPH_NO_RESET, clk_base, 1623 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1624 periph_clk_enb_refcnt); 1625 clk_register_clkdev(clk, "audio1_2x", NULL); 1626 clks[TEGRA114_CLK_AUDIO1_2X] = clk; 1627 1628 /* audio2_2x */ 1629 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1630 CLK_SET_RATE_PARENT, 2, 1); 1631 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1632 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 1633 0, &clk_doubler_lock); 1634 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1635 TEGRA_PERIPH_NO_RESET, clk_base, 1636 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1637 periph_clk_enb_refcnt); 1638 clk_register_clkdev(clk, "audio2_2x", NULL); 1639 clks[TEGRA114_CLK_AUDIO2_2X] = clk; 1640 1641 /* audio3_2x */ 1642 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1643 CLK_SET_RATE_PARENT, 2, 1); 1644 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1645 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 1646 0, &clk_doubler_lock); 1647 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1648 TEGRA_PERIPH_NO_RESET, clk_base, 1649 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1650 periph_clk_enb_refcnt); 1651 clk_register_clkdev(clk, "audio3_2x", NULL); 1652 clks[TEGRA114_CLK_AUDIO3_2X] = clk; 1653 1654 /* audio4_2x */ 1655 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1656 CLK_SET_RATE_PARENT, 2, 1); 1657 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1658 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 1659 0, &clk_doubler_lock); 1660 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1661 TEGRA_PERIPH_NO_RESET, clk_base, 1662 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1663 periph_clk_enb_refcnt); 1664 clk_register_clkdev(clk, "audio4_2x", NULL); 1665 clks[TEGRA114_CLK_AUDIO4_2X] = clk; 1666 1667 /* spdif_2x */ 1668 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1669 CLK_SET_RATE_PARENT, 2, 1); 1670 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1671 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 1672 0, &clk_doubler_lock); 1673 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1674 TEGRA_PERIPH_NO_RESET, clk_base, 1675 CLK_SET_RATE_PARENT, 118, 1676 &periph_v_regs, periph_clk_enb_refcnt); 1677 clk_register_clkdev(clk, "spdif_2x", NULL); 1678 clks[TEGRA114_CLK_SPDIF_2X] = clk; 1679} 1680 1681static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1682{ 1683 struct clk *clk; 1684 1685 /* clk_out_1 */ 1686 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1687 ARRAY_SIZE(clk_out1_parents), 1688 CLK_SET_RATE_NO_REPARENT, 1689 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1690 &clk_out_lock); 1691 clks[TEGRA114_CLK_CLK_OUT_1_MUX] = clk; 1692 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1693 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1694 &clk_out_lock); 1695 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1696 clks[TEGRA114_CLK_CLK_OUT_1] = clk; 1697 1698 /* clk_out_2 */ 1699 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1700 ARRAY_SIZE(clk_out2_parents), 1701 CLK_SET_RATE_NO_REPARENT, 1702 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1703 &clk_out_lock); 1704 clks[TEGRA114_CLK_CLK_OUT_2_MUX] = clk; 1705 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1706 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1707 &clk_out_lock); 1708 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1709 clks[TEGRA114_CLK_CLK_OUT_2] = clk; 1710 1711 /* clk_out_3 */ 1712 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1713 ARRAY_SIZE(clk_out3_parents), 1714 CLK_SET_RATE_NO_REPARENT, 1715 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1716 &clk_out_lock); 1717 clks[TEGRA114_CLK_CLK_OUT_3_MUX] = clk; 1718 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1719 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1720 &clk_out_lock); 1721 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1722 clks[TEGRA114_CLK_CLK_OUT_3] = clk; 1723 1724 /* blink */ 1725 /* clear the blink timer register to directly output clk_32k */ 1726 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1727 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1728 pmc_base + PMC_DPD_PADS_ORIDE, 1729 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1730 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1731 pmc_base + PMC_CTRL, 1732 PMC_CTRL_BLINK_ENB, 0, NULL); 1733 clk_register_clkdev(clk, "blink", NULL); 1734 clks[TEGRA114_CLK_BLINK] = clk; 1735 1736} 1737 1738static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1739 "pll_p", "pll_p_out2", "unused", 1740 "clk_32k", "pll_m_out1" }; 1741 1742static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1743 "pll_p", "pll_p_out4", "unused", 1744 "unused", "pll_x" }; 1745 1746static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1747 "pll_p", "pll_p_out4", "unused", 1748 "unused", "pll_x", "pll_x_out0" }; 1749 1750static void __init tegra114_super_clk_init(void __iomem *clk_base) 1751{ 1752 struct clk *clk; 1753 1754 /* CCLKG */ 1755 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1756 ARRAY_SIZE(cclk_g_parents), 1757 CLK_SET_RATE_PARENT, 1758 clk_base + CCLKG_BURST_POLICY, 1759 0, 4, 0, 0, NULL); 1760 clk_register_clkdev(clk, "cclk_g", NULL); 1761 clks[TEGRA114_CLK_CCLK_G] = clk; 1762 1763 /* CCLKLP */ 1764 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1765 ARRAY_SIZE(cclk_lp_parents), 1766 CLK_SET_RATE_PARENT, 1767 clk_base + CCLKLP_BURST_POLICY, 1768 0, 4, 8, 9, NULL); 1769 clk_register_clkdev(clk, "cclk_lp", NULL); 1770 clks[TEGRA114_CLK_CCLK_LP] = clk; 1771 1772 /* SCLK */ 1773 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1774 ARRAY_SIZE(sclk_parents), 1775 CLK_SET_RATE_PARENT, 1776 clk_base + SCLK_BURST_POLICY, 1777 0, 4, 0, 0, NULL); 1778 clk_register_clkdev(clk, "sclk", NULL); 1779 clks[TEGRA114_CLK_SCLK] = clk; 1780 1781 /* HCLK */ 1782 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1783 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1784 &sysrate_lock); 1785 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | 1786 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1787 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1788 clk_register_clkdev(clk, "hclk", NULL); 1789 clks[TEGRA114_CLK_HCLK] = clk; 1790 1791 /* PCLK */ 1792 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1793 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1794 &sysrate_lock); 1795 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 1796 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1797 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1798 clk_register_clkdev(clk, "pclk", NULL); 1799 clks[TEGRA114_CLK_PCLK] = clk; 1800} 1801 1802static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1803 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S0), 1804 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S1), 1805 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S2), 1806 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S3), 1807 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2S4), 1808 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_OUT), 1809 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SPDIF_IN), 1810 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_PWM), 1811 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_ADX), 1812 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_AMX), 1813 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA), 1814 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_HDA2CODEC_2X), 1815 TEGRA_INIT_DATA_MUX8("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC1), 1816 TEGRA_INIT_DATA_MUX8("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC2), 1817 TEGRA_INIT_DATA_MUX8("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC3), 1818 TEGRA_INIT_DATA_MUX8("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC4), 1819 TEGRA_INIT_DATA_MUX8("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC5), 1820 TEGRA_INIT_DATA_MUX8("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SBC6), 1821 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), 1822 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_NDSPEED), 1823 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_VFIR), 1824 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, TEGRA114_CLK_SDMMC1), 1825 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, TEGRA114_CLK_SDMMC2), 1826 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, TEGRA114_CLK_SDMMC3), 1827 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, TEGRA114_CLK_SDMMC4), 1828 TEGRA_INIT_DATA_INT8("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, TEGRA114_CLK_VDE), 1829 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_CSITE, CLK_IGNORE_UNUSED), 1830 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_LA), 1831 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TRACE), 1832 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_OWR), 1833 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, TEGRA114_CLK_NOR), 1834 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_MIPI), 1835 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA114_CLK_I2C1), 1836 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA114_CLK_I2C2), 1837 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA114_CLK_I2C3), 1838 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA114_CLK_I2C4), 1839 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA114_CLK_I2C5), 1840 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, TEGRA114_CLK_UARTA), 1841 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, TEGRA114_CLK_UARTB), 1842 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, TEGRA114_CLK_UARTC), 1843 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, TEGRA114_CLK_UARTD), 1844 TEGRA_INIT_DATA_INT8("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, TEGRA114_CLK_GR_3D), 1845 TEGRA_INIT_DATA_INT8("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, TEGRA114_CLK_GR_2D), 1846 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR), 1847 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, TEGRA114_CLK_VI), 1848 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, TEGRA114_CLK_EPP), 1849 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, TEGRA114_CLK_MSENC), 1850 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, TEGRA114_CLK_TSEC), 1851 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, TEGRA114_CLK_HOST1X), 1852 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, TEGRA114_CLK_HDMI), 1853 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, TEGRA114_CLK_CILAB), 1854 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, TEGRA114_CLK_CILCD), 1855 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, TEGRA114_CLK_CILE), 1856 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, TEGRA114_CLK_DSIALP), 1857 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, TEGRA114_CLK_DSIBLP), 1858 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_TSENSOR), 1859 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, TEGRA114_CLK_ACTMON), 1860 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, TEGRA114_CLK_EXTERN1), 1861 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, TEGRA114_CLK_EXTERN2), 1862 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, TEGRA114_CLK_EXTERN3), 1863 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_I2CSLOW), 1864 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SE), 1865 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, TEGRA114_CLK_MSELECT, CLK_IGNORE_UNUSED), 1866 TEGRA_INIT_DATA_MUX("dfll_ref", "ref", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_REF), 1867 TEGRA_INIT_DATA_MUX("dfll_soc", "soc", "t114_dfll", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, &periph_w_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DFLL_SOC), 1868 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_SOC_THERM), 1869 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_HOST_SRC), 1870 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FALCON_SRC), 1871 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_FS_SRC), 1872 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_SS_SRC), 1873 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_XUSB_DEV_SRC), 1874 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_D_AUDIO), 1875 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM0), 1876 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM1), 1877 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, TEGRA114_CLK_DAM2), 1878}; 1879 1880static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1881 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, TEGRA114_CLK_DISP1), 1882 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, TEGRA114_CLK_DISP2), 1883}; 1884 1885static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1886{ 1887 struct tegra_periph_init_data *data; 1888 struct clk *clk; 1889 int i; 1890 u32 val; 1891 1892 /* apbdma */ 1893 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1894 0, 34, &periph_h_regs, 1895 periph_clk_enb_refcnt); 1896 clks[TEGRA114_CLK_APBDMA] = clk; 1897 1898 /* rtc */ 1899 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1900 TEGRA_PERIPH_ON_APB | 1901 TEGRA_PERIPH_NO_RESET, clk_base, 1902 0, 4, &periph_l_regs, 1903 periph_clk_enb_refcnt); 1904 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1905 clks[TEGRA114_CLK_RTC] = clk; 1906 1907 /* kbc */ 1908 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1909 TEGRA_PERIPH_ON_APB | 1910 TEGRA_PERIPH_NO_RESET, clk_base, 1911 0, 36, &periph_h_regs, 1912 periph_clk_enb_refcnt); 1913 clks[TEGRA114_CLK_KBC] = clk; 1914 1915 /* timer */ 1916 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1917 0, 5, &periph_l_regs, 1918 periph_clk_enb_refcnt); 1919 clk_register_clkdev(clk, NULL, "timer"); 1920 clks[TEGRA114_CLK_TIMER] = clk; 1921 1922 /* kfuse */ 1923 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1924 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1925 &periph_h_regs, periph_clk_enb_refcnt); 1926 clks[TEGRA114_CLK_KFUSE] = clk; 1927 1928 /* fuse */ 1929 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1930 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1931 &periph_h_regs, periph_clk_enb_refcnt); 1932 clks[TEGRA114_CLK_FUSE] = clk; 1933 1934 /* fuse_burn */ 1935 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1936 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1937 &periph_h_regs, periph_clk_enb_refcnt); 1938 clks[TEGRA114_CLK_FUSE_BURN] = clk; 1939 1940 /* apbif */ 1941 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1942 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1943 &periph_v_regs, periph_clk_enb_refcnt); 1944 clks[TEGRA114_CLK_APBIF] = clk; 1945 1946 /* hda2hdmi */ 1947 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1948 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1949 &periph_w_regs, periph_clk_enb_refcnt); 1950 clks[TEGRA114_CLK_HDA2HDMI] = clk; 1951 1952 /* vcp */ 1953 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1954 29, &periph_l_regs, 1955 periph_clk_enb_refcnt); 1956 clks[TEGRA114_CLK_VCP] = clk; 1957 1958 /* bsea */ 1959 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 1960 0, 62, &periph_h_regs, 1961 periph_clk_enb_refcnt); 1962 clks[TEGRA114_CLK_BSEA] = clk; 1963 1964 /* bsev */ 1965 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 1966 0, 63, &periph_h_regs, 1967 periph_clk_enb_refcnt); 1968 clks[TEGRA114_CLK_BSEV] = clk; 1969 1970 /* mipi-cal */ 1971 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1972 0, 56, &periph_h_regs, 1973 periph_clk_enb_refcnt); 1974 clks[TEGRA114_CLK_MIPI_CAL] = clk; 1975 1976 /* usbd */ 1977 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 1978 0, 22, &periph_l_regs, 1979 periph_clk_enb_refcnt); 1980 clks[TEGRA114_CLK_USBD] = clk; 1981 1982 /* usb2 */ 1983 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 1984 0, 58, &periph_h_regs, 1985 periph_clk_enb_refcnt); 1986 clks[TEGRA114_CLK_USB2] = clk; 1987 1988 /* usb3 */ 1989 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 1990 0, 59, &periph_h_regs, 1991 periph_clk_enb_refcnt); 1992 clks[TEGRA114_CLK_USB3] = clk; 1993 1994 /* csi */ 1995 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1996 0, 52, &periph_h_regs, 1997 periph_clk_enb_refcnt); 1998 clks[TEGRA114_CLK_CSI] = clk; 1999 2000 /* isp */ 2001 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 2002 23, &periph_l_regs, 2003 periph_clk_enb_refcnt); 2004 clks[TEGRA114_CLK_ISP] = clk; 2005 2006 /* csus */ 2007 clk = tegra_clk_register_periph_gate("csus", "clk_m", 2008 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 2009 &periph_u_regs, periph_clk_enb_refcnt); 2010 clks[TEGRA114_CLK_CSUS] = clk; 2011 2012 /* dds */ 2013 clk = tegra_clk_register_periph_gate("dds", "clk_m", 2014 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 2015 &periph_w_regs, periph_clk_enb_refcnt); 2016 clks[TEGRA114_CLK_DDS] = clk; 2017 2018 /* dp2 */ 2019 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 2020 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 2021 &periph_w_regs, periph_clk_enb_refcnt); 2022 clks[TEGRA114_CLK_DP2] = clk; 2023 2024 /* dtv */ 2025 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 2026 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 2027 &periph_u_regs, periph_clk_enb_refcnt); 2028 clks[TEGRA114_CLK_DTV] = clk; 2029 2030 /* dsia */ 2031 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2032 ARRAY_SIZE(mux_plld_out0_plld2_out0), 2033 CLK_SET_RATE_NO_REPARENT, 2034 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2035 clks[TEGRA114_CLK_DSIA_MUX] = clk; 2036 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2037 0, 48, &periph_h_regs, 2038 periph_clk_enb_refcnt); 2039 clks[TEGRA114_CLK_DSIA] = clk; 2040 2041 /* dsib */ 2042 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2043 ARRAY_SIZE(mux_plld_out0_plld2_out0), 2044 CLK_SET_RATE_NO_REPARENT, 2045 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2046 clks[TEGRA114_CLK_DSIB_MUX] = clk; 2047 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2048 0, 82, &periph_u_regs, 2049 periph_clk_enb_refcnt); 2050 clks[TEGRA114_CLK_DSIB] = clk; 2051 2052 /* xusb_hs_src */ 2053 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); 2054 val |= BIT(25); /* always select PLLU_60M */ 2055 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); 2056 2057 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 2058 1, 1); 2059 clks[TEGRA114_CLK_XUSB_HS_SRC] = clk; 2060 2061 /* xusb_host */ 2062 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 2063 clk_base, 0, 89, &periph_u_regs, 2064 periph_clk_enb_refcnt); 2065 clks[TEGRA114_CLK_XUSB_HOST] = clk; 2066 2067 /* xusb_ss */ 2068 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 2069 clk_base, 0, 156, &periph_w_regs, 2070 periph_clk_enb_refcnt); 2071 clks[TEGRA114_CLK_XUSB_HOST] = clk; 2072 2073 /* xusb_dev */ 2074 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 2075 clk_base, 0, 95, &periph_u_regs, 2076 periph_clk_enb_refcnt); 2077 clks[TEGRA114_CLK_XUSB_DEV] = clk; 2078 2079 /* emc */ 2080 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2081 ARRAY_SIZE(mux_pllmcp_clkm), 2082 CLK_SET_RATE_NO_REPARENT, 2083 clk_base + CLK_SOURCE_EMC, 2084 29, 3, 0, NULL); 2085 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2086 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 2087 periph_clk_enb_refcnt); 2088 clks[TEGRA114_CLK_EMC] = clk; 2089 2090 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 2091 data = &tegra_periph_clk_list[i]; 2092 clk = tegra_clk_register_periph(data->name, data->parent_names, 2093 data->num_parents, &data->periph, 2094 clk_base, data->offset, data->flags); 2095 clks[data->clk_id] = clk; 2096 } 2097 2098 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 2099 data = &tegra_periph_nodiv_clk_list[i]; 2100 clk = tegra_clk_register_periph_nodiv(data->name, 2101 data->parent_names, data->num_parents, 2102 &data->periph, clk_base, data->offset); 2103 clks[data->clk_id] = clk; 2104 } 2105} 2106 2107/* Tegra114 CPU clock and reset control functions */ 2108static void tegra114_wait_cpu_in_reset(u32 cpu) 2109{ 2110 unsigned int reg; 2111 2112 do { 2113 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 2114 cpu_relax(); 2115 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 2116} 2117static void tegra114_disable_cpu_clock(u32 cpu) 2118{ 2119 /* flow controller would take care in the power sequence. */ 2120} 2121 2122#ifdef CONFIG_PM_SLEEP 2123static void tegra114_cpu_clock_suspend(void) 2124{ 2125 /* switch coresite to clk_m, save off original source */ 2126 tegra114_cpu_clk_sctx.clk_csite_src = 2127 readl(clk_base + CLK_SOURCE_CSITE); 2128 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 2129 2130 tegra114_cpu_clk_sctx.cclkg_burst = 2131 readl(clk_base + CCLKG_BURST_POLICY); 2132 tegra114_cpu_clk_sctx.cclkg_divider = 2133 readl(clk_base + CCLKG_BURST_POLICY + 4); 2134} 2135 2136static void tegra114_cpu_clock_resume(void) 2137{ 2138 writel(tegra114_cpu_clk_sctx.clk_csite_src, 2139 clk_base + CLK_SOURCE_CSITE); 2140 2141 writel(tegra114_cpu_clk_sctx.cclkg_burst, 2142 clk_base + CCLKG_BURST_POLICY); 2143 writel(tegra114_cpu_clk_sctx.cclkg_divider, 2144 clk_base + CCLKG_BURST_POLICY + 4); 2145} 2146#endif 2147 2148static struct tegra_cpu_car_ops tegra114_cpu_car_ops = { 2149 .wait_for_reset = tegra114_wait_cpu_in_reset, 2150 .disable_clock = tegra114_disable_cpu_clock, 2151#ifdef CONFIG_PM_SLEEP 2152 .suspend = tegra114_cpu_clock_suspend, 2153 .resume = tegra114_cpu_clock_resume, 2154#endif 2155}; 2156 2157static const struct of_device_id pmc_match[] __initconst = { 2158 { .compatible = "nvidia,tegra114-pmc" }, 2159 {}, 2160}; 2161 2162/* 2163 * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5 2164 * breaks 2165 */ 2166static struct tegra_clk_init_table init_table[] __initdata = { 2167 {TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0}, 2168 {TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0}, 2169 {TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0}, 2170 {TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0}, 2171 {TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1}, 2172 {TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1}, 2173 {TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1}, 2174 {TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1}, 2175 {TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1}, 2176 {TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2177 {TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2178 {TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2179 {TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2180 {TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0}, 2181 {TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1}, 2182 {TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1}, 2183 {TEGRA114_CLK_GR_2D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 2184 {TEGRA114_CLK_GR_3D, TEGRA114_CLK_PLL_C2, 300000000, 0}, 2185 2186 /* This MUST be the last entry. */ 2187 {TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0}, 2188}; 2189 2190static void __init tegra114_clock_apply_init_table(void) 2191{ 2192 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); 2193} 2194 2195 2196/** 2197 * tegra114_car_barrier - wait for pending writes to the CAR to complete 2198 * 2199 * Wait for any outstanding writes to the CAR MMIO space from this CPU 2200 * to complete before continuing execution. No return value. 2201 */ 2202static void tegra114_car_barrier(void) 2203{ 2204 wmb(); /* probably unnecessary */ 2205 readl_relaxed(clk_base + CPU_FINETRIM_SELECT); 2206} 2207 2208/** 2209 * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays 2210 * 2211 * When the CPU rail voltage is in the high-voltage range, use the 2212 * built-in hardwired clock propagation delays in the CPU clock 2213 * shaper. No return value. 2214 */ 2215void tegra114_clock_tune_cpu_trimmers_high(void) 2216{ 2217 u32 select = 0; 2218 2219 /* Use hardwired rise->rise & fall->fall clock propagation delays */ 2220 select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2221 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2222 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2223 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 2224 2225 tegra114_car_barrier(); 2226} 2227EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high); 2228 2229/** 2230 * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays 2231 * 2232 * When the CPU rail voltage is in the low-voltage range, use the 2233 * extended clock propagation delays set by 2234 * tegra114_clock_tune_cpu_trimmers_init(). The intention is to 2235 * maintain the input clock duty cycle that the FCPU subsystem 2236 * expects. No return value. 2237 */ 2238void tegra114_clock_tune_cpu_trimmers_low(void) 2239{ 2240 u32 select = 0; 2241 2242 /* 2243 * Use software-specified rise->rise & fall->fall clock 2244 * propagation delays (from 2245 * tegra114_clock_tune_cpu_trimmers_init() 2246 */ 2247 select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2248 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2249 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2250 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); 2251 2252 tegra114_car_barrier(); 2253} 2254EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low); 2255 2256/** 2257 * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays 2258 * 2259 * Program extended clock propagation delays into the FCPU clock 2260 * shaper and enable them. XXX Define the purpose - peak current 2261 * reduction? No return value. 2262 */ 2263/* XXX Initial voltage rail state assumption issues? */ 2264void tegra114_clock_tune_cpu_trimmers_init(void) 2265{ 2266 u32 dr = 0, r = 0; 2267 2268 /* Increment the rise->rise clock delay by four steps */ 2269 r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK | 2270 CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK | 2271 CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK); 2272 writel_relaxed(r, clk_base + CPU_FINETRIM_R); 2273 2274 /* 2275 * Use the rise->rise clock propagation delay specified in the 2276 * r field 2277 */ 2278 dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 | 2279 CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 | 2280 CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6); 2281 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); 2282 2283 tegra114_clock_tune_cpu_trimmers_low(); 2284} 2285EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init); 2286 2287/** 2288 * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset 2289 * 2290 * Assert the reset line of the DFLL's DVCO. No return value. 2291 */ 2292void tegra114_clock_assert_dfll_dvco_reset(void) 2293{ 2294 u32 v; 2295 2296 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 2297 v |= (1 << DVFS_DFLL_RESET_SHIFT); 2298 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 2299 tegra114_car_barrier(); 2300} 2301EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset); 2302 2303/** 2304 * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset 2305 * 2306 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to 2307 * operate. No return value. 2308 */ 2309void tegra114_clock_deassert_dfll_dvco_reset(void) 2310{ 2311 u32 v; 2312 2313 v = readl_relaxed(clk_base + RST_DFLL_DVCO); 2314 v &= ~(1 << DVFS_DFLL_RESET_SHIFT); 2315 writel_relaxed(v, clk_base + RST_DFLL_DVCO); 2316 tegra114_car_barrier(); 2317} 2318EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset); 2319 2320static void __init tegra114_clock_init(struct device_node *np) 2321{ 2322 struct device_node *node; 2323 int i; 2324 2325 clk_base = of_iomap(np, 0); 2326 if (!clk_base) { 2327 pr_err("ioremap tegra114 CAR failed\n"); 2328 return; 2329 } 2330 2331 node = of_find_matching_node(NULL, pmc_match); 2332 if (!node) { 2333 pr_err("Failed to find pmc node\n"); 2334 WARN_ON(1); 2335 return; 2336 } 2337 2338 pmc_base = of_iomap(node, 0); 2339 if (!pmc_base) { 2340 pr_err("Can't map pmc registers\n"); 2341 WARN_ON(1); 2342 return; 2343 } 2344 2345 if (tegra114_osc_clk_init(clk_base) < 0) 2346 return; 2347 2348 tegra114_fixed_clk_init(clk_base); 2349 tegra114_pll_init(clk_base, pmc_base); 2350 tegra114_periph_clk_init(clk_base); 2351 tegra114_audio_clk_init(clk_base); 2352 tegra114_pmc_clk_init(pmc_base); 2353 tegra114_super_clk_init(clk_base); 2354 2355 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2356 if (IS_ERR(clks[i])) { 2357 pr_err 2358 ("Tegra114 clk %d: register failed with %ld\n", 2359 i, PTR_ERR(clks[i])); 2360 } 2361 if (!clks[i]) 2362 clks[i] = ERR_PTR(-EINVAL); 2363 } 2364 2365 clk_data.clks = clks; 2366 clk_data.clk_num = ARRAY_SIZE(clks); 2367 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2368 2369 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 2370 2371 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 2372} 2373CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); 2374